1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "intel_display_types.h" 25 #include "intel_dp.h" 26 #include "intel_dp_link_training.h" 27 28 static void 29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE]) 30 { 31 32 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", 33 link_status[0], link_status[1], link_status[2], 34 link_status[3], link_status[4], link_status[5]); 35 } 36 37 void intel_dp_get_adjust_train(struct intel_dp *intel_dp, 38 const u8 link_status[DP_LINK_STATUS_SIZE]) 39 { 40 u8 v = 0; 41 u8 p = 0; 42 int lane; 43 u8 voltage_max; 44 u8 preemph_max; 45 46 for (lane = 0; lane < intel_dp->lane_count; lane++) { 47 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 48 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 49 50 if (this_v > v) 51 v = this_v; 52 if (this_p > p) 53 p = this_p; 54 } 55 56 voltage_max = intel_dp_voltage_max(intel_dp); 57 if (v >= voltage_max) 58 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 59 60 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 61 if (p >= preemph_max) 62 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 63 64 for (lane = 0; lane < 4; lane++) 65 intel_dp->train_set[lane] = v | p; 66 } 67 68 static bool 69 intel_dp_set_link_train(struct intel_dp *intel_dp, 70 u8 dp_train_pat) 71 { 72 u8 buf[sizeof(intel_dp->train_set) + 1]; 73 int ret, len; 74 75 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat); 76 77 buf[0] = dp_train_pat; 78 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 79 DP_TRAINING_PATTERN_DISABLE) { 80 /* don't write DP_TRAINING_LANEx_SET on disable */ 81 len = 1; 82 } else { 83 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 84 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 85 len = intel_dp->lane_count + 1; 86 } 87 88 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 89 buf, len); 90 91 return ret == len; 92 } 93 94 static bool 95 intel_dp_reset_link_train(struct intel_dp *intel_dp, 96 u8 dp_train_pat) 97 { 98 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 99 intel_dp_set_signal_levels(intel_dp); 100 return intel_dp_set_link_train(intel_dp, dp_train_pat); 101 } 102 103 static bool 104 intel_dp_update_link_train(struct intel_dp *intel_dp) 105 { 106 int ret; 107 108 intel_dp_set_signal_levels(intel_dp); 109 110 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 111 intel_dp->train_set, intel_dp->lane_count); 112 113 return ret == intel_dp->lane_count; 114 } 115 116 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp) 117 { 118 int lane; 119 120 for (lane = 0; lane < intel_dp->lane_count; lane++) 121 if ((intel_dp->train_set[lane] & 122 DP_TRAIN_MAX_SWING_REACHED) == 0) 123 return false; 124 125 return true; 126 } 127 128 /* Enable corresponding port and start training pattern 1 */ 129 static bool 130 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) 131 { 132 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 133 u8 voltage; 134 int voltage_tries, cr_tries, max_cr_tries; 135 bool max_vswing_reached = false; 136 u8 link_config[2]; 137 u8 link_bw, rate_select; 138 139 if (intel_dp->prepare_link_retrain) 140 intel_dp->prepare_link_retrain(intel_dp); 141 142 intel_dp_compute_rate(intel_dp, intel_dp->link_rate, 143 &link_bw, &rate_select); 144 145 if (link_bw) 146 drm_dbg_kms(&i915->drm, 147 "Using LINK_BW_SET value %02x\n", link_bw); 148 else 149 drm_dbg_kms(&i915->drm, 150 "Using LINK_RATE_SET value %02x\n", rate_select); 151 152 /* Write the link configuration data */ 153 link_config[0] = link_bw; 154 link_config[1] = intel_dp->lane_count; 155 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 156 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 157 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 158 159 /* eDP 1.4 rate select method. */ 160 if (!link_bw) 161 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 162 &rate_select, 1); 163 164 link_config[0] = 0; 165 link_config[1] = DP_SET_ANSI_8B10B; 166 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 167 168 intel_dp->DP |= DP_PORT_EN; 169 170 /* clock recovery */ 171 if (!intel_dp_reset_link_train(intel_dp, 172 DP_TRAINING_PATTERN_1 | 173 DP_LINK_SCRAMBLING_DISABLE)) { 174 drm_err(&i915->drm, "failed to enable link training\n"); 175 return false; 176 } 177 178 /* 179 * The DP 1.4 spec defines the max clock recovery retries value 180 * as 10 but for pre-DP 1.4 devices we set a very tolerant 181 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 182 * x 5 identical voltage retries). Since the previous specs didn't 183 * define a limit and created the possibility of an infinite loop 184 * we want to prevent any sync from triggering that corner case. 185 */ 186 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 187 max_cr_tries = 10; 188 else 189 max_cr_tries = 80; 190 191 voltage_tries = 1; 192 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 193 u8 link_status[DP_LINK_STATUS_SIZE]; 194 195 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 196 197 if (!intel_dp_get_link_status(intel_dp, link_status)) { 198 drm_err(&i915->drm, "failed to get link status\n"); 199 return false; 200 } 201 202 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 203 drm_dbg_kms(&i915->drm, "clock recovery OK\n"); 204 return true; 205 } 206 207 if (voltage_tries == 5) { 208 drm_dbg_kms(&i915->drm, 209 "Same voltage tried 5 times\n"); 210 return false; 211 } 212 213 if (max_vswing_reached) { 214 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); 215 return false; 216 } 217 218 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 219 220 /* Update training set as requested by target */ 221 intel_dp_get_adjust_train(intel_dp, link_status); 222 if (!intel_dp_update_link_train(intel_dp)) { 223 drm_err(&i915->drm, 224 "failed to update link training\n"); 225 return false; 226 } 227 228 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 229 voltage) 230 ++voltage_tries; 231 else 232 voltage_tries = 1; 233 234 if (intel_dp_link_max_vswing_reached(intel_dp)) 235 max_vswing_reached = true; 236 237 } 238 drm_err(&i915->drm, 239 "Failed clock recovery %d times, giving up!\n", max_cr_tries); 240 return false; 241 } 242 243 /* 244 * Pick training pattern for channel equalization. Training pattern 4 for HBR3 245 * or for 1.4 devices that support it, training Pattern 3 for HBR2 246 * or 1.2 devices that support it, Training Pattern 2 otherwise. 247 */ 248 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) 249 { 250 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 251 252 /* 253 * Intel platforms that support HBR3 also support TPS4. It is mandatory 254 * for all downstream devices that support HBR3. There are no known eDP 255 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 256 * specification. 257 */ 258 source_tps4 = intel_dp_source_supports_hbr3(intel_dp); 259 sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd); 260 if (source_tps4 && sink_tps4) { 261 return DP_TRAINING_PATTERN_4; 262 } else if (intel_dp->link_rate == 810000) { 263 if (!source_tps4) 264 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 265 "8.1 Gbps link rate without source HBR3/TPS4 support\n"); 266 if (!sink_tps4) 267 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 268 "8.1 Gbps link rate without sink TPS4 support\n"); 269 } 270 /* 271 * Intel platforms that support HBR2 also support TPS3. TPS3 support is 272 * also mandatory for downstream devices that support HBR2. However, not 273 * all sinks follow the spec. 274 */ 275 source_tps3 = intel_dp_source_supports_hbr2(intel_dp); 276 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); 277 if (source_tps3 && sink_tps3) { 278 return DP_TRAINING_PATTERN_3; 279 } else if (intel_dp->link_rate >= 540000) { 280 if (!source_tps3) 281 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 282 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); 283 if (!sink_tps3) 284 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 285 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 286 } 287 288 return DP_TRAINING_PATTERN_2; 289 } 290 291 static bool 292 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) 293 { 294 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 295 int tries; 296 u32 training_pattern; 297 u8 link_status[DP_LINK_STATUS_SIZE]; 298 bool channel_eq = false; 299 300 training_pattern = intel_dp_training_pattern(intel_dp); 301 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 302 if (training_pattern != DP_TRAINING_PATTERN_4) 303 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 304 305 /* channel equalization */ 306 if (!intel_dp_set_link_train(intel_dp, 307 training_pattern)) { 308 drm_err(&i915->drm, "failed to start channel equalization\n"); 309 return false; 310 } 311 312 for (tries = 0; tries < 5; tries++) { 313 314 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 315 if (!intel_dp_get_link_status(intel_dp, link_status)) { 316 drm_err(&i915->drm, 317 "failed to get link status\n"); 318 break; 319 } 320 321 /* Make sure clock is still ok */ 322 if (!drm_dp_clock_recovery_ok(link_status, 323 intel_dp->lane_count)) { 324 intel_dp_dump_link_status(link_status); 325 drm_dbg_kms(&i915->drm, 326 "Clock recovery check failed, cannot " 327 "continue channel equalization\n"); 328 break; 329 } 330 331 if (drm_dp_channel_eq_ok(link_status, 332 intel_dp->lane_count)) { 333 channel_eq = true; 334 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " 335 "successful\n"); 336 break; 337 } 338 339 /* Update training set as requested by target */ 340 intel_dp_get_adjust_train(intel_dp, link_status); 341 if (!intel_dp_update_link_train(intel_dp)) { 342 drm_err(&i915->drm, 343 "failed to update link training\n"); 344 break; 345 } 346 } 347 348 /* Try 5 times, else fail and try at lower BW */ 349 if (tries == 5) { 350 intel_dp_dump_link_status(link_status); 351 drm_dbg_kms(&i915->drm, 352 "Channel equalization failed 5 times\n"); 353 } 354 355 intel_dp_set_idle_link_train(intel_dp); 356 357 return channel_eq; 358 359 } 360 361 void intel_dp_stop_link_train(struct intel_dp *intel_dp) 362 { 363 intel_dp->link_trained = true; 364 365 intel_dp_set_link_train(intel_dp, 366 DP_TRAINING_PATTERN_DISABLE); 367 } 368 369 void 370 intel_dp_start_link_train(struct intel_dp *intel_dp) 371 { 372 struct intel_connector *intel_connector = intel_dp->attached_connector; 373 374 if (!intel_dp_link_training_clock_recovery(intel_dp)) 375 goto failure_handling; 376 if (!intel_dp_link_training_channel_equalization(intel_dp)) 377 goto failure_handling; 378 379 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 380 "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", 381 intel_connector->base.base.id, 382 intel_connector->base.name, 383 intel_dp->link_rate, intel_dp->lane_count); 384 return; 385 386 failure_handling: 387 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 388 "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", 389 intel_connector->base.base.id, 390 intel_connector->base.name, 391 intel_dp->link_rate, intel_dp->lane_count); 392 if (!intel_dp_get_link_train_fallback_values(intel_dp, 393 intel_dp->link_rate, 394 intel_dp->lane_count)) 395 /* Schedule a Hotplug Uevent to userspace to start modeset */ 396 schedule_work(&intel_connector->modeset_retry_work); 397 return; 398 } 399