1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc. 2 * Copyright 2020 NXP 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * ALTERNATIVELY, this software may be distributed under the terms of the 16 * GNU General Public License ("GPL") as published by the Free Software 17 * Foundation, either version 2 of that License or (at your option) any 18 * later version. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34 #include <linux/init.h> 35 #include <linux/module.h> 36 #include <linux/of_platform.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/io.h> 40 #include <linux/if_arp.h> 41 #include <linux/if_vlan.h> 42 #include <linux/icmp.h> 43 #include <linux/ip.h> 44 #include <linux/ipv6.h> 45 #include <linux/udp.h> 46 #include <linux/tcp.h> 47 #include <linux/net.h> 48 #include <linux/skbuff.h> 49 #include <linux/etherdevice.h> 50 #include <linux/if_ether.h> 51 #include <linux/highmem.h> 52 #include <linux/percpu.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/sort.h> 55 #include <linux/phy_fixed.h> 56 #include <soc/fsl/bman.h> 57 #include <soc/fsl/qman.h> 58 #include "fman.h" 59 #include "fman_port.h" 60 #include "mac.h" 61 #include "dpaa_eth.h" 62 63 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files 64 * using trace events only need to #include <trace/events/sched.h> 65 */ 66 #define CREATE_TRACE_POINTS 67 #include "dpaa_eth_trace.h" 68 69 static int debug = -1; 70 module_param(debug, int, 0444); 71 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)"); 72 73 static u16 tx_timeout = 1000; 74 module_param(tx_timeout, ushort, 0444); 75 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); 76 77 #define FM_FD_STAT_RX_ERRORS \ 78 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \ 79 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \ 80 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \ 81 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \ 82 FM_FD_ERR_PRS_HDR_ERR) 83 84 #define FM_FD_STAT_TX_ERRORS \ 85 (FM_FD_ERR_UNSUPPORTED_FORMAT | \ 86 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA) 87 88 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | \ 90 NETIF_MSG_IFDOWN) 91 92 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000 93 /* Ingress congestion threshold on FMan ports 94 * The size in bytes of the ingress tail-drop threshold on FMan ports. 95 * Traffic piling up above this value will be rejected by QMan and discarded 96 * by FMan. 97 */ 98 99 /* Size in bytes of the FQ taildrop threshold */ 100 #define DPAA_FQ_TD 0x200000 101 102 #define DPAA_CS_THRESHOLD_1G 0x06000000 103 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000 104 * The size in bytes of the egress Congestion State notification threshold on 105 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a 106 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"), 107 * and the larger the frame size, the more acute the problem. 108 * So we have to find a balance between these factors: 109 * - avoiding the device staying congested for a prolonged time (risking 110 * the netdev watchdog to fire - see also the tx_timeout module param); 111 * - affecting performance of protocols such as TCP, which otherwise 112 * behave well under the congestion notification mechanism; 113 * - preventing the Tx cores from tightly-looping (as if the congestion 114 * threshold was too low to be effective); 115 * - running out of memory if the CS threshold is set too high. 116 */ 117 118 #define DPAA_CS_THRESHOLD_10G 0x10000000 119 /* The size in bytes of the egress Congestion State notification threshold on 120 * 10G ports, range 0x1000 .. 0x10000000 121 */ 122 123 /* Largest value that the FQD's OAL field can hold */ 124 #define FSL_QMAN_MAX_OAL 127 125 126 /* Default alignment for start of data in an Rx FD */ 127 #ifdef CONFIG_DPAA_ERRATUM_A050385 128 /* aligning data start to 64 avoids DMA transaction splits, unless the buffer 129 * is crossing a 4k page boundary 130 */ 131 #define DPAA_FD_DATA_ALIGNMENT (fman_has_errata_a050385() ? 64 : 16) 132 /* aligning to 256 avoids DMA transaction splits caused by 4k page boundary 133 * crossings; also, all SG fragments except the last must have a size multiple 134 * of 256 to avoid DMA transaction splits 135 */ 136 #define DPAA_A050385_ALIGN 256 137 #define DPAA_FD_RX_DATA_ALIGNMENT (fman_has_errata_a050385() ? \ 138 DPAA_A050385_ALIGN : 16) 139 #else 140 #define DPAA_FD_DATA_ALIGNMENT 16 141 #define DPAA_FD_RX_DATA_ALIGNMENT DPAA_FD_DATA_ALIGNMENT 142 #endif 143 144 /* The DPAA requires 256 bytes reserved and mapped for the SGT */ 145 #define DPAA_SGT_SIZE 256 146 147 /* Values for the L3R field of the FM Parse Results 148 */ 149 /* L3 Type field: First IP Present IPv4 */ 150 #define FM_L3_PARSE_RESULT_IPV4 0x8000 151 /* L3 Type field: First IP Present IPv6 */ 152 #define FM_L3_PARSE_RESULT_IPV6 0x4000 153 /* Values for the L4R field of the FM Parse Results */ 154 /* L4 Type field: UDP */ 155 #define FM_L4_PARSE_RESULT_UDP 0x40 156 /* L4 Type field: TCP */ 157 #define FM_L4_PARSE_RESULT_TCP 0x20 158 159 /* FD status field indicating whether the FM Parser has attempted to validate 160 * the L4 csum of the frame. 161 * Note that having this bit set doesn't necessarily imply that the checksum 162 * is valid. One would have to check the parse results to find that out. 163 */ 164 #define FM_FD_STAT_L4CV 0x00000004 165 166 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 167 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */ 168 169 #define FSL_DPAA_BPID_INV 0xff 170 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128 171 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80 172 173 #define DPAA_TX_PRIV_DATA_SIZE 16 174 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result) 175 #define DPAA_TIME_STAMP_SIZE 8 176 #define DPAA_HASH_RESULTS_SIZE 8 177 #ifdef CONFIG_DPAA_ERRATUM_A050385 178 #define DPAA_RX_PRIV_DATA_SIZE (DPAA_A050385_ALIGN - (DPAA_PARSE_RESULTS_SIZE\ 179 + DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE)) 180 #else 181 #define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \ 182 dpaa_rx_extra_headroom) 183 #endif 184 185 #define DPAA_ETH_PCD_RXQ_NUM 128 186 187 #define DPAA_ENQUEUE_RETRIES 100000 188 189 enum port_type {RX, TX}; 190 191 struct fm_port_fqs { 192 struct dpaa_fq *tx_defq; 193 struct dpaa_fq *tx_errq; 194 struct dpaa_fq *rx_defq; 195 struct dpaa_fq *rx_errq; 196 struct dpaa_fq *rx_pcdq; 197 }; 198 199 /* All the dpa bps in use at any moment */ 200 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS]; 201 202 #define DPAA_BP_RAW_SIZE 4096 203 204 #ifdef CONFIG_DPAA_ERRATUM_A050385 205 #define dpaa_bp_size(raw_size) (SKB_WITH_OVERHEAD(raw_size) & \ 206 ~(DPAA_A050385_ALIGN - 1)) 207 #else 208 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size) 209 #endif 210 211 static int dpaa_max_frm; 212 213 static int dpaa_rx_extra_headroom; 214 215 #define dpaa_get_max_mtu() \ 216 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN)) 217 218 static int dpaa_netdev_init(struct net_device *net_dev, 219 const struct net_device_ops *dpaa_ops, 220 u16 tx_timeout) 221 { 222 struct dpaa_priv *priv = netdev_priv(net_dev); 223 struct device *dev = net_dev->dev.parent; 224 struct dpaa_percpu_priv *percpu_priv; 225 const u8 *mac_addr; 226 int i, err; 227 228 /* Although we access another CPU's private data here 229 * we do it at initialization so it is safe 230 */ 231 for_each_possible_cpu(i) { 232 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 233 percpu_priv->net_dev = net_dev; 234 } 235 236 net_dev->netdev_ops = dpaa_ops; 237 mac_addr = priv->mac_dev->addr; 238 239 net_dev->mem_start = priv->mac_dev->res->start; 240 net_dev->mem_end = priv->mac_dev->res->end; 241 242 net_dev->min_mtu = ETH_MIN_MTU; 243 net_dev->max_mtu = dpaa_get_max_mtu(); 244 245 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 246 NETIF_F_LLTX | NETIF_F_RXHASH); 247 248 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA; 249 /* The kernels enables GSO automatically, if we declare NETIF_F_SG. 250 * For conformity, we'll still declare GSO explicitly. 251 */ 252 net_dev->features |= NETIF_F_GSO; 253 net_dev->features |= NETIF_F_RXCSUM; 254 255 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 256 /* we do not want shared skbs on TX */ 257 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING; 258 259 net_dev->features |= net_dev->hw_features; 260 net_dev->vlan_features = net_dev->features; 261 262 if (is_valid_ether_addr(mac_addr)) { 263 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len); 264 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); 265 } else { 266 eth_hw_addr_random(net_dev); 267 err = priv->mac_dev->change_addr(priv->mac_dev->fman_mac, 268 (enet_addr_t *)net_dev->dev_addr); 269 if (err) { 270 dev_err(dev, "Failed to set random MAC address\n"); 271 return -EINVAL; 272 } 273 dev_info(dev, "Using random MAC address: %pM\n", 274 net_dev->dev_addr); 275 } 276 277 net_dev->ethtool_ops = &dpaa_ethtool_ops; 278 279 net_dev->needed_headroom = priv->tx_headroom; 280 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout); 281 282 /* start without the RUNNING flag, phylib controls it later */ 283 netif_carrier_off(net_dev); 284 285 err = register_netdev(net_dev); 286 if (err < 0) { 287 dev_err(dev, "register_netdev() = %d\n", err); 288 return err; 289 } 290 291 return 0; 292 } 293 294 static int dpaa_stop(struct net_device *net_dev) 295 { 296 struct mac_device *mac_dev; 297 struct dpaa_priv *priv; 298 int i, err, error; 299 300 priv = netdev_priv(net_dev); 301 mac_dev = priv->mac_dev; 302 303 netif_tx_stop_all_queues(net_dev); 304 /* Allow the Fman (Tx) port to process in-flight frames before we 305 * try switching it off. 306 */ 307 msleep(200); 308 309 err = mac_dev->stop(mac_dev); 310 if (err < 0) 311 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n", 312 err); 313 314 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 315 error = fman_port_disable(mac_dev->port[i]); 316 if (error) 317 err = error; 318 } 319 320 if (net_dev->phydev) 321 phy_disconnect(net_dev->phydev); 322 net_dev->phydev = NULL; 323 324 msleep(200); 325 326 return err; 327 } 328 329 static void dpaa_tx_timeout(struct net_device *net_dev, unsigned int txqueue) 330 { 331 struct dpaa_percpu_priv *percpu_priv; 332 const struct dpaa_priv *priv; 333 334 priv = netdev_priv(net_dev); 335 percpu_priv = this_cpu_ptr(priv->percpu_priv); 336 337 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n", 338 jiffies_to_msecs(jiffies - dev_trans_start(net_dev))); 339 340 percpu_priv->stats.tx_errors++; 341 } 342 343 /* Calculates the statistics for the given device by adding the statistics 344 * collected by each CPU. 345 */ 346 static void dpaa_get_stats64(struct net_device *net_dev, 347 struct rtnl_link_stats64 *s) 348 { 349 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64); 350 struct dpaa_priv *priv = netdev_priv(net_dev); 351 struct dpaa_percpu_priv *percpu_priv; 352 u64 *netstats = (u64 *)s; 353 u64 *cpustats; 354 int i, j; 355 356 for_each_possible_cpu(i) { 357 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 358 359 cpustats = (u64 *)&percpu_priv->stats; 360 361 /* add stats from all CPUs */ 362 for (j = 0; j < numstats; j++) 363 netstats[j] += cpustats[j]; 364 } 365 } 366 367 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type, 368 void *type_data) 369 { 370 struct dpaa_priv *priv = netdev_priv(net_dev); 371 struct tc_mqprio_qopt *mqprio = type_data; 372 u8 num_tc; 373 int i; 374 375 if (type != TC_SETUP_QDISC_MQPRIO) 376 return -EOPNOTSUPP; 377 378 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 379 num_tc = mqprio->num_tc; 380 381 if (num_tc == priv->num_tc) 382 return 0; 383 384 if (!num_tc) { 385 netdev_reset_tc(net_dev); 386 goto out; 387 } 388 389 if (num_tc > DPAA_TC_NUM) { 390 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n", 391 DPAA_TC_NUM); 392 return -EINVAL; 393 } 394 395 netdev_set_num_tc(net_dev, num_tc); 396 397 for (i = 0; i < num_tc; i++) 398 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM, 399 i * DPAA_TC_TXQ_NUM); 400 401 out: 402 priv->num_tc = num_tc ? : 1; 403 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 404 return 0; 405 } 406 407 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev) 408 { 409 struct dpaa_eth_data *eth_data; 410 struct device *dpaa_dev; 411 struct mac_device *mac_dev; 412 413 dpaa_dev = &pdev->dev; 414 eth_data = dpaa_dev->platform_data; 415 if (!eth_data) { 416 dev_err(dpaa_dev, "eth_data missing\n"); 417 return ERR_PTR(-ENODEV); 418 } 419 mac_dev = eth_data->mac_dev; 420 if (!mac_dev) { 421 dev_err(dpaa_dev, "mac_dev missing\n"); 422 return ERR_PTR(-EINVAL); 423 } 424 425 return mac_dev; 426 } 427 428 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr) 429 { 430 const struct dpaa_priv *priv; 431 struct mac_device *mac_dev; 432 struct sockaddr old_addr; 433 int err; 434 435 priv = netdev_priv(net_dev); 436 437 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN); 438 439 err = eth_mac_addr(net_dev, addr); 440 if (err < 0) { 441 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err); 442 return err; 443 } 444 445 mac_dev = priv->mac_dev; 446 447 err = mac_dev->change_addr(mac_dev->fman_mac, 448 (enet_addr_t *)net_dev->dev_addr); 449 if (err < 0) { 450 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n", 451 err); 452 /* reverting to previous address */ 453 eth_mac_addr(net_dev, &old_addr); 454 455 return err; 456 } 457 458 return 0; 459 } 460 461 static void dpaa_set_rx_mode(struct net_device *net_dev) 462 { 463 const struct dpaa_priv *priv; 464 int err; 465 466 priv = netdev_priv(net_dev); 467 468 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) { 469 priv->mac_dev->promisc = !priv->mac_dev->promisc; 470 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac, 471 priv->mac_dev->promisc); 472 if (err < 0) 473 netif_err(priv, drv, net_dev, 474 "mac_dev->set_promisc() = %d\n", 475 err); 476 } 477 478 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) { 479 priv->mac_dev->allmulti = !priv->mac_dev->allmulti; 480 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac, 481 priv->mac_dev->allmulti); 482 if (err < 0) 483 netif_err(priv, drv, net_dev, 484 "mac_dev->set_allmulti() = %d\n", 485 err); 486 } 487 488 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev); 489 if (err < 0) 490 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n", 491 err); 492 } 493 494 static struct dpaa_bp *dpaa_bpid2pool(int bpid) 495 { 496 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS)) 497 return NULL; 498 499 return dpaa_bp_array[bpid]; 500 } 501 502 /* checks if this bpool is already allocated */ 503 static bool dpaa_bpid2pool_use(int bpid) 504 { 505 if (dpaa_bpid2pool(bpid)) { 506 refcount_inc(&dpaa_bp_array[bpid]->refs); 507 return true; 508 } 509 510 return false; 511 } 512 513 /* called only once per bpid by dpaa_bp_alloc_pool() */ 514 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp) 515 { 516 dpaa_bp_array[bpid] = dpaa_bp; 517 refcount_set(&dpaa_bp->refs, 1); 518 } 519 520 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp) 521 { 522 int err; 523 524 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) { 525 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n", 526 __func__); 527 return -EINVAL; 528 } 529 530 /* If the pool is already specified, we only create one per bpid */ 531 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV && 532 dpaa_bpid2pool_use(dpaa_bp->bpid)) 533 return 0; 534 535 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) { 536 dpaa_bp->pool = bman_new_pool(); 537 if (!dpaa_bp->pool) { 538 pr_err("%s: bman_new_pool() failed\n", 539 __func__); 540 return -ENODEV; 541 } 542 543 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool); 544 } 545 546 if (dpaa_bp->seed_cb) { 547 err = dpaa_bp->seed_cb(dpaa_bp); 548 if (err) 549 goto pool_seed_failed; 550 } 551 552 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp); 553 554 return 0; 555 556 pool_seed_failed: 557 pr_err("%s: pool seeding failed\n", __func__); 558 bman_free_pool(dpaa_bp->pool); 559 560 return err; 561 } 562 563 /* remove and free all the buffers from the given buffer pool */ 564 static void dpaa_bp_drain(struct dpaa_bp *bp) 565 { 566 u8 num = 8; 567 int ret; 568 569 do { 570 struct bm_buffer bmb[8]; 571 int i; 572 573 ret = bman_acquire(bp->pool, bmb, num); 574 if (ret < 0) { 575 if (num == 8) { 576 /* we have less than 8 buffers left; 577 * drain them one by one 578 */ 579 num = 1; 580 ret = 1; 581 continue; 582 } else { 583 /* Pool is fully drained */ 584 break; 585 } 586 } 587 588 if (bp->free_buf_cb) 589 for (i = 0; i < num; i++) 590 bp->free_buf_cb(bp, &bmb[i]); 591 } while (ret > 0); 592 } 593 594 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp) 595 { 596 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid); 597 598 /* the mapping between bpid and dpaa_bp is done very late in the 599 * allocation procedure; if something failed before the mapping, the bp 600 * was not configured, therefore we don't need the below instructions 601 */ 602 if (!bp) 603 return; 604 605 if (!refcount_dec_and_test(&bp->refs)) 606 return; 607 608 if (bp->free_buf_cb) 609 dpaa_bp_drain(bp); 610 611 dpaa_bp_array[bp->bpid] = NULL; 612 bman_free_pool(bp->pool); 613 } 614 615 static void dpaa_bps_free(struct dpaa_priv *priv) 616 { 617 dpaa_bp_free(priv->dpaa_bp); 618 } 619 620 /* Use multiple WQs for FQ assignment: 621 * - Tx Confirmation queues go to WQ1. 622 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance 623 * to be scheduled, in case there are many more FQs in WQ6). 624 * - Rx Default goes to WQ6. 625 * - Tx queues go to different WQs depending on their priority. Equal 626 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and 627 * WQ0 (highest priority). 628 * This ensures that Tx-confirmed buffers are timely released. In particular, 629 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they 630 * are greatly outnumbered by other FQs in the system, while 631 * dequeue scheduling is round-robin. 632 */ 633 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx) 634 { 635 switch (fq->fq_type) { 636 case FQ_TYPE_TX_CONFIRM: 637 case FQ_TYPE_TX_CONF_MQ: 638 fq->wq = 1; 639 break; 640 case FQ_TYPE_RX_ERROR: 641 case FQ_TYPE_TX_ERROR: 642 fq->wq = 5; 643 break; 644 case FQ_TYPE_RX_DEFAULT: 645 case FQ_TYPE_RX_PCD: 646 fq->wq = 6; 647 break; 648 case FQ_TYPE_TX: 649 switch (idx / DPAA_TC_TXQ_NUM) { 650 case 0: 651 /* Low priority (best effort) */ 652 fq->wq = 6; 653 break; 654 case 1: 655 /* Medium priority */ 656 fq->wq = 2; 657 break; 658 case 2: 659 /* High priority */ 660 fq->wq = 1; 661 break; 662 case 3: 663 /* Very high priority */ 664 fq->wq = 0; 665 break; 666 default: 667 WARN(1, "Too many TX FQs: more than %d!\n", 668 DPAA_ETH_TXQ_NUM); 669 } 670 break; 671 default: 672 WARN(1, "Invalid FQ type %d for FQID %d!\n", 673 fq->fq_type, fq->fqid); 674 } 675 } 676 677 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev, 678 u32 start, u32 count, 679 struct list_head *list, 680 enum dpaa_fq_type fq_type) 681 { 682 struct dpaa_fq *dpaa_fq; 683 int i; 684 685 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq), 686 GFP_KERNEL); 687 if (!dpaa_fq) 688 return NULL; 689 690 for (i = 0; i < count; i++) { 691 dpaa_fq[i].fq_type = fq_type; 692 dpaa_fq[i].fqid = start ? start + i : 0; 693 list_add_tail(&dpaa_fq[i].list, list); 694 } 695 696 for (i = 0; i < count; i++) 697 dpaa_assign_wq(dpaa_fq + i, i); 698 699 return dpaa_fq; 700 } 701 702 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list, 703 struct fm_port_fqs *port_fqs) 704 { 705 struct dpaa_fq *dpaa_fq; 706 u32 fq_base, fq_base_aligned, i; 707 708 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR); 709 if (!dpaa_fq) 710 goto fq_alloc_failed; 711 712 port_fqs->rx_errq = &dpaa_fq[0]; 713 714 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT); 715 if (!dpaa_fq) 716 goto fq_alloc_failed; 717 718 port_fqs->rx_defq = &dpaa_fq[0]; 719 720 /* the PCD FQIDs range needs to be aligned for correct operation */ 721 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM)) 722 goto fq_alloc_failed; 723 724 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM); 725 726 for (i = fq_base; i < fq_base_aligned; i++) 727 qman_release_fqid(i); 728 729 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM; 730 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++) 731 qman_release_fqid(i); 732 733 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM, 734 list, FQ_TYPE_RX_PCD); 735 if (!dpaa_fq) 736 goto fq_alloc_failed; 737 738 port_fqs->rx_pcdq = &dpaa_fq[0]; 739 740 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ)) 741 goto fq_alloc_failed; 742 743 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR); 744 if (!dpaa_fq) 745 goto fq_alloc_failed; 746 747 port_fqs->tx_errq = &dpaa_fq[0]; 748 749 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM); 750 if (!dpaa_fq) 751 goto fq_alloc_failed; 752 753 port_fqs->tx_defq = &dpaa_fq[0]; 754 755 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX)) 756 goto fq_alloc_failed; 757 758 return 0; 759 760 fq_alloc_failed: 761 dev_err(dev, "dpaa_fq_alloc() failed\n"); 762 return -ENOMEM; 763 } 764 765 static u32 rx_pool_channel; 766 static DEFINE_SPINLOCK(rx_pool_channel_init); 767 768 static int dpaa_get_channel(void) 769 { 770 spin_lock(&rx_pool_channel_init); 771 if (!rx_pool_channel) { 772 u32 pool; 773 int ret; 774 775 ret = qman_alloc_pool(&pool); 776 777 if (!ret) 778 rx_pool_channel = pool; 779 } 780 spin_unlock(&rx_pool_channel_init); 781 if (!rx_pool_channel) 782 return -ENOMEM; 783 return rx_pool_channel; 784 } 785 786 static void dpaa_release_channel(void) 787 { 788 qman_release_pool(rx_pool_channel); 789 } 790 791 static void dpaa_eth_add_channel(u16 channel, struct device *dev) 792 { 793 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel); 794 const cpumask_t *cpus = qman_affine_cpus(); 795 struct qman_portal *portal; 796 int cpu; 797 798 for_each_cpu_and(cpu, cpus, cpu_online_mask) { 799 portal = qman_get_affine_portal(cpu); 800 qman_p_static_dequeue_add(portal, pool); 801 qman_start_using_portal(portal, dev); 802 } 803 } 804 805 /* Congestion group state change notification callback. 806 * Stops the device's egress queues while they are congested and 807 * wakes them upon exiting congested state. 808 * Also updates some CGR-related stats. 809 */ 810 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr, 811 int congested) 812 { 813 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr, 814 struct dpaa_priv, cgr_data.cgr); 815 816 if (congested) { 817 priv->cgr_data.congestion_start_jiffies = jiffies; 818 netif_tx_stop_all_queues(priv->net_dev); 819 priv->cgr_data.cgr_congested_count++; 820 } else { 821 priv->cgr_data.congested_jiffies += 822 (jiffies - priv->cgr_data.congestion_start_jiffies); 823 netif_tx_wake_all_queues(priv->net_dev); 824 } 825 } 826 827 static int dpaa_eth_cgr_init(struct dpaa_priv *priv) 828 { 829 struct qm_mcc_initcgr initcgr; 830 u32 cs_th; 831 int err; 832 833 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid); 834 if (err < 0) { 835 if (netif_msg_drv(priv)) 836 pr_err("%s: Error %d allocating CGR ID\n", 837 __func__, err); 838 goto out_error; 839 } 840 priv->cgr_data.cgr.cb = dpaa_eth_cgscn; 841 842 /* Enable Congestion State Change Notifications and CS taildrop */ 843 memset(&initcgr, 0, sizeof(initcgr)); 844 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES); 845 initcgr.cgr.cscn_en = QM_CGR_EN; 846 847 /* Set different thresholds based on the MAC speed. 848 * This may turn suboptimal if the MAC is reconfigured at a speed 849 * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link. 850 * In such cases, we ought to reconfigure the threshold, too. 851 */ 852 if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full) 853 cs_th = DPAA_CS_THRESHOLD_10G; 854 else 855 cs_th = DPAA_CS_THRESHOLD_1G; 856 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 857 858 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 859 initcgr.cgr.cstd_en = QM_CGR_EN; 860 861 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT, 862 &initcgr); 863 if (err < 0) { 864 if (netif_msg_drv(priv)) 865 pr_err("%s: Error %d creating CGR with ID %d\n", 866 __func__, err, priv->cgr_data.cgr.cgrid); 867 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 868 goto out_error; 869 } 870 if (netif_msg_drv(priv)) 871 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n", 872 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr, 873 priv->cgr_data.cgr.chan); 874 875 out_error: 876 return err; 877 } 878 879 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv, 880 struct dpaa_fq *fq, 881 const struct qman_fq *template) 882 { 883 fq->fq_base = *template; 884 fq->net_dev = priv->net_dev; 885 886 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; 887 fq->channel = priv->channel; 888 } 889 890 static inline void dpaa_setup_egress(const struct dpaa_priv *priv, 891 struct dpaa_fq *fq, 892 struct fman_port *port, 893 const struct qman_fq *template) 894 { 895 fq->fq_base = *template; 896 fq->net_dev = priv->net_dev; 897 898 if (port) { 899 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; 900 fq->channel = (u16)fman_port_get_qman_channel_id(port); 901 } else { 902 fq->flags = QMAN_FQ_FLAG_NO_MODIFY; 903 } 904 } 905 906 static void dpaa_fq_setup(struct dpaa_priv *priv, 907 const struct dpaa_fq_cbs *fq_cbs, 908 struct fman_port *tx_port) 909 { 910 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu; 911 const cpumask_t *affine_cpus = qman_affine_cpus(); 912 u16 channels[NR_CPUS]; 913 struct dpaa_fq *fq; 914 915 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask) 916 channels[num_portals++] = qman_affine_channel(cpu); 917 918 if (num_portals == 0) 919 dev_err(priv->net_dev->dev.parent, 920 "No Qman software (affine) channels found\n"); 921 922 /* Initialize each FQ in the list */ 923 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 924 switch (fq->fq_type) { 925 case FQ_TYPE_RX_DEFAULT: 926 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 927 break; 928 case FQ_TYPE_RX_ERROR: 929 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq); 930 break; 931 case FQ_TYPE_RX_PCD: 932 if (!num_portals) 933 continue; 934 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 935 fq->channel = channels[portal_cnt++ % num_portals]; 936 break; 937 case FQ_TYPE_TX: 938 dpaa_setup_egress(priv, fq, tx_port, 939 &fq_cbs->egress_ern); 940 /* If we have more Tx queues than the number of cores, 941 * just ignore the extra ones. 942 */ 943 if (egress_cnt < DPAA_ETH_TXQ_NUM) 944 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 945 break; 946 case FQ_TYPE_TX_CONF_MQ: 947 priv->conf_fqs[conf_cnt++] = &fq->fq_base; 948 /* fall through */ 949 case FQ_TYPE_TX_CONFIRM: 950 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq); 951 break; 952 case FQ_TYPE_TX_ERROR: 953 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq); 954 break; 955 default: 956 dev_warn(priv->net_dev->dev.parent, 957 "Unknown FQ type detected!\n"); 958 break; 959 } 960 } 961 962 /* Make sure all CPUs receive a corresponding Tx queue. */ 963 while (egress_cnt < DPAA_ETH_TXQ_NUM) { 964 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 965 if (fq->fq_type != FQ_TYPE_TX) 966 continue; 967 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 968 if (egress_cnt == DPAA_ETH_TXQ_NUM) 969 break; 970 } 971 } 972 } 973 974 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv, 975 struct qman_fq *tx_fq) 976 { 977 int i; 978 979 for (i = 0; i < DPAA_ETH_TXQ_NUM; i++) 980 if (priv->egress_fqs[i] == tx_fq) 981 return i; 982 983 return -EINVAL; 984 } 985 986 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable) 987 { 988 const struct dpaa_priv *priv; 989 struct qman_fq *confq = NULL; 990 struct qm_mcc_initfq initfq; 991 struct device *dev; 992 struct qman_fq *fq; 993 int queue_id; 994 int err; 995 996 priv = netdev_priv(dpaa_fq->net_dev); 997 dev = dpaa_fq->net_dev->dev.parent; 998 999 if (dpaa_fq->fqid == 0) 1000 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 1001 1002 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY); 1003 1004 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base); 1005 if (err) { 1006 dev_err(dev, "qman_create_fq() failed\n"); 1007 return err; 1008 } 1009 fq = &dpaa_fq->fq_base; 1010 1011 if (dpaa_fq->init) { 1012 memset(&initfq, 0, sizeof(initfq)); 1013 1014 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL); 1015 /* Note: we may get to keep an empty FQ in cache */ 1016 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE); 1017 1018 /* Try to reduce the number of portal interrupts for 1019 * Tx Confirmation FQs. 1020 */ 1021 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM) 1022 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK); 1023 1024 /* FQ placement */ 1025 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ); 1026 1027 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq); 1028 1029 /* Put all egress queues in a congestion group of their own. 1030 * Sensu stricto, the Tx confirmation queues are Rx FQs, 1031 * rather than Tx - but they nonetheless account for the 1032 * memory footprint on behalf of egress traffic. We therefore 1033 * place them in the netdev's CGR, along with the Tx FQs. 1034 */ 1035 if (dpaa_fq->fq_type == FQ_TYPE_TX || 1036 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM || 1037 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) { 1038 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1039 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1040 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid; 1041 /* Set a fixed overhead accounting, in an attempt to 1042 * reduce the impact of fixed-size skb shells and the 1043 * driver's needed headroom on system memory. This is 1044 * especially the case when the egress traffic is 1045 * composed of small datagrams. 1046 * Unfortunately, QMan's OAL value is capped to an 1047 * insufficient value, but even that is better than 1048 * no overhead accounting at all. 1049 */ 1050 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1051 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1052 qm_fqd_set_oal(&initfq.fqd, 1053 min(sizeof(struct sk_buff) + 1054 priv->tx_headroom, 1055 (size_t)FSL_QMAN_MAX_OAL)); 1056 } 1057 1058 if (td_enable) { 1059 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH); 1060 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1); 1061 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE); 1062 } 1063 1064 if (dpaa_fq->fq_type == FQ_TYPE_TX) { 1065 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base); 1066 if (queue_id >= 0) 1067 confq = priv->conf_fqs[queue_id]; 1068 if (confq) { 1069 initfq.we_mask |= 1070 cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1071 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD) 1072 * A2V=1 (contextA A2 field is valid) 1073 * A0V=1 (contextA A0 field is valid) 1074 * B0V=1 (contextB field is valid) 1075 * ContextA A2: EBD=1 (deallocate buffers inside FMan) 1076 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID) 1077 */ 1078 qm_fqd_context_a_set64(&initfq.fqd, 1079 0x1e00000080000000ULL); 1080 } 1081 } 1082 1083 /* Put all the ingress queues in our "ingress CGR". */ 1084 if (priv->use_ingress_cgr && 1085 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT || 1086 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR || 1087 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) { 1088 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1089 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1090 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid; 1091 /* Set a fixed overhead accounting, just like for the 1092 * egress CGR. 1093 */ 1094 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1095 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1096 qm_fqd_set_oal(&initfq.fqd, 1097 min(sizeof(struct sk_buff) + 1098 priv->tx_headroom, 1099 (size_t)FSL_QMAN_MAX_OAL)); 1100 } 1101 1102 /* Initialization common to all ingress queues */ 1103 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) { 1104 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1105 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE | 1106 QM_FQCTRL_CTXASTASHING); 1107 initfq.fqd.context_a.stashing.exclusive = 1108 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX | 1109 QM_STASHING_EXCL_ANNOTATION; 1110 qm_fqd_set_stashing(&initfq.fqd, 1, 2, 1111 DIV_ROUND_UP(sizeof(struct qman_fq), 1112 64)); 1113 } 1114 1115 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); 1116 if (err < 0) { 1117 dev_err(dev, "qman_init_fq(%u) = %d\n", 1118 qman_fq_fqid(fq), err); 1119 qman_destroy_fq(fq); 1120 return err; 1121 } 1122 } 1123 1124 dpaa_fq->fqid = qman_fq_fqid(fq); 1125 1126 return 0; 1127 } 1128 1129 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq) 1130 { 1131 const struct dpaa_priv *priv; 1132 struct dpaa_fq *dpaa_fq; 1133 int err, error; 1134 1135 err = 0; 1136 1137 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 1138 priv = netdev_priv(dpaa_fq->net_dev); 1139 1140 if (dpaa_fq->init) { 1141 err = qman_retire_fq(fq, NULL); 1142 if (err < 0 && netif_msg_drv(priv)) 1143 dev_err(dev, "qman_retire_fq(%u) = %d\n", 1144 qman_fq_fqid(fq), err); 1145 1146 error = qman_oos_fq(fq); 1147 if (error < 0 && netif_msg_drv(priv)) { 1148 dev_err(dev, "qman_oos_fq(%u) = %d\n", 1149 qman_fq_fqid(fq), error); 1150 if (err >= 0) 1151 err = error; 1152 } 1153 } 1154 1155 qman_destroy_fq(fq); 1156 list_del(&dpaa_fq->list); 1157 1158 return err; 1159 } 1160 1161 static int dpaa_fq_free(struct device *dev, struct list_head *list) 1162 { 1163 struct dpaa_fq *dpaa_fq, *tmp; 1164 int err, error; 1165 1166 err = 0; 1167 list_for_each_entry_safe(dpaa_fq, tmp, list, list) { 1168 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq); 1169 if (error < 0 && err >= 0) 1170 err = error; 1171 } 1172 1173 return err; 1174 } 1175 1176 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq, 1177 struct dpaa_fq *defq, 1178 struct dpaa_buffer_layout *buf_layout) 1179 { 1180 struct fman_buffer_prefix_content buf_prefix_content; 1181 struct fman_port_params params; 1182 int err; 1183 1184 memset(¶ms, 0, sizeof(params)); 1185 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1186 1187 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1188 buf_prefix_content.pass_prs_result = true; 1189 buf_prefix_content.pass_hash_result = true; 1190 buf_prefix_content.pass_time_stamp = true; 1191 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT; 1192 1193 params.specific_params.non_rx_params.err_fqid = errq->fqid; 1194 params.specific_params.non_rx_params.dflt_fqid = defq->fqid; 1195 1196 err = fman_port_config(port, ¶ms); 1197 if (err) { 1198 pr_err("%s: fman_port_config failed\n", __func__); 1199 return err; 1200 } 1201 1202 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1203 if (err) { 1204 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1205 __func__); 1206 return err; 1207 } 1208 1209 err = fman_port_init(port); 1210 if (err) 1211 pr_err("%s: fm_port_init failed\n", __func__); 1212 1213 return err; 1214 } 1215 1216 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp, 1217 struct dpaa_fq *errq, 1218 struct dpaa_fq *defq, struct dpaa_fq *pcdq, 1219 struct dpaa_buffer_layout *buf_layout) 1220 { 1221 struct fman_buffer_prefix_content buf_prefix_content; 1222 struct fman_port_rx_params *rx_p; 1223 struct fman_port_params params; 1224 int err; 1225 1226 memset(¶ms, 0, sizeof(params)); 1227 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1228 1229 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1230 buf_prefix_content.pass_prs_result = true; 1231 buf_prefix_content.pass_hash_result = true; 1232 buf_prefix_content.pass_time_stamp = true; 1233 buf_prefix_content.data_align = DPAA_FD_RX_DATA_ALIGNMENT; 1234 1235 rx_p = ¶ms.specific_params.rx_params; 1236 rx_p->err_fqid = errq->fqid; 1237 rx_p->dflt_fqid = defq->fqid; 1238 if (pcdq) { 1239 rx_p->pcd_base_fqid = pcdq->fqid; 1240 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM; 1241 } 1242 1243 rx_p->ext_buf_pools.num_of_pools_used = 1; 1244 rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid; 1245 rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size; 1246 1247 err = fman_port_config(port, ¶ms); 1248 if (err) { 1249 pr_err("%s: fman_port_config failed\n", __func__); 1250 return err; 1251 } 1252 1253 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1254 if (err) { 1255 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1256 __func__); 1257 return err; 1258 } 1259 1260 err = fman_port_init(port); 1261 if (err) 1262 pr_err("%s: fm_port_init failed\n", __func__); 1263 1264 return err; 1265 } 1266 1267 static int dpaa_eth_init_ports(struct mac_device *mac_dev, 1268 struct dpaa_bp *bp, 1269 struct fm_port_fqs *port_fqs, 1270 struct dpaa_buffer_layout *buf_layout, 1271 struct device *dev) 1272 { 1273 struct fman_port *rxport = mac_dev->port[RX]; 1274 struct fman_port *txport = mac_dev->port[TX]; 1275 int err; 1276 1277 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq, 1278 port_fqs->tx_defq, &buf_layout[TX]); 1279 if (err) 1280 return err; 1281 1282 err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq, 1283 port_fqs->rx_defq, port_fqs->rx_pcdq, 1284 &buf_layout[RX]); 1285 1286 return err; 1287 } 1288 1289 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp, 1290 struct bm_buffer *bmb, int cnt) 1291 { 1292 int err; 1293 1294 err = bman_release(dpaa_bp->pool, bmb, cnt); 1295 /* Should never occur, address anyway to avoid leaking the buffers */ 1296 if (WARN_ON(err) && dpaa_bp->free_buf_cb) 1297 while (cnt-- > 0) 1298 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]); 1299 1300 return cnt; 1301 } 1302 1303 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt) 1304 { 1305 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX]; 1306 struct dpaa_bp *dpaa_bp; 1307 int i = 0, j; 1308 1309 memset(bmb, 0, sizeof(bmb)); 1310 1311 do { 1312 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1313 if (!dpaa_bp) 1314 return; 1315 1316 j = 0; 1317 do { 1318 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1319 1320 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i])); 1321 1322 j++; i++; 1323 } while (j < ARRAY_SIZE(bmb) && 1324 !qm_sg_entry_is_final(&sgt[i - 1]) && 1325 sgt[i - 1].bpid == sgt[i].bpid); 1326 1327 dpaa_bman_release(dpaa_bp, bmb, j); 1328 } while (!qm_sg_entry_is_final(&sgt[i - 1])); 1329 } 1330 1331 static void dpaa_fd_release(const struct net_device *net_dev, 1332 const struct qm_fd *fd) 1333 { 1334 struct qm_sg_entry *sgt; 1335 struct dpaa_bp *dpaa_bp; 1336 struct bm_buffer bmb; 1337 dma_addr_t addr; 1338 void *vaddr; 1339 1340 bmb.data = 0; 1341 bm_buffer_set64(&bmb, qm_fd_addr(fd)); 1342 1343 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1344 if (!dpaa_bp) 1345 return; 1346 1347 if (qm_fd_get_format(fd) == qm_fd_sg) { 1348 vaddr = phys_to_virt(qm_fd_addr(fd)); 1349 sgt = vaddr + qm_fd_get_offset(fd); 1350 1351 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd), 1352 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1353 1354 dpaa_release_sgt_members(sgt); 1355 1356 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, 1357 virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE, 1358 DMA_FROM_DEVICE); 1359 if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) { 1360 netdev_err(net_dev, "DMA mapping failed\n"); 1361 return; 1362 } 1363 bm_buffer_set64(&bmb, addr); 1364 } 1365 1366 dpaa_bman_release(dpaa_bp, &bmb, 1); 1367 } 1368 1369 static void count_ern(struct dpaa_percpu_priv *percpu_priv, 1370 const union qm_mr_entry *msg) 1371 { 1372 switch (msg->ern.rc & QM_MR_RC_MASK) { 1373 case QM_MR_RC_CGR_TAILDROP: 1374 percpu_priv->ern_cnt.cg_tdrop++; 1375 break; 1376 case QM_MR_RC_WRED: 1377 percpu_priv->ern_cnt.wred++; 1378 break; 1379 case QM_MR_RC_ERROR: 1380 percpu_priv->ern_cnt.err_cond++; 1381 break; 1382 case QM_MR_RC_ORPWINDOW_EARLY: 1383 percpu_priv->ern_cnt.early_window++; 1384 break; 1385 case QM_MR_RC_ORPWINDOW_LATE: 1386 percpu_priv->ern_cnt.late_window++; 1387 break; 1388 case QM_MR_RC_FQ_TAILDROP: 1389 percpu_priv->ern_cnt.fq_tdrop++; 1390 break; 1391 case QM_MR_RC_ORPWINDOW_RETIRED: 1392 percpu_priv->ern_cnt.fq_retired++; 1393 break; 1394 case QM_MR_RC_ORP_ZERO: 1395 percpu_priv->ern_cnt.orp_zero++; 1396 break; 1397 } 1398 } 1399 1400 /* Turn on HW checksum computation for this outgoing frame. 1401 * If the current protocol is not something we support in this regard 1402 * (or if the stack has already computed the SW checksum), we do nothing. 1403 * 1404 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value 1405 * otherwise. 1406 * 1407 * Note that this function may modify the fd->cmd field and the skb data buffer 1408 * (the Parse Results area). 1409 */ 1410 static int dpaa_enable_tx_csum(struct dpaa_priv *priv, 1411 struct sk_buff *skb, 1412 struct qm_fd *fd, 1413 void *parse_results) 1414 { 1415 struct fman_prs_result *parse_result; 1416 u16 ethertype = ntohs(skb->protocol); 1417 struct ipv6hdr *ipv6h = NULL; 1418 struct iphdr *iph; 1419 int retval = 0; 1420 u8 l4_proto; 1421 1422 if (skb->ip_summed != CHECKSUM_PARTIAL) 1423 return 0; 1424 1425 /* Note: L3 csum seems to be already computed in sw, but we can't choose 1426 * L4 alone from the FM configuration anyway. 1427 */ 1428 1429 /* Fill in some fields of the Parse Results array, so the FMan 1430 * can find them as if they came from the FMan Parser. 1431 */ 1432 parse_result = (struct fman_prs_result *)parse_results; 1433 1434 /* If we're dealing with VLAN, get the real Ethernet type */ 1435 if (ethertype == ETH_P_8021Q) { 1436 /* We can't always assume the MAC header is set correctly 1437 * by the stack, so reset to beginning of skb->data 1438 */ 1439 skb_reset_mac_header(skb); 1440 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto); 1441 } 1442 1443 /* Fill in the relevant L3 parse result fields 1444 * and read the L4 protocol type 1445 */ 1446 switch (ethertype) { 1447 case ETH_P_IP: 1448 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4); 1449 iph = ip_hdr(skb); 1450 WARN_ON(!iph); 1451 l4_proto = iph->protocol; 1452 break; 1453 case ETH_P_IPV6: 1454 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6); 1455 ipv6h = ipv6_hdr(skb); 1456 WARN_ON(!ipv6h); 1457 l4_proto = ipv6h->nexthdr; 1458 break; 1459 default: 1460 /* We shouldn't even be here */ 1461 if (net_ratelimit()) 1462 netif_alert(priv, tx_err, priv->net_dev, 1463 "Can't compute HW csum for L3 proto 0x%x\n", 1464 ntohs(skb->protocol)); 1465 retval = -EIO; 1466 goto return_error; 1467 } 1468 1469 /* Fill in the relevant L4 parse result fields */ 1470 switch (l4_proto) { 1471 case IPPROTO_UDP: 1472 parse_result->l4r = FM_L4_PARSE_RESULT_UDP; 1473 break; 1474 case IPPROTO_TCP: 1475 parse_result->l4r = FM_L4_PARSE_RESULT_TCP; 1476 break; 1477 default: 1478 if (net_ratelimit()) 1479 netif_alert(priv, tx_err, priv->net_dev, 1480 "Can't compute HW csum for L4 proto 0x%x\n", 1481 l4_proto); 1482 retval = -EIO; 1483 goto return_error; 1484 } 1485 1486 /* At index 0 is IPOffset_1 as defined in the Parse Results */ 1487 parse_result->ip_off[0] = (u8)skb_network_offset(skb); 1488 parse_result->l4_off = (u8)skb_transport_offset(skb); 1489 1490 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */ 1491 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC); 1492 1493 /* On P1023 and similar platforms fd->cmd interpretation could 1494 * be disabled by setting CONTEXT_A bit ICMD; currently this bit 1495 * is not set so we do not need to check; in the future, if/when 1496 * using context_a we need to check this bit 1497 */ 1498 1499 return_error: 1500 return retval; 1501 } 1502 1503 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp) 1504 { 1505 struct net_device *net_dev = dpaa_bp->priv->net_dev; 1506 struct bm_buffer bmb[8]; 1507 dma_addr_t addr; 1508 struct page *p; 1509 u8 i; 1510 1511 for (i = 0; i < 8; i++) { 1512 p = dev_alloc_pages(0); 1513 if (unlikely(!p)) { 1514 netdev_err(net_dev, "dev_alloc_pages() failed\n"); 1515 goto release_previous_buffs; 1516 } 1517 1518 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0, 1519 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1520 if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev, 1521 addr))) { 1522 netdev_err(net_dev, "DMA map failed\n"); 1523 goto release_previous_buffs; 1524 } 1525 1526 bmb[i].data = 0; 1527 bm_buffer_set64(&bmb[i], addr); 1528 } 1529 1530 release_bufs: 1531 return dpaa_bman_release(dpaa_bp, bmb, i); 1532 1533 release_previous_buffs: 1534 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n"); 1535 1536 bm_buffer_set64(&bmb[i], 0); 1537 /* Avoid releasing a completely null buffer; bman_release() requires 1538 * at least one buffer. 1539 */ 1540 if (likely(i)) 1541 goto release_bufs; 1542 1543 return 0; 1544 } 1545 1546 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp) 1547 { 1548 int i; 1549 1550 /* Give each CPU an allotment of "config_count" buffers */ 1551 for_each_possible_cpu(i) { 1552 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i); 1553 int j; 1554 1555 /* Although we access another CPU's counters here 1556 * we do it at boot time so it is safe 1557 */ 1558 for (j = 0; j < dpaa_bp->config_count; j += 8) 1559 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp); 1560 } 1561 return 0; 1562 } 1563 1564 /* Add buffers/(pages) for Rx processing whenever bpool count falls below 1565 * REFILL_THRESHOLD. 1566 */ 1567 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr) 1568 { 1569 int count = *countptr; 1570 int new_bufs; 1571 1572 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) { 1573 do { 1574 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp); 1575 if (unlikely(!new_bufs)) { 1576 /* Avoid looping forever if we've temporarily 1577 * run out of memory. We'll try again at the 1578 * next NAPI cycle. 1579 */ 1580 break; 1581 } 1582 count += new_bufs; 1583 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT); 1584 1585 *countptr = count; 1586 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT)) 1587 return -ENOMEM; 1588 } 1589 1590 return 0; 1591 } 1592 1593 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv) 1594 { 1595 struct dpaa_bp *dpaa_bp; 1596 int *countptr; 1597 int res; 1598 1599 dpaa_bp = priv->dpaa_bp; 1600 if (!dpaa_bp) 1601 return -EINVAL; 1602 countptr = this_cpu_ptr(dpaa_bp->percpu_count); 1603 res = dpaa_eth_refill_bpool(dpaa_bp, countptr); 1604 if (res) 1605 return res; 1606 1607 return 0; 1608 } 1609 1610 /* Cleanup function for outgoing frame descriptors that were built on Tx path, 1611 * either contiguous frames or scatter/gather ones. 1612 * Skb freeing is not handled here. 1613 * 1614 * This function may be called on error paths in the Tx function, so guard 1615 * against cases when not all fd relevant fields were filled in. To avoid 1616 * reading the invalid transmission timestamp for the error paths set ts to 1617 * false. 1618 * 1619 * Return the skb backpointer, since for S/G frames the buffer containing it 1620 * gets freed here. 1621 */ 1622 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv, 1623 const struct qm_fd *fd, bool ts) 1624 { 1625 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1626 struct device *dev = priv->net_dev->dev.parent; 1627 struct skb_shared_hwtstamps shhwtstamps; 1628 dma_addr_t addr = qm_fd_addr(fd); 1629 void *vaddr = phys_to_virt(addr); 1630 const struct qm_sg_entry *sgt; 1631 struct sk_buff *skb; 1632 u64 ns; 1633 int i; 1634 1635 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) { 1636 dma_unmap_page(priv->tx_dma_dev, addr, 1637 qm_fd_get_offset(fd) + DPAA_SGT_SIZE, 1638 dma_dir); 1639 1640 /* The sgt buffer has been allocated with netdev_alloc_frag(), 1641 * it's from lowmem. 1642 */ 1643 sgt = vaddr + qm_fd_get_offset(fd); 1644 1645 /* sgt[0] is from lowmem, was dma_map_single()-ed */ 1646 dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]), 1647 qm_sg_entry_get_len(&sgt[0]), dma_dir); 1648 1649 /* remaining pages were mapped with skb_frag_dma_map() */ 1650 for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) && 1651 !qm_sg_entry_is_final(&sgt[i - 1]); i++) { 1652 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1653 1654 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]), 1655 qm_sg_entry_get_len(&sgt[i]), dma_dir); 1656 } 1657 } else { 1658 dma_unmap_single(priv->tx_dma_dev, addr, 1659 priv->tx_headroom + qm_fd_get_length(fd), 1660 dma_dir); 1661 } 1662 1663 skb = *(struct sk_buff **)vaddr; 1664 1665 /* DMA unmapping is required before accessing the HW provided info */ 1666 if (ts && priv->tx_tstamp && 1667 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1668 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1669 1670 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr, 1671 &ns)) { 1672 shhwtstamps.hwtstamp = ns_to_ktime(ns); 1673 skb_tstamp_tx(skb, &shhwtstamps); 1674 } else { 1675 dev_warn(dev, "fman_port_get_tstamp failed!\n"); 1676 } 1677 } 1678 1679 if (qm_fd_get_format(fd) == qm_fd_sg) 1680 /* Free the page that we allocated on Tx for the SGT */ 1681 free_pages((unsigned long)vaddr, 0); 1682 1683 return skb; 1684 } 1685 1686 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd) 1687 { 1688 /* The parser has run and performed L4 checksum validation. 1689 * We know there were no parser errors (and implicitly no 1690 * L4 csum error), otherwise we wouldn't be here. 1691 */ 1692 if ((priv->net_dev->features & NETIF_F_RXCSUM) && 1693 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV)) 1694 return CHECKSUM_UNNECESSARY; 1695 1696 /* We're here because either the parser didn't run or the L4 checksum 1697 * was not verified. This may include the case of a UDP frame with 1698 * checksum zero or an L4 proto other than TCP/UDP 1699 */ 1700 return CHECKSUM_NONE; 1701 } 1702 1703 #define PTR_IS_ALIGNED(x, a) (IS_ALIGNED((unsigned long)(x), (a))) 1704 1705 /* Build a linear skb around the received buffer. 1706 * We are guaranteed there is enough room at the end of the data buffer to 1707 * accommodate the shared info area of the skb. 1708 */ 1709 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv, 1710 const struct qm_fd *fd) 1711 { 1712 ssize_t fd_off = qm_fd_get_offset(fd); 1713 dma_addr_t addr = qm_fd_addr(fd); 1714 struct dpaa_bp *dpaa_bp; 1715 struct sk_buff *skb; 1716 void *vaddr; 1717 1718 vaddr = phys_to_virt(addr); 1719 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1720 1721 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1722 if (!dpaa_bp) 1723 goto free_buffer; 1724 1725 skb = build_skb(vaddr, dpaa_bp->size + 1726 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); 1727 if (WARN_ONCE(!skb, "Build skb failure on Rx\n")) 1728 goto free_buffer; 1729 WARN_ON(fd_off != priv->rx_headroom); 1730 skb_reserve(skb, fd_off); 1731 skb_put(skb, qm_fd_get_length(fd)); 1732 1733 skb->ip_summed = rx_csum_offload(priv, fd); 1734 1735 return skb; 1736 1737 free_buffer: 1738 free_pages((unsigned long)vaddr, 0); 1739 return NULL; 1740 } 1741 1742 /* Build an skb with the data of the first S/G entry in the linear portion and 1743 * the rest of the frame as skb fragments. 1744 * 1745 * The page fragment holding the S/G Table is recycled here. 1746 */ 1747 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv, 1748 const struct qm_fd *fd) 1749 { 1750 ssize_t fd_off = qm_fd_get_offset(fd); 1751 dma_addr_t addr = qm_fd_addr(fd); 1752 const struct qm_sg_entry *sgt; 1753 struct page *page, *head_page; 1754 struct dpaa_bp *dpaa_bp; 1755 void *vaddr, *sg_vaddr; 1756 int frag_off, frag_len; 1757 struct sk_buff *skb; 1758 dma_addr_t sg_addr; 1759 int page_offset; 1760 unsigned int sz; 1761 int *count_ptr; 1762 int i, j; 1763 1764 vaddr = phys_to_virt(addr); 1765 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1766 1767 /* Iterate through the SGT entries and add data buffers to the skb */ 1768 sgt = vaddr + fd_off; 1769 skb = NULL; 1770 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) { 1771 /* Extension bit is not supported */ 1772 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1773 1774 sg_addr = qm_sg_addr(&sgt[i]); 1775 sg_vaddr = phys_to_virt(sg_addr); 1776 WARN_ON(!PTR_IS_ALIGNED(sg_vaddr, SMP_CACHE_BYTES)); 1777 1778 dma_unmap_page(priv->rx_dma_dev, sg_addr, 1779 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1780 1781 /* We may use multiple Rx pools */ 1782 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1783 if (!dpaa_bp) 1784 goto free_buffers; 1785 1786 if (!skb) { 1787 sz = dpaa_bp->size + 1788 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1789 skb = build_skb(sg_vaddr, sz); 1790 if (WARN_ON(!skb)) 1791 goto free_buffers; 1792 1793 skb->ip_summed = rx_csum_offload(priv, fd); 1794 1795 /* Make sure forwarded skbs will have enough space 1796 * on Tx, if extra headers are added. 1797 */ 1798 WARN_ON(fd_off != priv->rx_headroom); 1799 skb_reserve(skb, fd_off); 1800 skb_put(skb, qm_sg_entry_get_len(&sgt[i])); 1801 } else { 1802 /* Not the first S/G entry; all data from buffer will 1803 * be added in an skb fragment; fragment index is offset 1804 * by one since first S/G entry was incorporated in the 1805 * linear part of the skb. 1806 * 1807 * Caution: 'page' may be a tail page. 1808 */ 1809 page = virt_to_page(sg_vaddr); 1810 head_page = virt_to_head_page(sg_vaddr); 1811 1812 /* Compute offset in (possibly tail) page */ 1813 page_offset = ((unsigned long)sg_vaddr & 1814 (PAGE_SIZE - 1)) + 1815 (page_address(page) - page_address(head_page)); 1816 /* page_offset only refers to the beginning of sgt[i]; 1817 * but the buffer itself may have an internal offset. 1818 */ 1819 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset; 1820 frag_len = qm_sg_entry_get_len(&sgt[i]); 1821 /* skb_add_rx_frag() does no checking on the page; if 1822 * we pass it a tail page, we'll end up with 1823 * bad page accounting and eventually with segafults. 1824 */ 1825 skb_add_rx_frag(skb, i - 1, head_page, frag_off, 1826 frag_len, dpaa_bp->size); 1827 } 1828 1829 /* Update the pool count for the current {cpu x bpool} */ 1830 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1831 (*count_ptr)--; 1832 1833 if (qm_sg_entry_is_final(&sgt[i])) 1834 break; 1835 } 1836 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n"); 1837 1838 /* free the SG table buffer */ 1839 free_pages((unsigned long)vaddr, 0); 1840 1841 return skb; 1842 1843 free_buffers: 1844 /* free all the SG entries */ 1845 for (j = 0; j < DPAA_SGT_MAX_ENTRIES ; j++) { 1846 sg_addr = qm_sg_addr(&sgt[j]); 1847 sg_vaddr = phys_to_virt(sg_addr); 1848 /* all pages 0..i were unmaped */ 1849 if (j > i) 1850 dma_unmap_page(priv->rx_dma_dev, qm_sg_addr(&sgt[j]), 1851 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE); 1852 free_pages((unsigned long)sg_vaddr, 0); 1853 /* counters 0..i-1 were decremented */ 1854 if (j >= i) { 1855 dpaa_bp = dpaa_bpid2pool(sgt[j].bpid); 1856 if (dpaa_bp) { 1857 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1858 (*count_ptr)--; 1859 } 1860 } 1861 1862 if (qm_sg_entry_is_final(&sgt[j])) 1863 break; 1864 } 1865 /* free the SGT fragment */ 1866 free_pages((unsigned long)vaddr, 0); 1867 1868 return NULL; 1869 } 1870 1871 static int skb_to_contig_fd(struct dpaa_priv *priv, 1872 struct sk_buff *skb, struct qm_fd *fd, 1873 int *offset) 1874 { 1875 struct net_device *net_dev = priv->net_dev; 1876 enum dma_data_direction dma_dir; 1877 unsigned char *buff_start; 1878 struct sk_buff **skbh; 1879 dma_addr_t addr; 1880 int err; 1881 1882 /* We are guaranteed to have at least tx_headroom bytes 1883 * available, so just use that for offset. 1884 */ 1885 fd->bpid = FSL_DPAA_BPID_INV; 1886 buff_start = skb->data - priv->tx_headroom; 1887 dma_dir = DMA_TO_DEVICE; 1888 1889 skbh = (struct sk_buff **)buff_start; 1890 *skbh = skb; 1891 1892 /* Enable L3/L4 hardware checksum computation. 1893 * 1894 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1895 * need to write into the skb. 1896 */ 1897 err = dpaa_enable_tx_csum(priv, skb, fd, 1898 buff_start + DPAA_TX_PRIV_DATA_SIZE); 1899 if (unlikely(err < 0)) { 1900 if (net_ratelimit()) 1901 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1902 err); 1903 return err; 1904 } 1905 1906 /* Fill in the rest of the FD fields */ 1907 qm_fd_set_contig(fd, priv->tx_headroom, skb->len); 1908 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 1909 1910 /* Map the entire buffer size that may be seen by FMan, but no more */ 1911 addr = dma_map_single(priv->tx_dma_dev, buff_start, 1912 priv->tx_headroom + skb->len, dma_dir); 1913 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1914 if (net_ratelimit()) 1915 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n"); 1916 return -EINVAL; 1917 } 1918 qm_fd_addr_set64(fd, addr); 1919 1920 return 0; 1921 } 1922 1923 static int skb_to_sg_fd(struct dpaa_priv *priv, 1924 struct sk_buff *skb, struct qm_fd *fd) 1925 { 1926 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1927 const int nr_frags = skb_shinfo(skb)->nr_frags; 1928 struct net_device *net_dev = priv->net_dev; 1929 struct qm_sg_entry *sgt; 1930 struct sk_buff **skbh; 1931 void *buff_start; 1932 skb_frag_t *frag; 1933 dma_addr_t addr; 1934 size_t frag_len; 1935 struct page *p; 1936 int i, j, err; 1937 1938 /* get a page to store the SGTable */ 1939 p = dev_alloc_pages(0); 1940 if (unlikely(!p)) { 1941 netdev_err(net_dev, "dev_alloc_pages() failed\n"); 1942 return -ENOMEM; 1943 } 1944 buff_start = page_address(p); 1945 1946 /* Enable L3/L4 hardware checksum computation. 1947 * 1948 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1949 * need to write into the skb. 1950 */ 1951 err = dpaa_enable_tx_csum(priv, skb, fd, 1952 buff_start + DPAA_TX_PRIV_DATA_SIZE); 1953 if (unlikely(err < 0)) { 1954 if (net_ratelimit()) 1955 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1956 err); 1957 goto csum_failed; 1958 } 1959 1960 /* SGT[0] is used by the linear part */ 1961 sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom); 1962 frag_len = skb_headlen(skb); 1963 qm_sg_entry_set_len(&sgt[0], frag_len); 1964 sgt[0].bpid = FSL_DPAA_BPID_INV; 1965 sgt[0].offset = 0; 1966 addr = dma_map_single(priv->tx_dma_dev, skb->data, 1967 skb_headlen(skb), dma_dir); 1968 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1969 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1970 err = -EINVAL; 1971 goto sg0_map_failed; 1972 } 1973 qm_sg_entry_set64(&sgt[0], addr); 1974 1975 /* populate the rest of SGT entries */ 1976 for (i = 0; i < nr_frags; i++) { 1977 frag = &skb_shinfo(skb)->frags[i]; 1978 frag_len = skb_frag_size(frag); 1979 WARN_ON(!skb_frag_page(frag)); 1980 addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0, 1981 frag_len, dma_dir); 1982 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 1983 netdev_err(priv->net_dev, "DMA mapping failed\n"); 1984 err = -EINVAL; 1985 goto sg_map_failed; 1986 } 1987 1988 qm_sg_entry_set_len(&sgt[i + 1], frag_len); 1989 sgt[i + 1].bpid = FSL_DPAA_BPID_INV; 1990 sgt[i + 1].offset = 0; 1991 1992 /* keep the offset in the address */ 1993 qm_sg_entry_set64(&sgt[i + 1], addr); 1994 } 1995 1996 /* Set the final bit in the last used entry of the SGT */ 1997 qm_sg_entry_set_f(&sgt[nr_frags], frag_len); 1998 1999 /* set fd offset to priv->tx_headroom */ 2000 qm_fd_set_sg(fd, priv->tx_headroom, skb->len); 2001 2002 /* DMA map the SGT page */ 2003 skbh = (struct sk_buff **)buff_start; 2004 *skbh = skb; 2005 2006 addr = dma_map_page(priv->tx_dma_dev, p, 0, 2007 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir); 2008 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) { 2009 netdev_err(priv->net_dev, "DMA mapping failed\n"); 2010 err = -EINVAL; 2011 goto sgt_map_failed; 2012 } 2013 2014 fd->bpid = FSL_DPAA_BPID_INV; 2015 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 2016 qm_fd_addr_set64(fd, addr); 2017 2018 return 0; 2019 2020 sgt_map_failed: 2021 sg_map_failed: 2022 for (j = 0; j < i; j++) 2023 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]), 2024 qm_sg_entry_get_len(&sgt[j]), dma_dir); 2025 sg0_map_failed: 2026 csum_failed: 2027 free_pages((unsigned long)buff_start, 0); 2028 2029 return err; 2030 } 2031 2032 static inline int dpaa_xmit(struct dpaa_priv *priv, 2033 struct rtnl_link_stats64 *percpu_stats, 2034 int queue, 2035 struct qm_fd *fd) 2036 { 2037 struct qman_fq *egress_fq; 2038 int err, i; 2039 2040 egress_fq = priv->egress_fqs[queue]; 2041 if (fd->bpid == FSL_DPAA_BPID_INV) 2042 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue])); 2043 2044 /* Trace this Tx fd */ 2045 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd); 2046 2047 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) { 2048 err = qman_enqueue(egress_fq, fd); 2049 if (err != -EBUSY) 2050 break; 2051 } 2052 2053 if (unlikely(err < 0)) { 2054 percpu_stats->tx_fifo_errors++; 2055 return err; 2056 } 2057 2058 percpu_stats->tx_packets++; 2059 percpu_stats->tx_bytes += qm_fd_get_length(fd); 2060 2061 return 0; 2062 } 2063 2064 #ifdef CONFIG_DPAA_ERRATUM_A050385 2065 static int dpaa_a050385_wa(struct net_device *net_dev, struct sk_buff **s) 2066 { 2067 struct dpaa_priv *priv = netdev_priv(net_dev); 2068 struct sk_buff *new_skb, *skb = *s; 2069 unsigned char *start, i; 2070 2071 /* check linear buffer alignment */ 2072 if (!PTR_IS_ALIGNED(skb->data, DPAA_A050385_ALIGN)) 2073 goto workaround; 2074 2075 /* linear buffers just need to have an aligned start */ 2076 if (!skb_is_nonlinear(skb)) 2077 return 0; 2078 2079 /* linear data size for nonlinear skbs needs to be aligned */ 2080 if (!IS_ALIGNED(skb_headlen(skb), DPAA_A050385_ALIGN)) 2081 goto workaround; 2082 2083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2084 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2085 2086 /* all fragments need to have aligned start addresses */ 2087 if (!IS_ALIGNED(skb_frag_off(frag), DPAA_A050385_ALIGN)) 2088 goto workaround; 2089 2090 /* all but last fragment need to have aligned sizes */ 2091 if (!IS_ALIGNED(skb_frag_size(frag), DPAA_A050385_ALIGN) && 2092 (i < skb_shinfo(skb)->nr_frags - 1)) 2093 goto workaround; 2094 } 2095 2096 return 0; 2097 2098 workaround: 2099 /* copy all the skb content into a new linear buffer */ 2100 new_skb = netdev_alloc_skb(net_dev, skb->len + DPAA_A050385_ALIGN - 1 + 2101 priv->tx_headroom); 2102 if (!new_skb) 2103 return -ENOMEM; 2104 2105 /* NET_SKB_PAD bytes already reserved, adding up to tx_headroom */ 2106 skb_reserve(new_skb, priv->tx_headroom - NET_SKB_PAD); 2107 2108 /* Workaround for DPAA_A050385 requires data start to be aligned */ 2109 start = PTR_ALIGN(new_skb->data, DPAA_A050385_ALIGN); 2110 if (start - new_skb->data != 0) 2111 skb_reserve(new_skb, start - new_skb->data); 2112 2113 skb_put(new_skb, skb->len); 2114 skb_copy_bits(skb, 0, new_skb->data, skb->len); 2115 skb_copy_header(new_skb, skb); 2116 new_skb->dev = skb->dev; 2117 2118 /* We move the headroom when we align it so we have to reset the 2119 * network and transport header offsets relative to the new data 2120 * pointer. The checksum offload relies on these offsets. 2121 */ 2122 skb_set_network_header(new_skb, skb_network_offset(skb)); 2123 skb_set_transport_header(new_skb, skb_transport_offset(skb)); 2124 2125 /* TODO: does timestamping need the result in the old skb? */ 2126 dev_kfree_skb(skb); 2127 *s = new_skb; 2128 2129 return 0; 2130 } 2131 #endif 2132 2133 static netdev_tx_t 2134 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev) 2135 { 2136 const int queue_mapping = skb_get_queue_mapping(skb); 2137 bool nonlinear = skb_is_nonlinear(skb); 2138 struct rtnl_link_stats64 *percpu_stats; 2139 struct dpaa_percpu_priv *percpu_priv; 2140 struct netdev_queue *txq; 2141 struct dpaa_priv *priv; 2142 struct qm_fd fd; 2143 int offset = 0; 2144 int err = 0; 2145 2146 priv = netdev_priv(net_dev); 2147 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2148 percpu_stats = &percpu_priv->stats; 2149 2150 qm_fd_clear_fd(&fd); 2151 2152 if (!nonlinear) { 2153 /* We're going to store the skb backpointer at the beginning 2154 * of the data buffer, so we need a privately owned skb 2155 * 2156 * We've made sure skb is not shared in dev->priv_flags, 2157 * we need to verify the skb head is not cloned 2158 */ 2159 if (skb_cow_head(skb, priv->tx_headroom)) 2160 goto enomem; 2161 2162 WARN_ON(skb_is_nonlinear(skb)); 2163 } 2164 2165 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES; 2166 * make sure we don't feed FMan with more fragments than it supports. 2167 */ 2168 if (unlikely(nonlinear && 2169 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) { 2170 /* If the egress skb contains more fragments than we support 2171 * we have no choice but to linearize it ourselves. 2172 */ 2173 if (__skb_linearize(skb)) 2174 goto enomem; 2175 2176 nonlinear = skb_is_nonlinear(skb); 2177 } 2178 2179 #ifdef CONFIG_DPAA_ERRATUM_A050385 2180 if (unlikely(fman_has_errata_a050385())) { 2181 if (dpaa_a050385_wa(net_dev, &skb)) 2182 goto enomem; 2183 nonlinear = skb_is_nonlinear(skb); 2184 } 2185 #endif 2186 2187 if (nonlinear) { 2188 /* Just create a S/G fd based on the skb */ 2189 err = skb_to_sg_fd(priv, skb, &fd); 2190 percpu_priv->tx_frag_skbuffs++; 2191 } else { 2192 /* Create a contig FD from this skb */ 2193 err = skb_to_contig_fd(priv, skb, &fd, &offset); 2194 } 2195 if (unlikely(err < 0)) 2196 goto skb_to_fd_failed; 2197 2198 txq = netdev_get_tx_queue(net_dev, queue_mapping); 2199 2200 /* LLTX requires to do our own update of trans_start */ 2201 txq->trans_start = jiffies; 2202 2203 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 2204 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD); 2205 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2206 } 2207 2208 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0)) 2209 return NETDEV_TX_OK; 2210 2211 dpaa_cleanup_tx_fd(priv, &fd, false); 2212 skb_to_fd_failed: 2213 enomem: 2214 percpu_stats->tx_errors++; 2215 dev_kfree_skb(skb); 2216 return NETDEV_TX_OK; 2217 } 2218 2219 static void dpaa_rx_error(struct net_device *net_dev, 2220 const struct dpaa_priv *priv, 2221 struct dpaa_percpu_priv *percpu_priv, 2222 const struct qm_fd *fd, 2223 u32 fqid) 2224 { 2225 if (net_ratelimit()) 2226 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n", 2227 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS); 2228 2229 percpu_priv->stats.rx_errors++; 2230 2231 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA) 2232 percpu_priv->rx_errors.dme++; 2233 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL) 2234 percpu_priv->rx_errors.fpe++; 2235 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE) 2236 percpu_priv->rx_errors.fse++; 2237 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR) 2238 percpu_priv->rx_errors.phe++; 2239 2240 dpaa_fd_release(net_dev, fd); 2241 } 2242 2243 static void dpaa_tx_error(struct net_device *net_dev, 2244 const struct dpaa_priv *priv, 2245 struct dpaa_percpu_priv *percpu_priv, 2246 const struct qm_fd *fd, 2247 u32 fqid) 2248 { 2249 struct sk_buff *skb; 2250 2251 if (net_ratelimit()) 2252 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2253 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS); 2254 2255 percpu_priv->stats.tx_errors++; 2256 2257 skb = dpaa_cleanup_tx_fd(priv, fd, false); 2258 dev_kfree_skb(skb); 2259 } 2260 2261 static int dpaa_eth_poll(struct napi_struct *napi, int budget) 2262 { 2263 struct dpaa_napi_portal *np = 2264 container_of(napi, struct dpaa_napi_portal, napi); 2265 2266 int cleaned = qman_p_poll_dqrr(np->p, budget); 2267 2268 if (cleaned < budget) { 2269 napi_complete_done(napi, cleaned); 2270 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2271 } else if (np->down) { 2272 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2273 } 2274 2275 return cleaned; 2276 } 2277 2278 static void dpaa_tx_conf(struct net_device *net_dev, 2279 const struct dpaa_priv *priv, 2280 struct dpaa_percpu_priv *percpu_priv, 2281 const struct qm_fd *fd, 2282 u32 fqid) 2283 { 2284 struct sk_buff *skb; 2285 2286 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) { 2287 if (net_ratelimit()) 2288 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2289 be32_to_cpu(fd->status) & 2290 FM_FD_STAT_TX_ERRORS); 2291 2292 percpu_priv->stats.tx_errors++; 2293 } 2294 2295 percpu_priv->tx_confirm++; 2296 2297 skb = dpaa_cleanup_tx_fd(priv, fd, true); 2298 2299 consume_skb(skb); 2300 } 2301 2302 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv, 2303 struct qman_portal *portal) 2304 { 2305 if (unlikely(in_irq() || !in_serving_softirq())) { 2306 /* Disable QMan IRQ and invoke NAPI */ 2307 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI); 2308 2309 percpu_priv->np.p = portal; 2310 napi_schedule(&percpu_priv->np.napi); 2311 percpu_priv->in_interrupt++; 2312 return 1; 2313 } 2314 return 0; 2315 } 2316 2317 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal, 2318 struct qman_fq *fq, 2319 const struct qm_dqrr_entry *dq) 2320 { 2321 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 2322 struct dpaa_percpu_priv *percpu_priv; 2323 struct net_device *net_dev; 2324 struct dpaa_bp *dpaa_bp; 2325 struct dpaa_priv *priv; 2326 2327 net_dev = dpaa_fq->net_dev; 2328 priv = netdev_priv(net_dev); 2329 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2330 if (!dpaa_bp) 2331 return qman_cb_dqrr_consume; 2332 2333 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2334 2335 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2336 return qman_cb_dqrr_stop; 2337 2338 dpaa_eth_refill_bpools(priv); 2339 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2340 2341 return qman_cb_dqrr_consume; 2342 } 2343 2344 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal, 2345 struct qman_fq *fq, 2346 const struct qm_dqrr_entry *dq) 2347 { 2348 struct skb_shared_hwtstamps *shhwtstamps; 2349 struct rtnl_link_stats64 *percpu_stats; 2350 struct dpaa_percpu_priv *percpu_priv; 2351 const struct qm_fd *fd = &dq->fd; 2352 dma_addr_t addr = qm_fd_addr(fd); 2353 enum qm_fd_format fd_format; 2354 struct net_device *net_dev; 2355 u32 fd_status, hash_offset; 2356 struct dpaa_bp *dpaa_bp; 2357 struct dpaa_priv *priv; 2358 unsigned int skb_len; 2359 struct sk_buff *skb; 2360 int *count_ptr; 2361 void *vaddr; 2362 u64 ns; 2363 2364 fd_status = be32_to_cpu(fd->status); 2365 fd_format = qm_fd_get_format(fd); 2366 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2367 priv = netdev_priv(net_dev); 2368 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2369 if (!dpaa_bp) 2370 return qman_cb_dqrr_consume; 2371 2372 /* Trace the Rx fd */ 2373 trace_dpaa_rx_fd(net_dev, fq, &dq->fd); 2374 2375 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2376 percpu_stats = &percpu_priv->stats; 2377 2378 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal))) 2379 return qman_cb_dqrr_stop; 2380 2381 /* Make sure we didn't run out of buffers */ 2382 if (unlikely(dpaa_eth_refill_bpools(priv))) { 2383 /* Unable to refill the buffer pool due to insufficient 2384 * system memory. Just release the frame back into the pool, 2385 * otherwise we'll soon end up with an empty buffer pool. 2386 */ 2387 dpaa_fd_release(net_dev, &dq->fd); 2388 return qman_cb_dqrr_consume; 2389 } 2390 2391 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) { 2392 if (net_ratelimit()) 2393 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2394 fd_status & FM_FD_STAT_RX_ERRORS); 2395 2396 percpu_stats->rx_errors++; 2397 dpaa_fd_release(net_dev, fd); 2398 return qman_cb_dqrr_consume; 2399 } 2400 2401 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE, 2402 DMA_FROM_DEVICE); 2403 2404 /* prefetch the first 64 bytes of the frame or the SGT start */ 2405 vaddr = phys_to_virt(addr); 2406 prefetch(vaddr + qm_fd_get_offset(fd)); 2407 2408 /* The only FD types that we may receive are contig and S/G */ 2409 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg)); 2410 2411 /* Account for either the contig buffer or the SGT buffer (depending on 2412 * which case we were in) having been removed from the pool. 2413 */ 2414 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 2415 (*count_ptr)--; 2416 2417 if (likely(fd_format == qm_fd_contig)) 2418 skb = contig_fd_to_skb(priv, fd); 2419 else 2420 skb = sg_fd_to_skb(priv, fd); 2421 if (!skb) 2422 return qman_cb_dqrr_consume; 2423 2424 if (priv->rx_tstamp) { 2425 shhwtstamps = skb_hwtstamps(skb); 2426 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2427 2428 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns)) 2429 shhwtstamps->hwtstamp = ns_to_ktime(ns); 2430 else 2431 dev_warn(net_dev->dev.parent, "fman_port_get_tstamp failed!\n"); 2432 } 2433 2434 skb->protocol = eth_type_trans(skb, net_dev); 2435 2436 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use && 2437 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX], 2438 &hash_offset)) { 2439 enum pkt_hash_types type; 2440 2441 /* if L4 exists, it was used in the hash generation */ 2442 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ? 2443 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3; 2444 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)), 2445 type); 2446 } 2447 2448 skb_len = skb->len; 2449 2450 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) { 2451 percpu_stats->rx_dropped++; 2452 return qman_cb_dqrr_consume; 2453 } 2454 2455 percpu_stats->rx_packets++; 2456 percpu_stats->rx_bytes += skb_len; 2457 2458 return qman_cb_dqrr_consume; 2459 } 2460 2461 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal, 2462 struct qman_fq *fq, 2463 const struct qm_dqrr_entry *dq) 2464 { 2465 struct dpaa_percpu_priv *percpu_priv; 2466 struct net_device *net_dev; 2467 struct dpaa_priv *priv; 2468 2469 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2470 priv = netdev_priv(net_dev); 2471 2472 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2473 2474 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2475 return qman_cb_dqrr_stop; 2476 2477 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2478 2479 return qman_cb_dqrr_consume; 2480 } 2481 2482 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal, 2483 struct qman_fq *fq, 2484 const struct qm_dqrr_entry *dq) 2485 { 2486 struct dpaa_percpu_priv *percpu_priv; 2487 struct net_device *net_dev; 2488 struct dpaa_priv *priv; 2489 2490 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2491 priv = netdev_priv(net_dev); 2492 2493 /* Trace the fd */ 2494 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd); 2495 2496 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2497 2498 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2499 return qman_cb_dqrr_stop; 2500 2501 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2502 2503 return qman_cb_dqrr_consume; 2504 } 2505 2506 static void egress_ern(struct qman_portal *portal, 2507 struct qman_fq *fq, 2508 const union qm_mr_entry *msg) 2509 { 2510 const struct qm_fd *fd = &msg->ern.fd; 2511 struct dpaa_percpu_priv *percpu_priv; 2512 const struct dpaa_priv *priv; 2513 struct net_device *net_dev; 2514 struct sk_buff *skb; 2515 2516 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2517 priv = netdev_priv(net_dev); 2518 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2519 2520 percpu_priv->stats.tx_dropped++; 2521 percpu_priv->stats.tx_fifo_errors++; 2522 count_ern(percpu_priv, msg); 2523 2524 skb = dpaa_cleanup_tx_fd(priv, fd, false); 2525 dev_kfree_skb_any(skb); 2526 } 2527 2528 static const struct dpaa_fq_cbs dpaa_fq_cbs = { 2529 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } }, 2530 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } }, 2531 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } }, 2532 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } }, 2533 .egress_ern = { .cb = { .ern = egress_ern } } 2534 }; 2535 2536 static void dpaa_eth_napi_enable(struct dpaa_priv *priv) 2537 { 2538 struct dpaa_percpu_priv *percpu_priv; 2539 int i; 2540 2541 for_each_online_cpu(i) { 2542 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2543 2544 percpu_priv->np.down = 0; 2545 napi_enable(&percpu_priv->np.napi); 2546 } 2547 } 2548 2549 static void dpaa_eth_napi_disable(struct dpaa_priv *priv) 2550 { 2551 struct dpaa_percpu_priv *percpu_priv; 2552 int i; 2553 2554 for_each_online_cpu(i) { 2555 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2556 2557 percpu_priv->np.down = 1; 2558 napi_disable(&percpu_priv->np.napi); 2559 } 2560 } 2561 2562 static void dpaa_adjust_link(struct net_device *net_dev) 2563 { 2564 struct mac_device *mac_dev; 2565 struct dpaa_priv *priv; 2566 2567 priv = netdev_priv(net_dev); 2568 mac_dev = priv->mac_dev; 2569 mac_dev->adjust_link(mac_dev); 2570 } 2571 2572 /* The Aquantia PHYs are capable of performing rate adaptation */ 2573 #define PHY_VEND_AQUANTIA 0x03a1b400 2574 2575 static int dpaa_phy_init(struct net_device *net_dev) 2576 { 2577 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2578 struct mac_device *mac_dev; 2579 struct phy_device *phy_dev; 2580 struct dpaa_priv *priv; 2581 2582 priv = netdev_priv(net_dev); 2583 mac_dev = priv->mac_dev; 2584 2585 phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, 2586 &dpaa_adjust_link, 0, 2587 mac_dev->phy_if); 2588 if (!phy_dev) { 2589 netif_err(priv, ifup, net_dev, "init_phy() failed\n"); 2590 return -ENODEV; 2591 } 2592 2593 /* Unless the PHY is capable of rate adaptation */ 2594 if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII || 2595 ((phy_dev->drv->phy_id & GENMASK(31, 10)) != PHY_VEND_AQUANTIA)) { 2596 /* remove any features not supported by the controller */ 2597 ethtool_convert_legacy_u32_to_link_mode(mask, 2598 mac_dev->if_support); 2599 linkmode_and(phy_dev->supported, phy_dev->supported, mask); 2600 } 2601 2602 phy_support_asym_pause(phy_dev); 2603 2604 mac_dev->phy_dev = phy_dev; 2605 net_dev->phydev = phy_dev; 2606 2607 return 0; 2608 } 2609 2610 static int dpaa_open(struct net_device *net_dev) 2611 { 2612 struct mac_device *mac_dev; 2613 struct dpaa_priv *priv; 2614 int err, i; 2615 2616 priv = netdev_priv(net_dev); 2617 mac_dev = priv->mac_dev; 2618 dpaa_eth_napi_enable(priv); 2619 2620 err = dpaa_phy_init(net_dev); 2621 if (err) 2622 goto phy_init_failed; 2623 2624 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 2625 err = fman_port_enable(mac_dev->port[i]); 2626 if (err) 2627 goto mac_start_failed; 2628 } 2629 2630 err = priv->mac_dev->start(mac_dev); 2631 if (err < 0) { 2632 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err); 2633 goto mac_start_failed; 2634 } 2635 2636 netif_tx_start_all_queues(net_dev); 2637 2638 return 0; 2639 2640 mac_start_failed: 2641 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) 2642 fman_port_disable(mac_dev->port[i]); 2643 2644 phy_init_failed: 2645 dpaa_eth_napi_disable(priv); 2646 2647 return err; 2648 } 2649 2650 static int dpaa_eth_stop(struct net_device *net_dev) 2651 { 2652 struct dpaa_priv *priv; 2653 int err; 2654 2655 err = dpaa_stop(net_dev); 2656 2657 priv = netdev_priv(net_dev); 2658 dpaa_eth_napi_disable(priv); 2659 2660 return err; 2661 } 2662 2663 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2664 { 2665 struct dpaa_priv *priv = netdev_priv(dev); 2666 struct hwtstamp_config config; 2667 2668 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 2669 return -EFAULT; 2670 2671 switch (config.tx_type) { 2672 case HWTSTAMP_TX_OFF: 2673 /* Couldn't disable rx/tx timestamping separately. 2674 * Do nothing here. 2675 */ 2676 priv->tx_tstamp = false; 2677 break; 2678 case HWTSTAMP_TX_ON: 2679 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2680 priv->tx_tstamp = true; 2681 break; 2682 default: 2683 return -ERANGE; 2684 } 2685 2686 if (config.rx_filter == HWTSTAMP_FILTER_NONE) { 2687 /* Couldn't disable rx/tx timestamping separately. 2688 * Do nothing here. 2689 */ 2690 priv->rx_tstamp = false; 2691 } else { 2692 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2693 priv->rx_tstamp = true; 2694 /* TS is set for all frame types, not only those requested */ 2695 config.rx_filter = HWTSTAMP_FILTER_ALL; 2696 } 2697 2698 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? 2699 -EFAULT : 0; 2700 } 2701 2702 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd) 2703 { 2704 int ret = -EINVAL; 2705 2706 if (cmd == SIOCGMIIREG) { 2707 if (net_dev->phydev) 2708 return phy_mii_ioctl(net_dev->phydev, rq, cmd); 2709 } 2710 2711 if (cmd == SIOCSHWTSTAMP) 2712 return dpaa_ts_ioctl(net_dev, rq, cmd); 2713 2714 return ret; 2715 } 2716 2717 static const struct net_device_ops dpaa_ops = { 2718 .ndo_open = dpaa_open, 2719 .ndo_start_xmit = dpaa_start_xmit, 2720 .ndo_stop = dpaa_eth_stop, 2721 .ndo_tx_timeout = dpaa_tx_timeout, 2722 .ndo_get_stats64 = dpaa_get_stats64, 2723 .ndo_change_carrier = fixed_phy_change_carrier, 2724 .ndo_set_mac_address = dpaa_set_mac_address, 2725 .ndo_validate_addr = eth_validate_addr, 2726 .ndo_set_rx_mode = dpaa_set_rx_mode, 2727 .ndo_do_ioctl = dpaa_ioctl, 2728 .ndo_setup_tc = dpaa_setup_tc, 2729 }; 2730 2731 static int dpaa_napi_add(struct net_device *net_dev) 2732 { 2733 struct dpaa_priv *priv = netdev_priv(net_dev); 2734 struct dpaa_percpu_priv *percpu_priv; 2735 int cpu; 2736 2737 for_each_possible_cpu(cpu) { 2738 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2739 2740 netif_napi_add(net_dev, &percpu_priv->np.napi, 2741 dpaa_eth_poll, NAPI_POLL_WEIGHT); 2742 } 2743 2744 return 0; 2745 } 2746 2747 static void dpaa_napi_del(struct net_device *net_dev) 2748 { 2749 struct dpaa_priv *priv = netdev_priv(net_dev); 2750 struct dpaa_percpu_priv *percpu_priv; 2751 int cpu; 2752 2753 for_each_possible_cpu(cpu) { 2754 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2755 2756 netif_napi_del(&percpu_priv->np.napi); 2757 } 2758 } 2759 2760 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp, 2761 struct bm_buffer *bmb) 2762 { 2763 dma_addr_t addr = bm_buf_addr(bmb); 2764 2765 dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE, 2766 DMA_FROM_DEVICE); 2767 2768 skb_free_frag(phys_to_virt(addr)); 2769 } 2770 2771 /* Alloc the dpaa_bp struct and configure default values */ 2772 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev) 2773 { 2774 struct dpaa_bp *dpaa_bp; 2775 2776 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL); 2777 if (!dpaa_bp) 2778 return ERR_PTR(-ENOMEM); 2779 2780 dpaa_bp->bpid = FSL_DPAA_BPID_INV; 2781 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count); 2782 if (!dpaa_bp->percpu_count) 2783 return ERR_PTR(-ENOMEM); 2784 2785 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT; 2786 2787 dpaa_bp->seed_cb = dpaa_bp_seed; 2788 dpaa_bp->free_buf_cb = dpaa_bp_free_pf; 2789 2790 return dpaa_bp; 2791 } 2792 2793 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR. 2794 * We won't be sending congestion notifications to FMan; for now, we just use 2795 * this CGR to generate enqueue rejections to FMan in order to drop the frames 2796 * before they reach our ingress queues and eat up memory. 2797 */ 2798 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv) 2799 { 2800 struct qm_mcc_initcgr initcgr; 2801 u32 cs_th; 2802 int err; 2803 2804 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid); 2805 if (err < 0) { 2806 if (netif_msg_drv(priv)) 2807 pr_err("Error %d allocating CGR ID\n", err); 2808 goto out_error; 2809 } 2810 2811 /* Enable CS TD, but disable Congestion State Change Notifications. */ 2812 memset(&initcgr, 0, sizeof(initcgr)); 2813 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES); 2814 initcgr.cgr.cscn_en = QM_CGR_EN; 2815 cs_th = DPAA_INGRESS_CS_THRESHOLD; 2816 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 2817 2818 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 2819 initcgr.cgr.cstd_en = QM_CGR_EN; 2820 2821 /* This CGR will be associated with the SWP affined to the current CPU. 2822 * However, we'll place all our ingress FQs in it. 2823 */ 2824 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT, 2825 &initcgr); 2826 if (err < 0) { 2827 if (netif_msg_drv(priv)) 2828 pr_err("Error %d creating ingress CGR with ID %d\n", 2829 err, priv->ingress_cgr.cgrid); 2830 qman_release_cgrid(priv->ingress_cgr.cgrid); 2831 goto out_error; 2832 } 2833 if (netif_msg_drv(priv)) 2834 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n", 2835 priv->ingress_cgr.cgrid, priv->mac_dev->addr); 2836 2837 priv->use_ingress_cgr = true; 2838 2839 out_error: 2840 return err; 2841 } 2842 2843 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl) 2844 { 2845 u16 headroom; 2846 2847 /* The frame headroom must accommodate: 2848 * - the driver private data area 2849 * - parse results, hash results, timestamp if selected 2850 * If either hash results or time stamp are selected, both will 2851 * be copied to/from the frame headroom, as TS is located between PR and 2852 * HR in the IC and IC copy size has a granularity of 16bytes 2853 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM) 2854 * 2855 * Also make sure the headroom is a multiple of data_align bytes 2856 */ 2857 headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE + 2858 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE); 2859 2860 return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT); 2861 } 2862 2863 static int dpaa_eth_probe(struct platform_device *pdev) 2864 { 2865 struct net_device *net_dev = NULL; 2866 struct dpaa_bp *dpaa_bp = NULL; 2867 struct dpaa_fq *dpaa_fq, *tmp; 2868 struct dpaa_priv *priv = NULL; 2869 struct fm_port_fqs port_fqs; 2870 struct mac_device *mac_dev; 2871 int err = 0, channel; 2872 struct device *dev; 2873 2874 dev = &pdev->dev; 2875 2876 err = bman_is_probed(); 2877 if (!err) 2878 return -EPROBE_DEFER; 2879 if (err < 0) { 2880 dev_err(dev, "failing probe due to bman probe error\n"); 2881 return -ENODEV; 2882 } 2883 err = qman_is_probed(); 2884 if (!err) 2885 return -EPROBE_DEFER; 2886 if (err < 0) { 2887 dev_err(dev, "failing probe due to qman probe error\n"); 2888 return -ENODEV; 2889 } 2890 err = bman_portals_probed(); 2891 if (!err) 2892 return -EPROBE_DEFER; 2893 if (err < 0) { 2894 dev_err(dev, 2895 "failing probe due to bman portals probe error\n"); 2896 return -ENODEV; 2897 } 2898 err = qman_portals_probed(); 2899 if (!err) 2900 return -EPROBE_DEFER; 2901 if (err < 0) { 2902 dev_err(dev, 2903 "failing probe due to qman portals probe error\n"); 2904 return -ENODEV; 2905 } 2906 2907 /* Allocate this early, so we can store relevant information in 2908 * the private area 2909 */ 2910 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM); 2911 if (!net_dev) { 2912 dev_err(dev, "alloc_etherdev_mq() failed\n"); 2913 return -ENOMEM; 2914 } 2915 2916 /* Do this here, so we can be verbose early */ 2917 SET_NETDEV_DEV(net_dev, dev); 2918 dev_set_drvdata(dev, net_dev); 2919 2920 priv = netdev_priv(net_dev); 2921 priv->net_dev = net_dev; 2922 2923 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT); 2924 2925 mac_dev = dpaa_mac_dev_get(pdev); 2926 if (IS_ERR(mac_dev)) { 2927 netdev_err(net_dev, "dpaa_mac_dev_get() failed\n"); 2928 err = PTR_ERR(mac_dev); 2929 goto free_netdev; 2930 } 2931 2932 /* Devices used for DMA mapping */ 2933 priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]); 2934 priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]); 2935 err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40)); 2936 if (!err) 2937 err = dma_coerce_mask_and_coherent(priv->tx_dma_dev, 2938 DMA_BIT_MASK(40)); 2939 if (err) { 2940 netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n"); 2941 return err; 2942 } 2943 2944 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500, 2945 * we choose conservatively and let the user explicitly set a higher 2946 * MTU via ifconfig. Otherwise, the user may end up with different MTUs 2947 * in the same LAN. 2948 * If on the other hand fsl_fm_max_frm has been chosen below 1500, 2949 * start with the maximum allowed. 2950 */ 2951 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN); 2952 2953 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n", 2954 net_dev->mtu); 2955 2956 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */ 2957 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */ 2958 2959 /* bp init */ 2960 dpaa_bp = dpaa_bp_alloc(dev); 2961 if (IS_ERR(dpaa_bp)) { 2962 err = PTR_ERR(dpaa_bp); 2963 goto free_dpaa_bps; 2964 } 2965 /* the raw size of the buffers used for reception */ 2966 dpaa_bp->raw_size = DPAA_BP_RAW_SIZE; 2967 /* avoid runtime computations by keeping the usable size here */ 2968 dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size); 2969 dpaa_bp->priv = priv; 2970 2971 err = dpaa_bp_alloc_pool(dpaa_bp); 2972 if (err < 0) 2973 goto free_dpaa_bps; 2974 priv->dpaa_bp = dpaa_bp; 2975 2976 INIT_LIST_HEAD(&priv->dpaa_fq_list); 2977 2978 memset(&port_fqs, 0, sizeof(port_fqs)); 2979 2980 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs); 2981 if (err < 0) { 2982 dev_err(dev, "dpaa_alloc_all_fqs() failed\n"); 2983 goto free_dpaa_bps; 2984 } 2985 2986 priv->mac_dev = mac_dev; 2987 2988 channel = dpaa_get_channel(); 2989 if (channel < 0) { 2990 dev_err(dev, "dpaa_get_channel() failed\n"); 2991 err = channel; 2992 goto free_dpaa_bps; 2993 } 2994 2995 priv->channel = (u16)channel; 2996 2997 /* Walk the CPUs with affine portals 2998 * and add this pool channel to each's dequeue mask. 2999 */ 3000 dpaa_eth_add_channel(priv->channel, &pdev->dev); 3001 3002 dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]); 3003 3004 /* Create a congestion group for this netdev, with 3005 * dynamically-allocated CGR ID. 3006 * Must be executed after probing the MAC, but before 3007 * assigning the egress FQs to the CGRs. 3008 */ 3009 err = dpaa_eth_cgr_init(priv); 3010 if (err < 0) { 3011 dev_err(dev, "Error initializing CGR\n"); 3012 goto free_dpaa_bps; 3013 } 3014 3015 err = dpaa_ingress_cgr_init(priv); 3016 if (err < 0) { 3017 dev_err(dev, "Error initializing ingress CGR\n"); 3018 goto delete_egress_cgr; 3019 } 3020 3021 /* Add the FQs to the interface, and make them active */ 3022 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) { 3023 err = dpaa_fq_init(dpaa_fq, false); 3024 if (err < 0) 3025 goto free_dpaa_fqs; 3026 } 3027 3028 priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]); 3029 priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]); 3030 3031 /* All real interfaces need their ports initialized */ 3032 err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs, 3033 &priv->buf_layout[0], dev); 3034 if (err) 3035 goto free_dpaa_fqs; 3036 3037 /* Rx traffic distribution based on keygen hashing defaults to on */ 3038 priv->keygen_in_use = true; 3039 3040 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); 3041 if (!priv->percpu_priv) { 3042 dev_err(dev, "devm_alloc_percpu() failed\n"); 3043 err = -ENOMEM; 3044 goto free_dpaa_fqs; 3045 } 3046 3047 priv->num_tc = 1; 3048 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 3049 3050 /* Initialize NAPI */ 3051 err = dpaa_napi_add(net_dev); 3052 if (err < 0) 3053 goto delete_dpaa_napi; 3054 3055 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout); 3056 if (err < 0) 3057 goto delete_dpaa_napi; 3058 3059 dpaa_eth_sysfs_init(&net_dev->dev); 3060 3061 netif_info(priv, probe, net_dev, "Probed interface %s\n", 3062 net_dev->name); 3063 3064 return 0; 3065 3066 delete_dpaa_napi: 3067 dpaa_napi_del(net_dev); 3068 free_dpaa_fqs: 3069 dpaa_fq_free(dev, &priv->dpaa_fq_list); 3070 qman_delete_cgr_safe(&priv->ingress_cgr); 3071 qman_release_cgrid(priv->ingress_cgr.cgrid); 3072 delete_egress_cgr: 3073 qman_delete_cgr_safe(&priv->cgr_data.cgr); 3074 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 3075 free_dpaa_bps: 3076 dpaa_bps_free(priv); 3077 free_netdev: 3078 dev_set_drvdata(dev, NULL); 3079 free_netdev(net_dev); 3080 3081 return err; 3082 } 3083 3084 static int dpaa_remove(struct platform_device *pdev) 3085 { 3086 struct net_device *net_dev; 3087 struct dpaa_priv *priv; 3088 struct device *dev; 3089 int err; 3090 3091 dev = &pdev->dev; 3092 net_dev = dev_get_drvdata(dev); 3093 3094 priv = netdev_priv(net_dev); 3095 3096 dpaa_eth_sysfs_remove(dev); 3097 3098 dev_set_drvdata(dev, NULL); 3099 unregister_netdev(net_dev); 3100 3101 err = dpaa_fq_free(dev, &priv->dpaa_fq_list); 3102 3103 qman_delete_cgr_safe(&priv->ingress_cgr); 3104 qman_release_cgrid(priv->ingress_cgr.cgrid); 3105 qman_delete_cgr_safe(&priv->cgr_data.cgr); 3106 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 3107 3108 dpaa_napi_del(net_dev); 3109 3110 dpaa_bps_free(priv); 3111 3112 free_netdev(net_dev); 3113 3114 return err; 3115 } 3116 3117 static const struct platform_device_id dpaa_devtype[] = { 3118 { 3119 .name = "dpaa-ethernet", 3120 .driver_data = 0, 3121 }, { 3122 } 3123 }; 3124 MODULE_DEVICE_TABLE(platform, dpaa_devtype); 3125 3126 static struct platform_driver dpaa_driver = { 3127 .driver = { 3128 .name = KBUILD_MODNAME, 3129 }, 3130 .id_table = dpaa_devtype, 3131 .probe = dpaa_eth_probe, 3132 .remove = dpaa_remove 3133 }; 3134 3135 static int __init dpaa_load(void) 3136 { 3137 int err; 3138 3139 pr_debug("FSL DPAA Ethernet driver\n"); 3140 3141 /* initialize dpaa_eth mirror values */ 3142 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom(); 3143 dpaa_max_frm = fman_get_max_frm(); 3144 3145 err = platform_driver_register(&dpaa_driver); 3146 if (err < 0) 3147 pr_err("Error, platform_driver_register() = %d\n", err); 3148 3149 return err; 3150 } 3151 module_init(dpaa_load); 3152 3153 static void __exit dpaa_unload(void) 3154 { 3155 platform_driver_unregister(&dpaa_driver); 3156 3157 /* Only one channel is used and needs to be released after all 3158 * interfaces are removed 3159 */ 3160 dpaa_release_channel(); 3161 } 3162 module_exit(dpaa_unload); 3163 3164 MODULE_LICENSE("Dual BSD/GPL"); 3165 MODULE_DESCRIPTION("FSL DPAA Ethernet driver"); 3166