1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Christoph Hellwig. 4 * 5 * DMA operations that map physical memory directly without using an IOMMU. 6 */ 7 #include <linux/memblock.h> /* for max_pfn */ 8 #include <linux/export.h> 9 #include <linux/mm.h> 10 #include <linux/dma-direct.h> 11 #include <linux/scatterlist.h> 12 #include <linux/dma-contiguous.h> 13 #include <linux/dma-noncoherent.h> 14 #include <linux/pfn.h> 15 #include <linux/vmalloc.h> 16 #include <linux/set_memory.h> 17 #include <linux/swiotlb.h> 18 19 /* 20 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use it 21 * it for entirely different regions. In that case the arch code needs to 22 * override the variable below for dma-direct to work properly. 23 */ 24 unsigned int zone_dma_bits __ro_after_init = 24; 25 26 static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size) 27 { 28 if (!dev->dma_mask) { 29 dev_err_once(dev, "DMA map on device without dma_mask\n"); 30 } else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_limit) { 31 dev_err_once(dev, 32 "overflow %pad+%zu of DMA mask %llx bus limit %llx\n", 33 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); 34 } 35 WARN_ON_ONCE(1); 36 } 37 38 static inline dma_addr_t phys_to_dma_direct(struct device *dev, 39 phys_addr_t phys) 40 { 41 if (force_dma_unencrypted(dev)) 42 return __phys_to_dma(dev, phys); 43 return phys_to_dma(dev, phys); 44 } 45 46 static inline struct page *dma_direct_to_page(struct device *dev, 47 dma_addr_t dma_addr) 48 { 49 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr))); 50 } 51 52 u64 dma_direct_get_required_mask(struct device *dev) 53 { 54 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT); 55 56 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1; 57 } 58 59 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask, 60 u64 *phys_limit) 61 { 62 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit); 63 64 if (force_dma_unencrypted(dev)) 65 *phys_limit = __dma_to_phys(dev, dma_limit); 66 else 67 *phys_limit = dma_to_phys(dev, dma_limit); 68 69 /* 70 * Optimistically try the zone that the physical address mask falls 71 * into first. If that returns memory that isn't actually addressable 72 * we will fallback to the next lower zone and try again. 73 * 74 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding 75 * zones. 76 */ 77 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits)) 78 return GFP_DMA; 79 if (*phys_limit <= DMA_BIT_MASK(32)) 80 return GFP_DMA32; 81 return 0; 82 } 83 84 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size) 85 { 86 return phys_to_dma_direct(dev, phys) + size - 1 <= 87 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit); 88 } 89 90 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size, 91 gfp_t gfp, unsigned long attrs) 92 { 93 size_t alloc_size = PAGE_ALIGN(size); 94 int node = dev_to_node(dev); 95 struct page *page = NULL; 96 u64 phys_limit; 97 98 if (attrs & DMA_ATTR_NO_WARN) 99 gfp |= __GFP_NOWARN; 100 101 /* we always manually zero the memory once we are done: */ 102 gfp &= ~__GFP_ZERO; 103 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask, 104 &phys_limit); 105 page = dma_alloc_contiguous(dev, alloc_size, gfp); 106 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 107 dma_free_contiguous(dev, page, alloc_size); 108 page = NULL; 109 } 110 again: 111 if (!page) 112 page = alloc_pages_node(node, gfp, get_order(alloc_size)); 113 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 114 dma_free_contiguous(dev, page, size); 115 page = NULL; 116 117 if (IS_ENABLED(CONFIG_ZONE_DMA32) && 118 phys_limit < DMA_BIT_MASK(64) && 119 !(gfp & (GFP_DMA32 | GFP_DMA))) { 120 gfp |= GFP_DMA32; 121 goto again; 122 } 123 124 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) { 125 gfp = (gfp & ~GFP_DMA32) | GFP_DMA; 126 goto again; 127 } 128 } 129 130 return page; 131 } 132 133 void *dma_direct_alloc_pages(struct device *dev, size_t size, 134 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 135 { 136 struct page *page; 137 void *ret; 138 139 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 140 dma_alloc_need_uncached(dev, attrs) && 141 !gfpflags_allow_blocking(gfp)) { 142 ret = dma_alloc_from_pool(PAGE_ALIGN(size), &page, gfp); 143 if (!ret) 144 return NULL; 145 goto done; 146 } 147 148 page = __dma_direct_alloc_pages(dev, size, gfp, attrs); 149 if (!page) 150 return NULL; 151 152 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 153 !force_dma_unencrypted(dev)) { 154 /* remove any dirty cache lines on the kernel alias */ 155 if (!PageHighMem(page)) 156 arch_dma_prep_coherent(page, size); 157 /* return the page pointer as the opaque cookie */ 158 ret = page; 159 goto done; 160 } 161 162 if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 163 dma_alloc_need_uncached(dev, attrs)) || 164 (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) { 165 /* remove any dirty cache lines on the kernel alias */ 166 arch_dma_prep_coherent(page, PAGE_ALIGN(size)); 167 168 /* create a coherent mapping */ 169 ret = dma_common_contiguous_remap(page, PAGE_ALIGN(size), 170 dma_pgprot(dev, PAGE_KERNEL, attrs), 171 __builtin_return_address(0)); 172 if (!ret) { 173 dma_free_contiguous(dev, page, size); 174 return ret; 175 } 176 177 memset(ret, 0, size); 178 goto done; 179 } 180 181 if (PageHighMem(page)) { 182 /* 183 * Depending on the cma= arguments and per-arch setup 184 * dma_alloc_contiguous could return highmem pages. 185 * Without remapping there is no way to return them here, 186 * so log an error and fail. 187 */ 188 dev_info(dev, "Rejecting highmem page from CMA.\n"); 189 dma_free_contiguous(dev, page, size); 190 return NULL; 191 } 192 193 ret = page_address(page); 194 if (force_dma_unencrypted(dev)) 195 set_memory_decrypted((unsigned long)ret, 1 << get_order(size)); 196 197 memset(ret, 0, size); 198 199 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 200 dma_alloc_need_uncached(dev, attrs)) { 201 arch_dma_prep_coherent(page, size); 202 ret = uncached_kernel_address(ret); 203 } 204 done: 205 if (force_dma_unencrypted(dev)) 206 *dma_handle = __phys_to_dma(dev, page_to_phys(page)); 207 else 208 *dma_handle = phys_to_dma(dev, page_to_phys(page)); 209 return ret; 210 } 211 212 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr, 213 dma_addr_t dma_addr, unsigned long attrs) 214 { 215 unsigned int page_order = get_order(size); 216 217 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 218 !force_dma_unencrypted(dev)) { 219 /* cpu_addr is a struct page cookie, not a kernel address */ 220 dma_free_contiguous(dev, cpu_addr, size); 221 return; 222 } 223 224 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 225 dma_free_from_pool(cpu_addr, PAGE_ALIGN(size))) 226 return; 227 228 if (force_dma_unencrypted(dev)) 229 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order); 230 231 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) 232 vunmap(cpu_addr); 233 234 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size); 235 } 236 237 void *dma_direct_alloc(struct device *dev, size_t size, 238 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 239 { 240 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 241 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 242 dma_alloc_need_uncached(dev, attrs)) 243 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs); 244 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs); 245 } 246 247 void dma_direct_free(struct device *dev, size_t size, 248 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs) 249 { 250 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 251 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 252 dma_alloc_need_uncached(dev, attrs)) 253 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs); 254 else 255 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs); 256 } 257 258 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ 259 defined(CONFIG_SWIOTLB) 260 void dma_direct_sync_single_for_device(struct device *dev, 261 dma_addr_t addr, size_t size, enum dma_data_direction dir) 262 { 263 phys_addr_t paddr = dma_to_phys(dev, addr); 264 265 if (unlikely(is_swiotlb_buffer(paddr))) 266 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE); 267 268 if (!dev_is_dma_coherent(dev)) 269 arch_sync_dma_for_device(paddr, size, dir); 270 } 271 EXPORT_SYMBOL(dma_direct_sync_single_for_device); 272 273 void dma_direct_sync_sg_for_device(struct device *dev, 274 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 275 { 276 struct scatterlist *sg; 277 int i; 278 279 for_each_sg(sgl, sg, nents, i) { 280 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); 281 282 if (unlikely(is_swiotlb_buffer(paddr))) 283 swiotlb_tbl_sync_single(dev, paddr, sg->length, 284 dir, SYNC_FOR_DEVICE); 285 286 if (!dev_is_dma_coherent(dev)) 287 arch_sync_dma_for_device(paddr, sg->length, 288 dir); 289 } 290 } 291 EXPORT_SYMBOL(dma_direct_sync_sg_for_device); 292 #endif 293 294 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ 295 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \ 296 defined(CONFIG_SWIOTLB) 297 void dma_direct_sync_single_for_cpu(struct device *dev, 298 dma_addr_t addr, size_t size, enum dma_data_direction dir) 299 { 300 phys_addr_t paddr = dma_to_phys(dev, addr); 301 302 if (!dev_is_dma_coherent(dev)) { 303 arch_sync_dma_for_cpu(paddr, size, dir); 304 arch_sync_dma_for_cpu_all(); 305 } 306 307 if (unlikely(is_swiotlb_buffer(paddr))) 308 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU); 309 } 310 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu); 311 312 void dma_direct_sync_sg_for_cpu(struct device *dev, 313 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 314 { 315 struct scatterlist *sg; 316 int i; 317 318 for_each_sg(sgl, sg, nents, i) { 319 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); 320 321 if (!dev_is_dma_coherent(dev)) 322 arch_sync_dma_for_cpu(paddr, sg->length, dir); 323 324 if (unlikely(is_swiotlb_buffer(paddr))) 325 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir, 326 SYNC_FOR_CPU); 327 } 328 329 if (!dev_is_dma_coherent(dev)) 330 arch_sync_dma_for_cpu_all(); 331 } 332 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu); 333 334 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr, 335 size_t size, enum dma_data_direction dir, unsigned long attrs) 336 { 337 phys_addr_t phys = dma_to_phys(dev, addr); 338 339 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 340 dma_direct_sync_single_for_cpu(dev, addr, size, dir); 341 342 if (unlikely(is_swiotlb_buffer(phys))) 343 swiotlb_tbl_unmap_single(dev, phys, size, size, dir, attrs); 344 } 345 EXPORT_SYMBOL(dma_direct_unmap_page); 346 347 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl, 348 int nents, enum dma_data_direction dir, unsigned long attrs) 349 { 350 struct scatterlist *sg; 351 int i; 352 353 for_each_sg(sgl, sg, nents, i) 354 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir, 355 attrs); 356 } 357 EXPORT_SYMBOL(dma_direct_unmap_sg); 358 #endif 359 360 static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr, 361 size_t size) 362 { 363 return swiotlb_force != SWIOTLB_FORCE && 364 dma_capable(dev, dma_addr, size, true); 365 } 366 367 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page, 368 unsigned long offset, size_t size, enum dma_data_direction dir, 369 unsigned long attrs) 370 { 371 phys_addr_t phys = page_to_phys(page) + offset; 372 dma_addr_t dma_addr = phys_to_dma(dev, phys); 373 374 if (unlikely(!dma_direct_possible(dev, dma_addr, size)) && 375 !swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) { 376 report_addr(dev, dma_addr, size); 377 return DMA_MAPPING_ERROR; 378 } 379 380 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 381 arch_sync_dma_for_device(phys, size, dir); 382 return dma_addr; 383 } 384 EXPORT_SYMBOL(dma_direct_map_page); 385 386 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents, 387 enum dma_data_direction dir, unsigned long attrs) 388 { 389 int i; 390 struct scatterlist *sg; 391 392 for_each_sg(sgl, sg, nents, i) { 393 sg->dma_address = dma_direct_map_page(dev, sg_page(sg), 394 sg->offset, sg->length, dir, attrs); 395 if (sg->dma_address == DMA_MAPPING_ERROR) 396 goto out_unmap; 397 sg_dma_len(sg) = sg->length; 398 } 399 400 return nents; 401 402 out_unmap: 403 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC); 404 return 0; 405 } 406 EXPORT_SYMBOL(dma_direct_map_sg); 407 408 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr, 409 size_t size, enum dma_data_direction dir, unsigned long attrs) 410 { 411 dma_addr_t dma_addr = paddr; 412 413 if (unlikely(!dma_capable(dev, dma_addr, size, false))) { 414 report_addr(dev, dma_addr, size); 415 return DMA_MAPPING_ERROR; 416 } 417 418 return dma_addr; 419 } 420 EXPORT_SYMBOL(dma_direct_map_resource); 421 422 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt, 423 void *cpu_addr, dma_addr_t dma_addr, size_t size, 424 unsigned long attrs) 425 { 426 struct page *page = dma_direct_to_page(dev, dma_addr); 427 int ret; 428 429 ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 430 if (!ret) 431 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 432 return ret; 433 } 434 435 #ifdef CONFIG_MMU 436 bool dma_direct_can_mmap(struct device *dev) 437 { 438 return dev_is_dma_coherent(dev) || 439 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP); 440 } 441 442 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma, 443 void *cpu_addr, dma_addr_t dma_addr, size_t size, 444 unsigned long attrs) 445 { 446 unsigned long user_count = vma_pages(vma); 447 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 448 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr)); 449 int ret = -ENXIO; 450 451 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs); 452 453 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) 454 return ret; 455 456 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff) 457 return -ENXIO; 458 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, 459 user_count << PAGE_SHIFT, vma->vm_page_prot); 460 } 461 #else /* CONFIG_MMU */ 462 bool dma_direct_can_mmap(struct device *dev) 463 { 464 return false; 465 } 466 467 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma, 468 void *cpu_addr, dma_addr_t dma_addr, size_t size, 469 unsigned long attrs) 470 { 471 return -ENXIO; 472 } 473 #endif /* CONFIG_MMU */ 474 475 /* 476 * Because 32-bit DMA masks are so common we expect every architecture to be 477 * able to satisfy them - either by not supporting more physical memory, or by 478 * providing a ZONE_DMA32. If neither is the case, the architecture needs to 479 * use an IOMMU instead of the direct mapping. 480 */ 481 int dma_direct_supported(struct device *dev, u64 mask) 482 { 483 u64 min_mask; 484 485 if (IS_ENABLED(CONFIG_ZONE_DMA)) 486 min_mask = DMA_BIT_MASK(zone_dma_bits); 487 else 488 min_mask = DMA_BIT_MASK(32); 489 490 min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT); 491 492 /* 493 * This check needs to be against the actual bit mask value, so 494 * use __phys_to_dma() here so that the SME encryption mask isn't 495 * part of the check. 496 */ 497 return mask >= __phys_to_dma(dev, min_mask); 498 } 499 500 size_t dma_direct_max_mapping_size(struct device *dev) 501 { 502 /* If SWIOTLB is active, use its maximum mapping size */ 503 if (is_swiotlb_active() && 504 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE)) 505 return swiotlb_max_mapping_size(dev); 506 return SIZE_MAX; 507 } 508