1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 /* register offsets */ 32 #define ICSCR 0x00 /* slave ctrl */ 33 #define ICMCR 0x04 /* master ctrl */ 34 #define ICSSR 0x08 /* slave status */ 35 #define ICMSR 0x0C /* master status */ 36 #define ICSIER 0x10 /* slave irq enable */ 37 #define ICMIER 0x14 /* master irq enable */ 38 #define ICCCR 0x18 /* clock dividers */ 39 #define ICSAR 0x1C /* slave address */ 40 #define ICMAR 0x20 /* master address */ 41 #define ICRXTX 0x24 /* data port */ 42 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 43 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 44 45 /* ICSCR */ 46 #define SDBS (1 << 3) /* slave data buffer select */ 47 #define SIE (1 << 2) /* slave interface enable */ 48 #define GCAE (1 << 1) /* general call address enable */ 49 #define FNA (1 << 0) /* forced non acknowledgment */ 50 51 /* ICMCR */ 52 #define MDBS (1 << 7) /* non-fifo mode switch */ 53 #define FSCL (1 << 6) /* override SCL pin */ 54 #define FSDA (1 << 5) /* override SDA pin */ 55 #define OBPC (1 << 4) /* override pins */ 56 #define MIE (1 << 3) /* master if enable */ 57 #define TSBE (1 << 2) 58 #define FSB (1 << 1) /* force stop bit */ 59 #define ESG (1 << 0) /* enable start bit gen */ 60 61 /* ICSSR (also for ICSIER) */ 62 #define GCAR (1 << 6) /* general call received */ 63 #define STM (1 << 5) /* slave transmit mode */ 64 #define SSR (1 << 4) /* stop received */ 65 #define SDE (1 << 3) /* slave data empty */ 66 #define SDT (1 << 2) /* slave data transmitted */ 67 #define SDR (1 << 1) /* slave data received */ 68 #define SAR (1 << 0) /* slave addr received */ 69 70 /* ICMSR (also for ICMIE) */ 71 #define MNR (1 << 6) /* nack received */ 72 #define MAL (1 << 5) /* arbitration lost */ 73 #define MST (1 << 4) /* sent a stop */ 74 #define MDE (1 << 3) 75 #define MDT (1 << 2) 76 #define MDR (1 << 1) 77 #define MAT (1 << 0) /* slave addr xfer done */ 78 79 /* ICDMAER */ 80 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 81 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 82 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 83 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 84 85 /* ICFBSCR */ 86 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 87 88 #define RCAR_MIN_DMA_LEN 8 89 90 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 91 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 92 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 93 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 94 95 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 96 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 97 #define RCAR_IRQ_STOP (MST) 98 99 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 100 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 101 102 #define ID_LAST_MSG (1 << 0) 103 #define ID_FIRST_MSG (1 << 1) 104 #define ID_DONE (1 << 2) 105 #define ID_ARBLOST (1 << 3) 106 #define ID_NACK (1 << 4) 107 /* persistent flags */ 108 #define ID_P_REP_AFTER_RD BIT(29) 109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 110 #define ID_P_PM_BLOCKED BIT(31) 111 #define ID_P_MASK GENMASK(31, 29) 112 113 enum rcar_i2c_type { 114 I2C_RCAR_GEN1, 115 I2C_RCAR_GEN2, 116 I2C_RCAR_GEN3, 117 }; 118 119 struct rcar_i2c_priv { 120 void __iomem *io; 121 struct i2c_adapter adap; 122 struct i2c_msg *msg; 123 int msgs_left; 124 struct clk *clk; 125 126 wait_queue_head_t wait; 127 128 int pos; 129 u32 icccr; 130 u32 flags; 131 u8 recovery_icmcr; /* protected by adapter lock */ 132 enum rcar_i2c_type devtype; 133 struct i2c_client *slave; 134 135 struct resource *res; 136 struct dma_chan *dma_tx; 137 struct dma_chan *dma_rx; 138 struct scatterlist sg; 139 enum dma_data_direction dma_direction; 140 141 struct reset_control *rstc; 142 int irq; 143 }; 144 145 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 146 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 147 148 #define LOOP_TIMEOUT 1024 149 150 151 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 152 { 153 writel(val, priv->io + reg); 154 } 155 156 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 157 { 158 return readl(priv->io + reg); 159 } 160 161 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 162 { 163 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 164 165 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 166 167 }; 168 169 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 170 { 171 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 172 173 if (val) 174 priv->recovery_icmcr |= FSCL; 175 else 176 priv->recovery_icmcr &= ~FSCL; 177 178 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 179 }; 180 181 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 182 { 183 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 184 185 if (val) 186 priv->recovery_icmcr |= FSDA; 187 else 188 priv->recovery_icmcr &= ~FSDA; 189 190 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 191 }; 192 193 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 194 { 195 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 196 197 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 198 199 }; 200 201 static struct i2c_bus_recovery_info rcar_i2c_bri = { 202 .get_scl = rcar_i2c_get_scl, 203 .set_scl = rcar_i2c_set_scl, 204 .set_sda = rcar_i2c_set_sda, 205 .get_bus_free = rcar_i2c_get_bus_free, 206 .recover_bus = i2c_generic_scl_recovery, 207 }; 208 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 209 { 210 /* reset master mode */ 211 rcar_i2c_write(priv, ICMIER, 0); 212 rcar_i2c_write(priv, ICMCR, MDBS); 213 rcar_i2c_write(priv, ICMSR, 0); 214 /* start clock */ 215 rcar_i2c_write(priv, ICCCR, priv->icccr); 216 217 if (priv->devtype == I2C_RCAR_GEN3) 218 rcar_i2c_write(priv, ICFBSCR, TCYC17); 219 220 } 221 222 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 223 { 224 int i; 225 226 for (i = 0; i < LOOP_TIMEOUT; i++) { 227 /* make sure that bus is not busy */ 228 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 229 return 0; 230 udelay(1); 231 } 232 233 /* Waiting did not help, try to recover */ 234 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 235 return i2c_recover_bus(&priv->adap); 236 } 237 238 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 239 { 240 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 241 unsigned long rate; 242 struct device *dev = rcar_i2c_priv_to_dev(priv); 243 struct i2c_timings t = { 244 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 245 .scl_fall_ns = 35, 246 .scl_rise_ns = 200, 247 .scl_int_delay_ns = 50, 248 }; 249 250 /* Fall back to previously used values if not supplied */ 251 i2c_parse_fw_timings(dev, &t, false); 252 253 switch (priv->devtype) { 254 case I2C_RCAR_GEN1: 255 cdf_width = 2; 256 break; 257 case I2C_RCAR_GEN2: 258 case I2C_RCAR_GEN3: 259 cdf_width = 3; 260 break; 261 default: 262 dev_err(dev, "device type error\n"); 263 return -EIO; 264 } 265 266 /* 267 * calculate SCL clock 268 * see 269 * ICCCR 270 * 271 * ick = clkp / (1 + CDF) 272 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 273 * 274 * ick : I2C internal clock < 20 MHz 275 * ticf : I2C SCL falling time 276 * tr : I2C SCL rising time 277 * intd : LSI internal delay 278 * clkp : peripheral_clk 279 * F[] : integer up-valuation 280 */ 281 rate = clk_get_rate(priv->clk); 282 cdf = rate / 20000000; 283 if (cdf >= 1U << cdf_width) { 284 dev_err(dev, "Input clock %lu too high\n", rate); 285 return -EIO; 286 } 287 ick = rate / (cdf + 1); 288 289 /* 290 * it is impossible to calculate large scale 291 * number on u32. separate it 292 * 293 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 294 * = F[sum * ick / 1000000000] 295 * = F[(ick / 1000000) * sum / 1000] 296 */ 297 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 298 round = (ick + 500000) / 1000000 * sum; 299 round = (round + 500) / 1000; 300 301 /* 302 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 303 * 304 * Calculation result (= SCL) should be less than 305 * bus_speed for hardware safety 306 * 307 * We could use something along the lines of 308 * div = ick / (bus_speed + 1) + 1; 309 * scgd = (div - 20 - round + 7) / 8; 310 * scl = ick / (20 + (scgd * 8) + round); 311 * (not fully verified) but that would get pretty involved 312 */ 313 for (scgd = 0; scgd < 0x40; scgd++) { 314 scl = ick / (20 + (scgd * 8) + round); 315 if (scl <= t.bus_freq_hz) 316 goto scgd_find; 317 } 318 dev_err(dev, "it is impossible to calculate best SCL\n"); 319 return -EIO; 320 321 scgd_find: 322 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 323 scl, t.bus_freq_hz, rate, round, cdf, scgd); 324 325 /* keep icccr value */ 326 priv->icccr = scgd << cdf_width | cdf; 327 328 return 0; 329 } 330 331 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 332 { 333 int read = !!rcar_i2c_is_recv(priv); 334 335 priv->pos = 0; 336 if (priv->msgs_left == 1) 337 priv->flags |= ID_LAST_MSG; 338 339 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 340 /* 341 * We don't have a test case but the HW engineers say that the write order 342 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 343 * it didn't cause a drawback for me, let's rather be safe than sorry. 344 */ 345 if (priv->flags & ID_FIRST_MSG) { 346 rcar_i2c_write(priv, ICMSR, 0); 347 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 348 } else { 349 if (priv->flags & ID_P_REP_AFTER_RD) 350 priv->flags &= ~ID_P_REP_AFTER_RD; 351 else 352 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 353 rcar_i2c_write(priv, ICMSR, 0); 354 } 355 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 356 } 357 358 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 359 { 360 priv->msg++; 361 priv->msgs_left--; 362 priv->flags &= ID_P_MASK; 363 rcar_i2c_prepare_msg(priv); 364 } 365 366 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 367 { 368 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 369 ? priv->dma_rx : priv->dma_tx; 370 371 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 372 sg_dma_len(&priv->sg), priv->dma_direction); 373 374 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 375 if (priv->devtype == I2C_RCAR_GEN3 && 376 priv->dma_direction == DMA_FROM_DEVICE) 377 priv->flags |= ID_P_NO_RXDMA; 378 379 priv->dma_direction = DMA_NONE; 380 381 /* Disable DMA Master Received/Transmitted, must be last! */ 382 rcar_i2c_write(priv, ICDMAER, 0); 383 } 384 385 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 386 { 387 if (priv->dma_direction == DMA_NONE) 388 return; 389 else if (priv->dma_direction == DMA_FROM_DEVICE) 390 dmaengine_terminate_all(priv->dma_rx); 391 else if (priv->dma_direction == DMA_TO_DEVICE) 392 dmaengine_terminate_all(priv->dma_tx); 393 394 rcar_i2c_dma_unmap(priv); 395 } 396 397 static void rcar_i2c_dma_callback(void *data) 398 { 399 struct rcar_i2c_priv *priv = data; 400 401 priv->pos += sg_dma_len(&priv->sg); 402 403 rcar_i2c_dma_unmap(priv); 404 } 405 406 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 407 { 408 struct device *dev = rcar_i2c_priv_to_dev(priv); 409 struct i2c_msg *msg = priv->msg; 410 bool read = msg->flags & I2C_M_RD; 411 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 412 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 413 struct dma_async_tx_descriptor *txdesc; 414 dma_addr_t dma_addr; 415 dma_cookie_t cookie; 416 unsigned char *buf; 417 int len; 418 419 /* Do various checks to see if DMA is feasible at all */ 420 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 421 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 422 return false; 423 424 if (read) { 425 /* 426 * The last two bytes needs to be fetched using PIO in 427 * order for the STOP phase to work. 428 */ 429 buf = priv->msg->buf; 430 len = priv->msg->len - 2; 431 } else { 432 /* 433 * First byte in message was sent using PIO. 434 */ 435 buf = priv->msg->buf + 1; 436 len = priv->msg->len - 1; 437 } 438 439 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 440 if (dma_mapping_error(chan->device->dev, dma_addr)) { 441 dev_dbg(dev, "dma map failed, using PIO\n"); 442 return false; 443 } 444 445 sg_dma_len(&priv->sg) = len; 446 sg_dma_address(&priv->sg) = dma_addr; 447 448 priv->dma_direction = dir; 449 450 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 451 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 453 if (!txdesc) { 454 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 455 rcar_i2c_cleanup_dma(priv); 456 return false; 457 } 458 459 txdesc->callback = rcar_i2c_dma_callback; 460 txdesc->callback_param = priv; 461 462 cookie = dmaengine_submit(txdesc); 463 if (dma_submit_error(cookie)) { 464 dev_dbg(dev, "submitting dma failed, using PIO\n"); 465 rcar_i2c_cleanup_dma(priv); 466 return false; 467 } 468 469 /* Enable DMA Master Received/Transmitted */ 470 if (read) 471 rcar_i2c_write(priv, ICDMAER, RMDMAE); 472 else 473 rcar_i2c_write(priv, ICDMAER, TMDMAE); 474 475 dma_async_issue_pending(chan); 476 return true; 477 } 478 479 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 480 { 481 struct i2c_msg *msg = priv->msg; 482 483 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 484 if (!(msr & MDE)) 485 return; 486 487 /* Check if DMA can be enabled and take over */ 488 if (priv->pos == 1 && rcar_i2c_dma(priv)) 489 return; 490 491 if (priv->pos < msg->len) { 492 /* 493 * Prepare next data to ICRXTX register. 494 * This data will go to _SHIFT_ register. 495 * 496 * * 497 * [ICRXTX] -> [SHIFT] -> [I2C bus] 498 */ 499 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 500 priv->pos++; 501 } else { 502 /* 503 * The last data was pushed to ICRXTX on _PREV_ empty irq. 504 * It is on _SHIFT_ register, and will sent to I2C bus. 505 * 506 * * 507 * [ICRXTX] -> [SHIFT] -> [I2C bus] 508 */ 509 510 if (priv->flags & ID_LAST_MSG) { 511 /* 512 * If current msg is the _LAST_ msg, 513 * prepare stop condition here. 514 * ID_DONE will be set on STOP irq. 515 */ 516 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 517 } else { 518 rcar_i2c_next_msg(priv); 519 return; 520 } 521 } 522 523 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 524 } 525 526 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 527 { 528 struct i2c_msg *msg = priv->msg; 529 530 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 531 if (!(msr & MDR)) 532 return; 533 534 if (msr & MAT) { 535 /* 536 * Address transfer phase finished, but no data at this point. 537 * Try to use DMA to receive data. 538 */ 539 rcar_i2c_dma(priv); 540 } else if (priv->pos < msg->len) { 541 /* get received data */ 542 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 543 priv->pos++; 544 } 545 546 /* If next received data is the _LAST_, go to new phase. */ 547 if (priv->pos + 1 == msg->len) { 548 if (priv->flags & ID_LAST_MSG) { 549 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 550 } else { 551 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 552 priv->flags |= ID_P_REP_AFTER_RD; 553 } 554 } 555 556 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 557 rcar_i2c_next_msg(priv); 558 else 559 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 560 } 561 562 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 563 { 564 u32 ssr_raw, ssr_filtered; 565 u8 value; 566 567 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 568 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 569 570 if (!ssr_filtered) 571 return false; 572 573 /* address detected */ 574 if (ssr_filtered & SAR) { 575 /* read or write request */ 576 if (ssr_raw & STM) { 577 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 578 rcar_i2c_write(priv, ICRXTX, value); 579 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 580 } else { 581 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 582 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 583 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 584 } 585 586 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 587 } 588 589 /* master sent stop */ 590 if (ssr_filtered & SSR) { 591 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 592 rcar_i2c_write(priv, ICSIER, SAR | SSR); 593 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 594 } 595 596 /* master wants to write to us */ 597 if (ssr_filtered & SDR) { 598 int ret; 599 600 value = rcar_i2c_read(priv, ICRXTX); 601 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 602 /* Send NACK in case of error */ 603 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 604 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 605 } 606 607 /* master wants to read from us */ 608 if (ssr_filtered & SDE) { 609 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 610 rcar_i2c_write(priv, ICRXTX, value); 611 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 612 } 613 614 return true; 615 } 616 617 /* 618 * This driver has a lock-free design because there are IP cores (at least 619 * R-Car Gen2) which have an inherent race condition in their hardware design. 620 * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after 621 * the interrupt was generated, otherwise an unwanted repeated message gets 622 * generated. It turned out that taking a spinlock at the beginning of the ISR 623 * was already causing repeated messages. Thus, this driver was converted to 624 * the now lockless behaviour. Please keep this in mind when hacking the driver. 625 */ 626 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 627 { 628 struct rcar_i2c_priv *priv = ptr; 629 u32 msr, val; 630 631 /* Clear START or STOP immediately, except for REPSTART after read */ 632 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { 633 val = rcar_i2c_read(priv, ICMCR); 634 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 635 } 636 637 msr = rcar_i2c_read(priv, ICMSR); 638 639 /* Only handle interrupts that are currently enabled */ 640 msr &= rcar_i2c_read(priv, ICMIER); 641 if (!msr) { 642 if (rcar_i2c_slave_irq(priv)) 643 return IRQ_HANDLED; 644 645 return IRQ_NONE; 646 } 647 648 /* Arbitration lost */ 649 if (msr & MAL) { 650 priv->flags |= ID_DONE | ID_ARBLOST; 651 goto out; 652 } 653 654 /* Nack */ 655 if (msr & MNR) { 656 /* HW automatically sends STOP after received NACK */ 657 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 658 priv->flags |= ID_NACK; 659 goto out; 660 } 661 662 /* Stop */ 663 if (msr & MST) { 664 priv->msgs_left--; /* The last message also made it */ 665 priv->flags |= ID_DONE; 666 goto out; 667 } 668 669 if (rcar_i2c_is_recv(priv)) 670 rcar_i2c_irq_recv(priv, msr); 671 else 672 rcar_i2c_irq_send(priv, msr); 673 674 out: 675 if (priv->flags & ID_DONE) { 676 rcar_i2c_write(priv, ICMIER, 0); 677 rcar_i2c_write(priv, ICMSR, 0); 678 wake_up(&priv->wait); 679 } 680 681 return IRQ_HANDLED; 682 } 683 684 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 685 enum dma_transfer_direction dir, 686 dma_addr_t port_addr) 687 { 688 struct dma_chan *chan; 689 struct dma_slave_config cfg; 690 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 691 int ret; 692 693 chan = dma_request_chan(dev, chan_name); 694 if (IS_ERR(chan)) { 695 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 696 chan_name, PTR_ERR(chan)); 697 return chan; 698 } 699 700 memset(&cfg, 0, sizeof(cfg)); 701 cfg.direction = dir; 702 if (dir == DMA_MEM_TO_DEV) { 703 cfg.dst_addr = port_addr; 704 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 705 } else { 706 cfg.src_addr = port_addr; 707 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 708 } 709 710 ret = dmaengine_slave_config(chan, &cfg); 711 if (ret) { 712 dev_dbg(dev, "slave_config failed for %s (%d)\n", 713 chan_name, ret); 714 dma_release_channel(chan); 715 return ERR_PTR(ret); 716 } 717 718 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 719 return chan; 720 } 721 722 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 723 struct i2c_msg *msg) 724 { 725 struct device *dev = rcar_i2c_priv_to_dev(priv); 726 bool read; 727 struct dma_chan *chan; 728 enum dma_transfer_direction dir; 729 730 read = msg->flags & I2C_M_RD; 731 732 chan = read ? priv->dma_rx : priv->dma_tx; 733 if (PTR_ERR(chan) != -EPROBE_DEFER) 734 return; 735 736 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 737 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 738 739 if (read) 740 priv->dma_rx = chan; 741 else 742 priv->dma_tx = chan; 743 } 744 745 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 746 { 747 if (!IS_ERR(priv->dma_tx)) { 748 dma_release_channel(priv->dma_tx); 749 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 750 } 751 752 if (!IS_ERR(priv->dma_rx)) { 753 dma_release_channel(priv->dma_rx); 754 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 755 } 756 } 757 758 /* I2C is a special case, we need to poll the status of a reset */ 759 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 760 { 761 int i, ret; 762 763 ret = reset_control_reset(priv->rstc); 764 if (ret) 765 return ret; 766 767 for (i = 0; i < LOOP_TIMEOUT; i++) { 768 ret = reset_control_status(priv->rstc); 769 if (ret == 0) 770 return 0; 771 udelay(1); 772 } 773 774 return -ETIMEDOUT; 775 } 776 777 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 778 struct i2c_msg *msgs, 779 int num) 780 { 781 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 782 struct device *dev = rcar_i2c_priv_to_dev(priv); 783 int i, ret; 784 long time_left; 785 786 pm_runtime_get_sync(dev); 787 788 /* Check bus state before init otherwise bus busy info will be lost */ 789 ret = rcar_i2c_bus_barrier(priv); 790 if (ret < 0) 791 goto out; 792 793 /* Gen3 needs a reset before allowing RXDMA once */ 794 if (priv->devtype == I2C_RCAR_GEN3) { 795 priv->flags |= ID_P_NO_RXDMA; 796 if (!IS_ERR(priv->rstc)) { 797 ret = rcar_i2c_do_reset(priv); 798 if (ret == 0) 799 priv->flags &= ~ID_P_NO_RXDMA; 800 } 801 } 802 803 rcar_i2c_init(priv); 804 805 for (i = 0; i < num; i++) 806 rcar_i2c_request_dma(priv, msgs + i); 807 808 /* init first message */ 809 priv->msg = msgs; 810 priv->msgs_left = num; 811 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 812 rcar_i2c_prepare_msg(priv); 813 814 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 815 num * adap->timeout); 816 817 /* cleanup DMA if it couldn't complete properly due to an error */ 818 if (priv->dma_direction != DMA_NONE) 819 rcar_i2c_cleanup_dma(priv); 820 821 if (!time_left) { 822 rcar_i2c_init(priv); 823 ret = -ETIMEDOUT; 824 } else if (priv->flags & ID_NACK) { 825 ret = -ENXIO; 826 } else if (priv->flags & ID_ARBLOST) { 827 ret = -EAGAIN; 828 } else { 829 ret = num - priv->msgs_left; /* The number of transfer */ 830 } 831 out: 832 pm_runtime_put(dev); 833 834 if (ret < 0 && ret != -ENXIO) 835 dev_err(dev, "error %d : %x\n", ret, priv->flags); 836 837 return ret; 838 } 839 840 static int rcar_reg_slave(struct i2c_client *slave) 841 { 842 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 843 844 if (priv->slave) 845 return -EBUSY; 846 847 if (slave->flags & I2C_CLIENT_TEN) 848 return -EAFNOSUPPORT; 849 850 /* Keep device active for slave address detection logic */ 851 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 852 853 priv->slave = slave; 854 rcar_i2c_write(priv, ICSAR, slave->addr); 855 rcar_i2c_write(priv, ICSSR, 0); 856 rcar_i2c_write(priv, ICSIER, SAR | SSR); 857 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 858 859 return 0; 860 } 861 862 static int rcar_unreg_slave(struct i2c_client *slave) 863 { 864 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 865 866 WARN_ON(!priv->slave); 867 868 /* disable irqs and ensure none is running before clearing ptr */ 869 rcar_i2c_write(priv, ICSIER, 0); 870 rcar_i2c_write(priv, ICSCR, 0); 871 872 synchronize_irq(priv->irq); 873 priv->slave = NULL; 874 875 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 876 877 return 0; 878 } 879 880 static u32 rcar_i2c_func(struct i2c_adapter *adap) 881 { 882 /* 883 * This HW can't do: 884 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 885 * I2C_M_NOSTART (automatically sends address after START) 886 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 887 */ 888 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 889 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 890 } 891 892 static const struct i2c_algorithm rcar_i2c_algo = { 893 .master_xfer = rcar_i2c_master_xfer, 894 .functionality = rcar_i2c_func, 895 .reg_slave = rcar_reg_slave, 896 .unreg_slave = rcar_unreg_slave, 897 }; 898 899 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 900 .flags = I2C_AQ_NO_ZERO_LEN, 901 }; 902 903 static const struct of_device_id rcar_i2c_dt_ids[] = { 904 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 905 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 906 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 907 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 908 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 909 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 910 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 911 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 912 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 913 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 914 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 915 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 916 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 917 {}, 918 }; 919 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 920 921 static int rcar_i2c_probe(struct platform_device *pdev) 922 { 923 struct rcar_i2c_priv *priv; 924 struct i2c_adapter *adap; 925 struct device *dev = &pdev->dev; 926 int ret; 927 928 /* Otherwise logic will break because some bytes must always use PIO */ 929 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 930 931 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 932 if (!priv) 933 return -ENOMEM; 934 935 priv->clk = devm_clk_get(dev, NULL); 936 if (IS_ERR(priv->clk)) { 937 dev_err(dev, "cannot get clock\n"); 938 return PTR_ERR(priv->clk); 939 } 940 941 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 942 if (IS_ERR(priv->io)) 943 return PTR_ERR(priv->io); 944 945 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 946 init_waitqueue_head(&priv->wait); 947 948 adap = &priv->adap; 949 adap->nr = pdev->id; 950 adap->algo = &rcar_i2c_algo; 951 adap->class = I2C_CLASS_DEPRECATED; 952 adap->retries = 3; 953 adap->dev.parent = dev; 954 adap->dev.of_node = dev->of_node; 955 adap->bus_recovery_info = &rcar_i2c_bri; 956 adap->quirks = &rcar_i2c_quirks; 957 i2c_set_adapdata(adap, priv); 958 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 959 960 /* Init DMA */ 961 sg_init_table(&priv->sg, 1); 962 priv->dma_direction = DMA_NONE; 963 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 964 965 /* Activate device for clock calculation */ 966 pm_runtime_enable(dev); 967 pm_runtime_get_sync(dev); 968 ret = rcar_i2c_clock_calculate(priv); 969 if (ret < 0) 970 goto out_pm_put; 971 972 if (priv->devtype == I2C_RCAR_GEN3) { 973 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 974 if (!IS_ERR(priv->rstc)) { 975 ret = reset_control_status(priv->rstc); 976 if (ret < 0) 977 priv->rstc = ERR_PTR(-ENOTSUPP); 978 } 979 } 980 981 /* Stay always active when multi-master to keep arbitration working */ 982 if (of_property_read_bool(dev->of_node, "multi-master")) 983 priv->flags |= ID_P_PM_BLOCKED; 984 else 985 pm_runtime_put(dev); 986 987 988 priv->irq = platform_get_irq(pdev, 0); 989 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv); 990 if (ret < 0) { 991 dev_err(dev, "cannot get irq %d\n", priv->irq); 992 goto out_pm_disable; 993 } 994 995 platform_set_drvdata(pdev, priv); 996 997 ret = i2c_add_numbered_adapter(adap); 998 if (ret < 0) 999 goto out_pm_disable; 1000 1001 dev_info(dev, "probed\n"); 1002 1003 return 0; 1004 1005 out_pm_put: 1006 pm_runtime_put(dev); 1007 out_pm_disable: 1008 pm_runtime_disable(dev); 1009 return ret; 1010 } 1011 1012 static int rcar_i2c_remove(struct platform_device *pdev) 1013 { 1014 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1015 struct device *dev = &pdev->dev; 1016 1017 i2c_del_adapter(&priv->adap); 1018 rcar_i2c_release_dma(priv); 1019 if (priv->flags & ID_P_PM_BLOCKED) 1020 pm_runtime_put(dev); 1021 pm_runtime_disable(dev); 1022 1023 return 0; 1024 } 1025 1026 #ifdef CONFIG_PM_SLEEP 1027 static int rcar_i2c_suspend(struct device *dev) 1028 { 1029 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1030 1031 i2c_mark_adapter_suspended(&priv->adap); 1032 return 0; 1033 } 1034 1035 static int rcar_i2c_resume(struct device *dev) 1036 { 1037 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1038 1039 i2c_mark_adapter_resumed(&priv->adap); 1040 return 0; 1041 } 1042 1043 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1044 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1045 }; 1046 1047 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1048 #else 1049 #define DEV_PM_OPS NULL 1050 #endif /* CONFIG_PM_SLEEP */ 1051 1052 static struct platform_driver rcar_i2c_driver = { 1053 .driver = { 1054 .name = "i2c-rcar", 1055 .of_match_table = rcar_i2c_dt_ids, 1056 .pm = DEV_PM_OPS, 1057 }, 1058 .probe = rcar_i2c_probe, 1059 .remove = rcar_i2c_remove, 1060 }; 1061 1062 module_platform_driver(rcar_i2c_driver); 1063 1064 MODULE_LICENSE("GPL v2"); 1065 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1066 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1067