1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Microsemi Ocelot Switch driver 3 * Copyright (c) 2019 Microsemi Corporation 4 */ 5 6 #ifndef _OCELOT_VCAP_H_ 7 #define _OCELOT_VCAP_H_ 8 9 /* ================================================================= 10 * VCAP Common 11 * ================================================================= 12 */ 13 14 enum { 15 /* VCAP_IS1, */ 16 VCAP_IS2, 17 /* VCAP_ES0, */ 18 }; 19 20 struct vcap_props { 21 u16 tg_width; /* Type-group width (in bits) */ 22 u16 sw_count; /* Sub word count */ 23 u16 entry_count; /* Entry count */ 24 u16 entry_words; /* Number of entry words */ 25 u16 entry_width; /* Entry width (in bits) */ 26 u16 action_count; /* Action count */ 27 u16 action_words; /* Number of action words */ 28 u16 action_width; /* Action width (in bits) */ 29 u16 action_type_width; /* Action type width (in bits) */ 30 struct { 31 u16 width; /* Action type width (in bits) */ 32 u16 count; /* Action type sub word count */ 33 } action_table[2]; 34 u16 counter_words; /* Number of counter words */ 35 u16 counter_width; /* Counter width (in bits) */ 36 }; 37 38 /* VCAP Type-Group values */ 39 #define VCAP_TG_NONE 0 /* Entry is invalid */ 40 #define VCAP_TG_FULL 1 /* Full entry */ 41 #define VCAP_TG_HALF 2 /* Half entry */ 42 #define VCAP_TG_QUARTER 3 /* Quarter entry */ 43 44 /* ================================================================= 45 * VCAP IS2 46 * ================================================================= 47 */ 48 49 /* IS2 half key types */ 50 #define IS2_TYPE_ETYPE 0 51 #define IS2_TYPE_LLC 1 52 #define IS2_TYPE_SNAP 2 53 #define IS2_TYPE_ARP 3 54 #define IS2_TYPE_IP_UDP_TCP 4 55 #define IS2_TYPE_IP_OTHER 5 56 #define IS2_TYPE_IPV6 6 57 #define IS2_TYPE_OAM 7 58 #define IS2_TYPE_SMAC_SIP6 8 59 #define IS2_TYPE_ANY 100 /* Pseudo type */ 60 61 /* IS2 half key type mask for matching any IP */ 62 #define IS2_TYPE_MASK_IP_ANY 0xe 63 64 enum { 65 IS2_ACTION_TYPE_NORMAL, 66 IS2_ACTION_TYPE_SMAC_SIP, 67 IS2_ACTION_TYPE_MAX, 68 }; 69 70 /* IS2 MASK_MODE values */ 71 #define IS2_ACT_MASK_MODE_NONE 0 72 #define IS2_ACT_MASK_MODE_FILTER 1 73 #define IS2_ACT_MASK_MODE_POLICY 2 74 #define IS2_ACT_MASK_MODE_REDIR 3 75 76 /* IS2 REW_OP values */ 77 #define IS2_ACT_REW_OP_NONE 0 78 #define IS2_ACT_REW_OP_PTP_ONE 2 79 #define IS2_ACT_REW_OP_PTP_TWO 3 80 #define IS2_ACT_REW_OP_SPECIAL 8 81 #define IS2_ACT_REW_OP_PTP_ORG 9 82 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 83 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 84 #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 85 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 86 87 #define VCAP_PORT_WIDTH 4 88 89 /* IS2 quarter key - SMAC_SIP4 */ 90 #define IS2_QKO_IGR_PORT 0 91 #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 92 #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 93 #define IS2_QKL_L2_SMAC 48 94 #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 95 #define IS2_QKL_L3_IP4_SIP 32 96 97 enum vcap_is2_half_key_field { 98 /* Common */ 99 VCAP_IS2_TYPE, 100 VCAP_IS2_HK_FIRST, 101 VCAP_IS2_HK_PAG, 102 VCAP_IS2_HK_RSV1, 103 VCAP_IS2_HK_IGR_PORT_MASK, 104 VCAP_IS2_HK_RSV2, 105 VCAP_IS2_HK_HOST_MATCH, 106 VCAP_IS2_HK_L2_MC, 107 VCAP_IS2_HK_L2_BC, 108 VCAP_IS2_HK_VLAN_TAGGED, 109 VCAP_IS2_HK_VID, 110 VCAP_IS2_HK_DEI, 111 VCAP_IS2_HK_PCP, 112 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 113 VCAP_IS2_HK_L2_DMAC, 114 VCAP_IS2_HK_L2_SMAC, 115 /* MAC_ETYPE (TYPE=000) */ 116 VCAP_IS2_HK_MAC_ETYPE_ETYPE, 117 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 118 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 119 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 120 /* MAC_LLC (TYPE=001) */ 121 VCAP_IS2_HK_MAC_LLC_DMAC, 122 VCAP_IS2_HK_MAC_LLC_SMAC, 123 VCAP_IS2_HK_MAC_LLC_L2_LLC, 124 /* MAC_SNAP (TYPE=010) */ 125 VCAP_IS2_HK_MAC_SNAP_SMAC, 126 VCAP_IS2_HK_MAC_SNAP_DMAC, 127 VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 128 /* MAC_ARP (TYPE=011) */ 129 VCAP_IS2_HK_MAC_ARP_SMAC, 130 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 131 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 132 VCAP_IS2_HK_MAC_ARP_LEN_OK, 133 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 134 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 135 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 136 VCAP_IS2_HK_MAC_ARP_OPCODE, 137 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 138 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 139 VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 140 /* IP4_TCP_UDP / IP4_OTHER common */ 141 VCAP_IS2_HK_IP4, 142 VCAP_IS2_HK_L3_FRAGMENT, 143 VCAP_IS2_HK_L3_FRAG_OFS_GT0, 144 VCAP_IS2_HK_L3_OPTIONS, 145 VCAP_IS2_HK_IP4_L3_TTL_GT0, 146 VCAP_IS2_HK_L3_TOS, 147 VCAP_IS2_HK_L3_IP4_DIP, 148 VCAP_IS2_HK_L3_IP4_SIP, 149 VCAP_IS2_HK_DIP_EQ_SIP, 150 /* IP4_TCP_UDP (TYPE=100) */ 151 VCAP_IS2_HK_TCP, 152 VCAP_IS2_HK_L4_SPORT, 153 VCAP_IS2_HK_L4_DPORT, 154 VCAP_IS2_HK_L4_RNG, 155 VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 156 VCAP_IS2_HK_L4_SEQUENCE_EQ0, 157 VCAP_IS2_HK_L4_URG, 158 VCAP_IS2_HK_L4_ACK, 159 VCAP_IS2_HK_L4_PSH, 160 VCAP_IS2_HK_L4_RST, 161 VCAP_IS2_HK_L4_SYN, 162 VCAP_IS2_HK_L4_FIN, 163 VCAP_IS2_HK_L4_1588_DOM, 164 VCAP_IS2_HK_L4_1588_VER, 165 /* IP4_OTHER (TYPE=101) */ 166 VCAP_IS2_HK_IP4_L3_PROTO, 167 VCAP_IS2_HK_L3_PAYLOAD, 168 /* IP6_STD (TYPE=110) */ 169 VCAP_IS2_HK_IP6_L3_TTL_GT0, 170 VCAP_IS2_HK_IP6_L3_PROTO, 171 VCAP_IS2_HK_L3_IP6_SIP, 172 /* OAM (TYPE=111) */ 173 VCAP_IS2_HK_OAM_MEL_FLAGS, 174 VCAP_IS2_HK_OAM_VER, 175 VCAP_IS2_HK_OAM_OPCODE, 176 VCAP_IS2_HK_OAM_FLAGS, 177 VCAP_IS2_HK_OAM_MEPID, 178 VCAP_IS2_HK_OAM_CCM_CNTS_EQ0, 179 VCAP_IS2_HK_OAM_IS_Y1731, 180 }; 181 182 struct vcap_field { 183 int offset; 184 int length; 185 }; 186 187 enum vcap_is2_action_field { 188 VCAP_IS2_ACT_HIT_ME_ONCE, 189 VCAP_IS2_ACT_CPU_COPY_ENA, 190 VCAP_IS2_ACT_CPU_QU_NUM, 191 VCAP_IS2_ACT_MASK_MODE, 192 VCAP_IS2_ACT_MIRROR_ENA, 193 VCAP_IS2_ACT_LRN_DIS, 194 VCAP_IS2_ACT_POLICE_ENA, 195 VCAP_IS2_ACT_POLICE_IDX, 196 VCAP_IS2_ACT_POLICE_VCAP_ONLY, 197 VCAP_IS2_ACT_PORT_MASK, 198 VCAP_IS2_ACT_REW_OP, 199 VCAP_IS2_ACT_SMAC_REPLACE_ENA, 200 VCAP_IS2_ACT_RSV, 201 VCAP_IS2_ACT_ACL_ID, 202 VCAP_IS2_ACT_HIT_CNT, 203 }; 204 205 #endif /* _OCELOT_VCAP_H_ */ 206