1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 #include <linux/debugfs.h> 10 #include <linux/kthread.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drm_crtc.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_probe_helper.h> 16 17 #include "msm_drv.h" 18 #include "dpu_kms.h" 19 #include "dpu_hwio.h" 20 #include "dpu_hw_catalog.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_ctl.h" 23 #include "dpu_hw_dspp.h" 24 #include "dpu_formats.h" 25 #include "dpu_encoder_phys.h" 26 #include "dpu_crtc.h" 27 #include "dpu_trace.h" 28 #include "dpu_core_irq.h" 29 30 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ 31 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 32 33 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 34 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 35 36 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ 37 (p) ? (p)->parent->base.id : -1, \ 38 (p) ? (p)->intf_idx - INTF_0 : -1, \ 39 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 40 ##__VA_ARGS__) 41 42 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\ 43 (p) ? (p)->parent->base.id : -1, \ 44 (p) ? (p)->intf_idx - INTF_0 : -1, \ 45 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 46 ##__VA_ARGS__) 47 48 /* 49 * Two to anticipate panels that can do cmd/vid dynamic switching 50 * plan is to create all possible physical encoder types, and switch between 51 * them at runtime 52 */ 53 #define NUM_PHYS_ENCODER_TYPES 2 54 55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 56 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 57 58 #define MAX_CHANNELS_PER_ENC 2 59 60 #define IDLE_SHORT_TIMEOUT 1 61 62 #define MAX_HDISPLAY_SPLIT 1080 63 64 /* timeout in frames waiting for frame done */ 65 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 66 67 /** 68 * enum dpu_enc_rc_events - events for resource control state machine 69 * @DPU_ENC_RC_EVENT_KICKOFF: 70 * This event happens at NORMAL priority. 71 * Event that signals the start of the transfer. When this event is 72 * received, enable MDP/DSI core clocks. Regardless of the previous 73 * state, the resource should be in ON state at the end of this event. 74 * @DPU_ENC_RC_EVENT_FRAME_DONE: 75 * This event happens at INTERRUPT level. 76 * Event signals the end of the data transfer after the PP FRAME_DONE 77 * event. At the end of this event, a delayed work is scheduled to go to 78 * IDLE_PC state after IDLE_TIMEOUT time. 79 * @DPU_ENC_RC_EVENT_PRE_STOP: 80 * This event happens at NORMAL priority. 81 * This event, when received during the ON state, leave the RC STATE 82 * in the PRE_OFF state. It should be followed by the STOP event as 83 * part of encoder disable. 84 * If received during IDLE or OFF states, it will do nothing. 85 * @DPU_ENC_RC_EVENT_STOP: 86 * This event happens at NORMAL priority. 87 * When this event is received, disable all the MDP/DSI core clocks, and 88 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 89 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 90 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 91 * Resource state should be in OFF at the end of the event. 92 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 93 * This event happens at NORMAL priority from a work item. 94 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 95 * This would disable MDP/DSI core clocks and change the resource state 96 * to IDLE. 97 */ 98 enum dpu_enc_rc_events { 99 DPU_ENC_RC_EVENT_KICKOFF = 1, 100 DPU_ENC_RC_EVENT_FRAME_DONE, 101 DPU_ENC_RC_EVENT_PRE_STOP, 102 DPU_ENC_RC_EVENT_STOP, 103 DPU_ENC_RC_EVENT_ENTER_IDLE 104 }; 105 106 /* 107 * enum dpu_enc_rc_states - states that the resource control maintains 108 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 109 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 110 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 111 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 112 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 113 */ 114 enum dpu_enc_rc_states { 115 DPU_ENC_RC_STATE_OFF, 116 DPU_ENC_RC_STATE_PRE_OFF, 117 DPU_ENC_RC_STATE_ON, 118 DPU_ENC_RC_STATE_IDLE 119 }; 120 121 /** 122 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 123 * encoders. Virtual encoder manages one "logical" display. Physical 124 * encoders manage one intf block, tied to a specific panel/sub-panel. 125 * Virtual encoder defers as much as possible to the physical encoders. 126 * Virtual encoder registers itself with the DRM Framework as the encoder. 127 * @base: drm_encoder base class for registration with DRM 128 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 129 * @bus_scaling_client: Client handle to the bus scaling interface 130 * @enabled: True if the encoder is active, protected by enc_lock 131 * @num_phys_encs: Actual number of physical encoders contained. 132 * @phys_encs: Container of physical encoders managed. 133 * @cur_master: Pointer to the current master in this mode. Optimization 134 * Only valid after enable. Cleared as disable. 135 * @hw_pp Handle to the pingpong blocks used for the display. No. 136 * pingpong blocks can be different than num_phys_encs. 137 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped 138 * for partial update right-only cases, such as pingpong 139 * split where virtual pingpong does not generate IRQs 140 * @crtc: Pointer to the currently assigned crtc. Normally you 141 * would use crtc->state->encoder_mask to determine the 142 * link between encoder/crtc. However in this case we need 143 * to track crtc in the disable() hook which is called 144 * _after_ encoder_mask is cleared. 145 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 146 * all CTL paths 147 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 148 * @debugfs_root: Debug file system root file node 149 * @enc_lock: Lock around physical encoder 150 * create/destroy/enable/disable 151 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 152 * busy processing current command. 153 * Bit0 = phys_encs[0] etc. 154 * @crtc_frame_event_cb: callback handler for frame event 155 * @crtc_frame_event_cb_data: callback handler private data 156 * @frame_done_timeout_ms: frame done timeout in ms 157 * @frame_done_timer: watchdog timer for frame done event 158 * @vsync_event_timer: vsync timer 159 * @disp_info: local copy of msm_display_info struct 160 * @idle_pc_supported: indicate if idle power collaps is supported 161 * @rc_lock: resource control mutex lock to protect 162 * virt encoder over various state changes 163 * @rc_state: resource controller state 164 * @delayed_off_work: delayed worker to schedule disabling of 165 * clks and resources after IDLE_TIMEOUT time. 166 * @vsync_event_work: worker to handle vsync event for autorefresh 167 * @topology: topology of the display 168 * @idle_timeout: idle timeout duration in milliseconds 169 */ 170 struct dpu_encoder_virt { 171 struct drm_encoder base; 172 spinlock_t enc_spinlock; 173 uint32_t bus_scaling_client; 174 175 bool enabled; 176 177 unsigned int num_phys_encs; 178 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 179 struct dpu_encoder_phys *cur_master; 180 struct dpu_encoder_phys *cur_slave; 181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 182 183 bool intfs_swapped; 184 185 struct drm_crtc *crtc; 186 187 struct dentry *debugfs_root; 188 struct mutex enc_lock; 189 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 190 void (*crtc_frame_event_cb)(void *, u32 event); 191 void *crtc_frame_event_cb_data; 192 193 atomic_t frame_done_timeout_ms; 194 struct timer_list frame_done_timer; 195 struct timer_list vsync_event_timer; 196 197 struct msm_display_info disp_info; 198 199 bool idle_pc_supported; 200 struct mutex rc_lock; 201 enum dpu_enc_rc_states rc_state; 202 struct delayed_work delayed_off_work; 203 struct kthread_work vsync_event_work; 204 struct msm_display_topology topology; 205 206 u32 idle_timeout; 207 }; 208 209 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 210 211 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 212 enum dpu_intr_idx intr_idx) 213 { 214 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n", 215 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, 216 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 217 218 if (phys_enc->parent_ops->handle_frame_done) 219 phys_enc->parent_ops->handle_frame_done( 220 phys_enc->parent, phys_enc, 221 DPU_ENCODER_FRAME_EVENT_ERROR); 222 } 223 224 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 225 int32_t hw_id, struct dpu_encoder_wait_info *info); 226 227 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 228 enum dpu_intr_idx intr_idx, 229 struct dpu_encoder_wait_info *wait_info) 230 { 231 struct dpu_encoder_irq *irq; 232 u32 irq_status; 233 int ret; 234 235 if (!wait_info || intr_idx >= INTR_IDX_MAX) { 236 DPU_ERROR("invalid params\n"); 237 return -EINVAL; 238 } 239 irq = &phys_enc->irq[intr_idx]; 240 241 /* note: do master / slave checking outside */ 242 243 /* return EWOULDBLOCK since we know the wait isn't necessary */ 244 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 245 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", 246 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 247 irq->irq_idx); 248 return -EWOULDBLOCK; 249 } 250 251 if (irq->irq_idx < 0) { 252 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", 253 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 254 irq->name); 255 return 0; 256 } 257 258 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", 259 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 260 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, 261 atomic_read(wait_info->atomic_cnt)); 262 263 ret = dpu_encoder_helper_wait_event_timeout( 264 DRMID(phys_enc->parent), 265 irq->hw_idx, 266 wait_info); 267 268 if (ret <= 0) { 269 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, 270 irq->irq_idx, true); 271 if (irq_status) { 272 unsigned long flags; 273 274 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " 275 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 276 DRMID(phys_enc->parent), intr_idx, 277 irq->hw_idx, irq->irq_idx, 278 phys_enc->hw_pp->idx - PINGPONG_0, 279 atomic_read(wait_info->atomic_cnt)); 280 local_irq_save(flags); 281 irq->cb.func(phys_enc, irq->irq_idx); 282 local_irq_restore(flags); 283 ret = 0; 284 } else { 285 ret = -ETIMEDOUT; 286 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " 287 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 288 DRMID(phys_enc->parent), intr_idx, 289 irq->hw_idx, irq->irq_idx, 290 phys_enc->hw_pp->idx - PINGPONG_0, 291 atomic_read(wait_info->atomic_cnt)); 292 } 293 } else { 294 ret = 0; 295 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 296 intr_idx, irq->hw_idx, irq->irq_idx, 297 phys_enc->hw_pp->idx - PINGPONG_0, 298 atomic_read(wait_info->atomic_cnt)); 299 } 300 301 return ret; 302 } 303 304 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 305 enum dpu_intr_idx intr_idx) 306 { 307 struct dpu_encoder_irq *irq; 308 int ret = 0; 309 310 if (intr_idx >= INTR_IDX_MAX) { 311 DPU_ERROR("invalid params\n"); 312 return -EINVAL; 313 } 314 irq = &phys_enc->irq[intr_idx]; 315 316 if (irq->irq_idx >= 0) { 317 DPU_DEBUG_PHYS(phys_enc, 318 "skipping already registered irq %s type %d\n", 319 irq->name, irq->intr_type); 320 return 0; 321 } 322 323 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, 324 irq->intr_type, irq->hw_idx); 325 if (irq->irq_idx < 0) { 326 DPU_ERROR_PHYS(phys_enc, 327 "failed to lookup IRQ index for %s type:%d\n", 328 irq->name, irq->intr_type); 329 return -EINVAL; 330 } 331 332 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, 333 &irq->cb); 334 if (ret) { 335 DPU_ERROR_PHYS(phys_enc, 336 "failed to register IRQ callback for %s\n", 337 irq->name); 338 irq->irq_idx = -EINVAL; 339 return ret; 340 } 341 342 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); 343 if (ret) { 344 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", 345 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 346 irq->irq_idx); 347 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 348 irq->irq_idx, &irq->cb); 349 irq->irq_idx = -EINVAL; 350 return ret; 351 } 352 353 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, 354 irq->hw_idx, irq->irq_idx); 355 356 return ret; 357 } 358 359 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 360 enum dpu_intr_idx intr_idx) 361 { 362 struct dpu_encoder_irq *irq; 363 int ret; 364 365 irq = &phys_enc->irq[intr_idx]; 366 367 /* silently skip irqs that weren't registered */ 368 if (irq->irq_idx < 0) { 369 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", 370 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 371 irq->irq_idx); 372 return 0; 373 } 374 375 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); 376 if (ret) { 377 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", 378 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 379 irq->irq_idx, ret); 380 } 381 382 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, 383 &irq->cb); 384 if (ret) { 385 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", 386 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 387 irq->irq_idx, ret); 388 } 389 390 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, 391 irq->hw_idx, irq->irq_idx); 392 393 irq->irq_idx = -EINVAL; 394 395 return 0; 396 } 397 398 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, 399 struct dpu_encoder_hw_resources *hw_res) 400 { 401 struct dpu_encoder_virt *dpu_enc = NULL; 402 int i = 0; 403 404 dpu_enc = to_dpu_encoder_virt(drm_enc); 405 DPU_DEBUG_ENC(dpu_enc, "\n"); 406 407 /* Query resources used by phys encs, expected to be without overlap */ 408 memset(hw_res, 0, sizeof(*hw_res)); 409 410 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 411 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 412 413 if (phys->ops.get_hw_resources) 414 phys->ops.get_hw_resources(phys, hw_res); 415 } 416 } 417 418 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 419 { 420 struct dpu_encoder_virt *dpu_enc = NULL; 421 int i = 0; 422 423 if (!drm_enc) { 424 DPU_ERROR("invalid encoder\n"); 425 return; 426 } 427 428 dpu_enc = to_dpu_encoder_virt(drm_enc); 429 DPU_DEBUG_ENC(dpu_enc, "\n"); 430 431 mutex_lock(&dpu_enc->enc_lock); 432 433 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 434 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 435 436 if (phys->ops.destroy) { 437 phys->ops.destroy(phys); 438 --dpu_enc->num_phys_encs; 439 dpu_enc->phys_encs[i] = NULL; 440 } 441 } 442 443 if (dpu_enc->num_phys_encs) 444 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 445 dpu_enc->num_phys_encs); 446 dpu_enc->num_phys_encs = 0; 447 mutex_unlock(&dpu_enc->enc_lock); 448 449 drm_encoder_cleanup(drm_enc); 450 mutex_destroy(&dpu_enc->enc_lock); 451 } 452 453 void dpu_encoder_helper_split_config( 454 struct dpu_encoder_phys *phys_enc, 455 enum dpu_intf interface) 456 { 457 struct dpu_encoder_virt *dpu_enc; 458 struct split_pipe_cfg cfg = { 0 }; 459 struct dpu_hw_mdp *hw_mdptop; 460 struct msm_display_info *disp_info; 461 462 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 463 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 464 return; 465 } 466 467 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 468 hw_mdptop = phys_enc->hw_mdptop; 469 disp_info = &dpu_enc->disp_info; 470 471 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) 472 return; 473 474 /** 475 * disable split modes since encoder will be operating in as the only 476 * encoder, either for the entire use case in the case of, for example, 477 * single DSI, or for this frame in the case of left/right only partial 478 * update. 479 */ 480 if (phys_enc->split_role == ENC_ROLE_SOLO) { 481 if (hw_mdptop->ops.setup_split_pipe) 482 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 483 return; 484 } 485 486 cfg.en = true; 487 cfg.mode = phys_enc->intf_mode; 488 cfg.intf = interface; 489 490 if (cfg.en && phys_enc->ops.needs_single_flush && 491 phys_enc->ops.needs_single_flush(phys_enc)) 492 cfg.split_flush_en = true; 493 494 if (phys_enc->split_role == ENC_ROLE_MASTER) { 495 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 496 497 if (hw_mdptop->ops.setup_split_pipe) 498 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 499 } 500 } 501 502 static void _dpu_encoder_adjust_mode(struct drm_connector *connector, 503 struct drm_display_mode *adj_mode) 504 { 505 struct drm_display_mode *cur_mode; 506 507 if (!connector || !adj_mode) 508 return; 509 510 list_for_each_entry(cur_mode, &connector->modes, head) { 511 if (cur_mode->vdisplay == adj_mode->vdisplay && 512 cur_mode->hdisplay == adj_mode->hdisplay && 513 drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) { 514 adj_mode->private_flags |= cur_mode->private_flags; 515 } 516 } 517 } 518 519 static struct msm_display_topology dpu_encoder_get_topology( 520 struct dpu_encoder_virt *dpu_enc, 521 struct dpu_kms *dpu_kms, 522 struct drm_display_mode *mode) 523 { 524 struct msm_display_topology topology; 525 int i, intf_count = 0; 526 527 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 528 if (dpu_enc->phys_encs[i]) 529 intf_count++; 530 531 /* Datapath topology selection 532 * 533 * Dual display 534 * 2 LM, 2 INTF ( Split display using 2 interfaces) 535 * 536 * Single display 537 * 1 LM, 1 INTF 538 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 539 * 540 * Adding color blocks only to primary interface 541 */ 542 if (intf_count == 2) 543 topology.num_lm = 2; 544 else if (!dpu_kms->catalog->caps->has_3d_merge) 545 topology.num_lm = 1; 546 else 547 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 548 549 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) 550 topology.num_dspp = topology.num_lm; 551 552 topology.num_enc = 0; 553 topology.num_intf = intf_count; 554 555 return topology; 556 } 557 static int dpu_encoder_virt_atomic_check( 558 struct drm_encoder *drm_enc, 559 struct drm_crtc_state *crtc_state, 560 struct drm_connector_state *conn_state) 561 { 562 struct dpu_encoder_virt *dpu_enc; 563 struct msm_drm_private *priv; 564 struct dpu_kms *dpu_kms; 565 const struct drm_display_mode *mode; 566 struct drm_display_mode *adj_mode; 567 struct msm_display_topology topology; 568 struct dpu_global_state *global_state; 569 int i = 0; 570 int ret = 0; 571 572 if (!drm_enc || !crtc_state || !conn_state) { 573 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 574 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 575 return -EINVAL; 576 } 577 578 dpu_enc = to_dpu_encoder_virt(drm_enc); 579 DPU_DEBUG_ENC(dpu_enc, "\n"); 580 581 priv = drm_enc->dev->dev_private; 582 dpu_kms = to_dpu_kms(priv->kms); 583 mode = &crtc_state->mode; 584 adj_mode = &crtc_state->adjusted_mode; 585 global_state = dpu_kms_get_existing_global_state(dpu_kms); 586 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 587 588 /* 589 * display drivers may populate private fields of the drm display mode 590 * structure while registering possible modes of a connector with DRM. 591 * These private fields are not populated back while DRM invokes 592 * the mode_set callbacks. This module retrieves and populates the 593 * private fields of the given mode. 594 */ 595 _dpu_encoder_adjust_mode(conn_state->connector, adj_mode); 596 597 /* perform atomic check on the first physical encoder (master) */ 598 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 599 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 600 601 if (phys->ops.atomic_check) 602 ret = phys->ops.atomic_check(phys, crtc_state, 603 conn_state); 604 else if (phys->ops.mode_fixup) 605 if (!phys->ops.mode_fixup(phys, mode, adj_mode)) 606 ret = -EINVAL; 607 608 if (ret) { 609 DPU_ERROR_ENC(dpu_enc, 610 "mode unsupported, phys idx %d\n", i); 611 break; 612 } 613 } 614 615 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 616 617 /* Reserve dynamic resources now. */ 618 if (!ret) { 619 /* 620 * Avoid reserving resources when mode set is pending. Topology 621 * info may not be available to complete reservation. 622 */ 623 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 624 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 625 drm_enc, crtc_state, topology); 626 } 627 } 628 629 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags, 630 adj_mode->private_flags); 631 632 return ret; 633 } 634 635 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 636 struct msm_display_info *disp_info) 637 { 638 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 639 struct msm_drm_private *priv; 640 struct dpu_kms *dpu_kms; 641 struct dpu_hw_mdp *hw_mdptop; 642 struct drm_encoder *drm_enc; 643 int i; 644 645 if (!dpu_enc || !disp_info) { 646 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 647 dpu_enc != NULL, disp_info != NULL); 648 return; 649 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 650 DPU_ERROR("invalid num phys enc %d/%d\n", 651 dpu_enc->num_phys_encs, 652 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 653 return; 654 } 655 656 drm_enc = &dpu_enc->base; 657 /* this pointers are checked in virt_enable_helper */ 658 priv = drm_enc->dev->dev_private; 659 660 dpu_kms = to_dpu_kms(priv->kms); 661 hw_mdptop = dpu_kms->hw_mdp; 662 if (!hw_mdptop) { 663 DPU_ERROR("invalid mdptop\n"); 664 return; 665 } 666 667 if (hw_mdptop->ops.setup_vsync_source && 668 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { 669 for (i = 0; i < dpu_enc->num_phys_encs; i++) 670 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 671 672 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 673 if (disp_info->is_te_using_watchdog_timer) 674 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 675 else 676 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 677 678 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 679 } 680 } 681 682 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 683 { 684 struct dpu_encoder_virt *dpu_enc; 685 int i; 686 687 if (!drm_enc) { 688 DPU_ERROR("invalid encoder\n"); 689 return; 690 } 691 692 dpu_enc = to_dpu_encoder_virt(drm_enc); 693 694 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 695 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 696 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 697 698 if (phys->ops.irq_control) 699 phys->ops.irq_control(phys, enable); 700 } 701 702 } 703 704 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 705 bool enable) 706 { 707 struct msm_drm_private *priv; 708 struct dpu_kms *dpu_kms; 709 struct dpu_encoder_virt *dpu_enc; 710 711 dpu_enc = to_dpu_encoder_virt(drm_enc); 712 priv = drm_enc->dev->dev_private; 713 dpu_kms = to_dpu_kms(priv->kms); 714 715 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 716 717 if (!dpu_enc->cur_master) { 718 DPU_ERROR("encoder master not set\n"); 719 return; 720 } 721 722 if (enable) { 723 /* enable DPU core clks */ 724 pm_runtime_get_sync(&dpu_kms->pdev->dev); 725 726 /* enable all the irq */ 727 _dpu_encoder_irq_control(drm_enc, true); 728 729 } else { 730 /* disable all the irq */ 731 _dpu_encoder_irq_control(drm_enc, false); 732 733 /* disable DPU core clks */ 734 pm_runtime_put_sync(&dpu_kms->pdev->dev); 735 } 736 737 } 738 739 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 740 u32 sw_event) 741 { 742 struct dpu_encoder_virt *dpu_enc; 743 struct msm_drm_private *priv; 744 bool is_vid_mode = false; 745 746 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 747 DPU_ERROR("invalid parameters\n"); 748 return -EINVAL; 749 } 750 dpu_enc = to_dpu_encoder_virt(drm_enc); 751 priv = drm_enc->dev->dev_private; 752 is_vid_mode = dpu_enc->disp_info.capabilities & 753 MSM_DISPLAY_CAP_VID_MODE; 754 755 /* 756 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 757 * events and return early for other events (ie wb display). 758 */ 759 if (!dpu_enc->idle_pc_supported && 760 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 761 sw_event != DPU_ENC_RC_EVENT_STOP && 762 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 763 return 0; 764 765 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 766 dpu_enc->rc_state, "begin"); 767 768 switch (sw_event) { 769 case DPU_ENC_RC_EVENT_KICKOFF: 770 /* cancel delayed off work, if any */ 771 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 772 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 773 sw_event); 774 775 mutex_lock(&dpu_enc->rc_lock); 776 777 /* return if the resource control is already in ON state */ 778 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 779 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", 780 DRMID(drm_enc), sw_event); 781 mutex_unlock(&dpu_enc->rc_lock); 782 return 0; 783 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 784 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 785 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", 786 DRMID(drm_enc), sw_event, 787 dpu_enc->rc_state); 788 mutex_unlock(&dpu_enc->rc_lock); 789 return -EINVAL; 790 } 791 792 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 793 _dpu_encoder_irq_control(drm_enc, true); 794 else 795 _dpu_encoder_resource_control_helper(drm_enc, true); 796 797 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 798 799 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 800 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 801 "kickoff"); 802 803 mutex_unlock(&dpu_enc->rc_lock); 804 break; 805 806 case DPU_ENC_RC_EVENT_FRAME_DONE: 807 /* 808 * mutex lock is not used as this event happens at interrupt 809 * context. And locking is not required as, the other events 810 * like KICKOFF and STOP does a wait-for-idle before executing 811 * the resource_control 812 */ 813 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 814 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 815 DRMID(drm_enc), sw_event, 816 dpu_enc->rc_state); 817 return -EINVAL; 818 } 819 820 /* 821 * schedule off work item only when there are no 822 * frames pending 823 */ 824 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 825 DRM_DEBUG_KMS("id:%d skip schedule work\n", 826 DRMID(drm_enc)); 827 return 0; 828 } 829 830 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 831 msecs_to_jiffies(dpu_enc->idle_timeout)); 832 833 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 834 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 835 "frame done"); 836 break; 837 838 case DPU_ENC_RC_EVENT_PRE_STOP: 839 /* cancel delayed off work, if any */ 840 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 841 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 842 sw_event); 843 844 mutex_lock(&dpu_enc->rc_lock); 845 846 if (is_vid_mode && 847 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 848 _dpu_encoder_irq_control(drm_enc, true); 849 } 850 /* skip if is already OFF or IDLE, resources are off already */ 851 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 852 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 853 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 854 DRMID(drm_enc), sw_event, 855 dpu_enc->rc_state); 856 mutex_unlock(&dpu_enc->rc_lock); 857 return 0; 858 } 859 860 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 861 862 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 863 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 864 "pre stop"); 865 866 mutex_unlock(&dpu_enc->rc_lock); 867 break; 868 869 case DPU_ENC_RC_EVENT_STOP: 870 mutex_lock(&dpu_enc->rc_lock); 871 872 /* return if the resource control is already in OFF state */ 873 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 874 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 875 DRMID(drm_enc), sw_event); 876 mutex_unlock(&dpu_enc->rc_lock); 877 return 0; 878 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 879 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 880 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 881 mutex_unlock(&dpu_enc->rc_lock); 882 return -EINVAL; 883 } 884 885 /** 886 * expect to arrive here only if in either idle state or pre-off 887 * and in IDLE state the resources are already disabled 888 */ 889 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 890 _dpu_encoder_resource_control_helper(drm_enc, false); 891 892 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 893 894 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 895 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 896 "stop"); 897 898 mutex_unlock(&dpu_enc->rc_lock); 899 break; 900 901 case DPU_ENC_RC_EVENT_ENTER_IDLE: 902 mutex_lock(&dpu_enc->rc_lock); 903 904 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 905 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 906 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 907 mutex_unlock(&dpu_enc->rc_lock); 908 return 0; 909 } 910 911 /* 912 * if we are in ON but a frame was just kicked off, 913 * ignore the IDLE event, it's probably a stale timer event 914 */ 915 if (dpu_enc->frame_busy_mask[0]) { 916 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 917 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 918 mutex_unlock(&dpu_enc->rc_lock); 919 return 0; 920 } 921 922 if (is_vid_mode) 923 _dpu_encoder_irq_control(drm_enc, false); 924 else 925 _dpu_encoder_resource_control_helper(drm_enc, false); 926 927 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 928 929 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 930 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 931 "idle"); 932 933 mutex_unlock(&dpu_enc->rc_lock); 934 break; 935 936 default: 937 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 938 sw_event); 939 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 940 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 941 "error"); 942 break; 943 } 944 945 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 946 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 947 "end"); 948 return 0; 949 } 950 951 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 952 struct drm_display_mode *mode, 953 struct drm_display_mode *adj_mode) 954 { 955 struct dpu_encoder_virt *dpu_enc; 956 struct msm_drm_private *priv; 957 struct dpu_kms *dpu_kms; 958 struct list_head *connector_list; 959 struct drm_connector *conn = NULL, *conn_iter; 960 struct drm_crtc *drm_crtc; 961 struct dpu_crtc_state *cstate; 962 struct dpu_global_state *global_state; 963 struct msm_display_topology topology; 964 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 965 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 966 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 967 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; 968 int num_lm, num_ctl, num_pp, num_dspp; 969 int i, j; 970 971 if (!drm_enc) { 972 DPU_ERROR("invalid encoder\n"); 973 return; 974 } 975 976 dpu_enc = to_dpu_encoder_virt(drm_enc); 977 DPU_DEBUG_ENC(dpu_enc, "\n"); 978 979 priv = drm_enc->dev->dev_private; 980 dpu_kms = to_dpu_kms(priv->kms); 981 connector_list = &dpu_kms->dev->mode_config.connector_list; 982 983 global_state = dpu_kms_get_existing_global_state(dpu_kms); 984 if (IS_ERR_OR_NULL(global_state)) { 985 DPU_ERROR("Failed to get global state"); 986 return; 987 } 988 989 trace_dpu_enc_mode_set(DRMID(drm_enc)); 990 991 list_for_each_entry(conn_iter, connector_list, head) 992 if (conn_iter->encoder == drm_enc) 993 conn = conn_iter; 994 995 if (!conn) { 996 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); 997 return; 998 } else if (!conn->state) { 999 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); 1000 return; 1001 } 1002 1003 drm_for_each_crtc(drm_crtc, drm_enc->dev) 1004 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc)) 1005 break; 1006 1007 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 1008 1009 /* Query resource that have been reserved in atomic check step. */ 1010 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1011 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1012 ARRAY_SIZE(hw_pp)); 1013 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1014 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1015 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1016 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1017 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1018 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 1019 ARRAY_SIZE(hw_dspp)); 1020 1021 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1022 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1023 : NULL; 1024 1025 cstate = to_dpu_crtc_state(drm_crtc->state); 1026 1027 for (i = 0; i < num_lm; i++) { 1028 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1029 1030 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1031 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1032 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 1033 } 1034 1035 cstate->num_mixers = num_lm; 1036 1037 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1038 int num_blk; 1039 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC]; 1040 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1041 1042 if (!dpu_enc->hw_pp[i]) { 1043 DPU_ERROR_ENC(dpu_enc, 1044 "no pp block assigned at idx: %d\n", i); 1045 return; 1046 } 1047 1048 if (!hw_ctl[i]) { 1049 DPU_ERROR_ENC(dpu_enc, 1050 "no ctl block assigned at idx: %d\n", i); 1051 return; 1052 } 1053 1054 phys->hw_pp = dpu_enc->hw_pp[i]; 1055 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1056 1057 num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm, 1058 global_state, drm_enc->base.id, DPU_HW_BLK_INTF, 1059 hw_blk, ARRAY_SIZE(hw_blk)); 1060 for (j = 0; j < num_blk; j++) { 1061 struct dpu_hw_intf *hw_intf; 1062 1063 hw_intf = to_dpu_hw_intf(hw_blk[i]); 1064 if (hw_intf->idx == phys->intf_idx) 1065 phys->hw_intf = hw_intf; 1066 } 1067 1068 if (!phys->hw_intf) { 1069 DPU_ERROR_ENC(dpu_enc, 1070 "no intf block assigned at idx: %d\n", i); 1071 return; 1072 } 1073 1074 phys->connector = conn->state->connector; 1075 if (phys->ops.mode_set) 1076 phys->ops.mode_set(phys, mode, adj_mode); 1077 } 1078 } 1079 1080 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1081 { 1082 struct dpu_encoder_virt *dpu_enc = NULL; 1083 struct msm_drm_private *priv; 1084 struct dpu_kms *dpu_kms; 1085 1086 if (!drm_enc || !drm_enc->dev) { 1087 DPU_ERROR("invalid parameters\n"); 1088 return; 1089 } 1090 1091 priv = drm_enc->dev->dev_private; 1092 dpu_kms = to_dpu_kms(priv->kms); 1093 1094 dpu_enc = to_dpu_encoder_virt(drm_enc); 1095 if (!dpu_enc || !dpu_enc->cur_master) { 1096 DPU_ERROR("invalid dpu encoder/master\n"); 1097 return; 1098 } 1099 1100 if (dpu_enc->cur_master->hw_mdptop && 1101 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) 1102 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( 1103 dpu_enc->cur_master->hw_mdptop, 1104 dpu_kms->catalog); 1105 1106 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1107 } 1108 1109 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1110 { 1111 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1112 1113 mutex_lock(&dpu_enc->enc_lock); 1114 1115 if (!dpu_enc->enabled) 1116 goto out; 1117 1118 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1119 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1120 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1121 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1122 1123 _dpu_encoder_virt_enable_helper(drm_enc); 1124 1125 out: 1126 mutex_unlock(&dpu_enc->enc_lock); 1127 } 1128 1129 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) 1130 { 1131 struct dpu_encoder_virt *dpu_enc = NULL; 1132 int ret = 0; 1133 struct drm_display_mode *cur_mode = NULL; 1134 1135 if (!drm_enc) { 1136 DPU_ERROR("invalid encoder\n"); 1137 return; 1138 } 1139 dpu_enc = to_dpu_encoder_virt(drm_enc); 1140 1141 mutex_lock(&dpu_enc->enc_lock); 1142 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1143 1144 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1145 cur_mode->vdisplay); 1146 1147 /* always enable slave encoder before master */ 1148 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1149 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1150 1151 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1152 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1153 1154 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1155 if (ret) { 1156 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1157 ret); 1158 goto out; 1159 } 1160 1161 _dpu_encoder_virt_enable_helper(drm_enc); 1162 1163 dpu_enc->enabled = true; 1164 1165 out: 1166 mutex_unlock(&dpu_enc->enc_lock); 1167 } 1168 1169 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) 1170 { 1171 struct dpu_encoder_virt *dpu_enc = NULL; 1172 struct msm_drm_private *priv; 1173 struct dpu_kms *dpu_kms; 1174 struct dpu_global_state *global_state; 1175 int i = 0; 1176 1177 if (!drm_enc) { 1178 DPU_ERROR("invalid encoder\n"); 1179 return; 1180 } else if (!drm_enc->dev) { 1181 DPU_ERROR("invalid dev\n"); 1182 return; 1183 } 1184 1185 dpu_enc = to_dpu_encoder_virt(drm_enc); 1186 DPU_DEBUG_ENC(dpu_enc, "\n"); 1187 1188 mutex_lock(&dpu_enc->enc_lock); 1189 dpu_enc->enabled = false; 1190 1191 priv = drm_enc->dev->dev_private; 1192 dpu_kms = to_dpu_kms(priv->kms); 1193 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1194 1195 trace_dpu_enc_disable(DRMID(drm_enc)); 1196 1197 /* wait for idle */ 1198 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1199 1200 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1201 1202 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1203 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1204 1205 if (phys->ops.disable) 1206 phys->ops.disable(phys); 1207 } 1208 1209 /* after phys waits for frame-done, should be no more frames pending */ 1210 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1211 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1212 del_timer_sync(&dpu_enc->frame_done_timer); 1213 } 1214 1215 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1216 1217 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1218 dpu_enc->phys_encs[i]->connector = NULL; 1219 } 1220 1221 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1222 1223 dpu_rm_release(global_state, drm_enc); 1224 1225 mutex_unlock(&dpu_enc->enc_lock); 1226 } 1227 1228 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, 1229 enum dpu_intf_type type, u32 controller_id) 1230 { 1231 int i = 0; 1232 1233 for (i = 0; i < catalog->intf_count; i++) { 1234 if (catalog->intf[i].type == type 1235 && catalog->intf[i].controller_id == controller_id) { 1236 return catalog->intf[i].id; 1237 } 1238 } 1239 1240 return INTF_MAX; 1241 } 1242 1243 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1244 struct dpu_encoder_phys *phy_enc) 1245 { 1246 struct dpu_encoder_virt *dpu_enc = NULL; 1247 unsigned long lock_flags; 1248 1249 if (!drm_enc || !phy_enc) 1250 return; 1251 1252 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1253 dpu_enc = to_dpu_encoder_virt(drm_enc); 1254 1255 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1256 if (dpu_enc->crtc) 1257 dpu_crtc_vblank_callback(dpu_enc->crtc); 1258 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1259 1260 atomic_inc(&phy_enc->vsync_cnt); 1261 DPU_ATRACE_END("encoder_vblank_callback"); 1262 } 1263 1264 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1265 struct dpu_encoder_phys *phy_enc) 1266 { 1267 if (!phy_enc) 1268 return; 1269 1270 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1271 atomic_inc(&phy_enc->underrun_cnt); 1272 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1273 atomic_read(&phy_enc->underrun_cnt)); 1274 DPU_ATRACE_END("encoder_underrun_callback"); 1275 } 1276 1277 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1278 { 1279 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1280 unsigned long lock_flags; 1281 1282 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1283 /* crtc should always be cleared before re-assigning */ 1284 WARN_ON(crtc && dpu_enc->crtc); 1285 dpu_enc->crtc = crtc; 1286 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1287 } 1288 1289 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1290 struct drm_crtc *crtc, bool enable) 1291 { 1292 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1293 unsigned long lock_flags; 1294 int i; 1295 1296 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1297 1298 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1299 if (dpu_enc->crtc != crtc) { 1300 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1301 return; 1302 } 1303 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1304 1305 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1306 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1307 1308 if (phys->ops.control_vblank_irq) 1309 phys->ops.control_vblank_irq(phys, enable); 1310 } 1311 } 1312 1313 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1314 void (*frame_event_cb)(void *, u32 event), 1315 void *frame_event_cb_data) 1316 { 1317 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1318 unsigned long lock_flags; 1319 bool enable; 1320 1321 enable = frame_event_cb ? true : false; 1322 1323 if (!drm_enc) { 1324 DPU_ERROR("invalid encoder\n"); 1325 return; 1326 } 1327 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1328 1329 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1330 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1331 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1332 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1333 } 1334 1335 static void dpu_encoder_frame_done_callback( 1336 struct drm_encoder *drm_enc, 1337 struct dpu_encoder_phys *ready_phys, u32 event) 1338 { 1339 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1340 unsigned int i; 1341 1342 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1343 | DPU_ENCODER_FRAME_EVENT_ERROR 1344 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1345 1346 if (!dpu_enc->frame_busy_mask[0]) { 1347 /** 1348 * suppress frame_done without waiter, 1349 * likely autorefresh 1350 */ 1351 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 1352 event, ready_phys->intf_idx); 1353 return; 1354 } 1355 1356 /* One of the physical encoders has become idle */ 1357 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1358 if (dpu_enc->phys_encs[i] == ready_phys) { 1359 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1360 dpu_enc->frame_busy_mask[0]); 1361 clear_bit(i, dpu_enc->frame_busy_mask); 1362 } 1363 } 1364 1365 if (!dpu_enc->frame_busy_mask[0]) { 1366 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1367 del_timer(&dpu_enc->frame_done_timer); 1368 1369 dpu_encoder_resource_control(drm_enc, 1370 DPU_ENC_RC_EVENT_FRAME_DONE); 1371 1372 if (dpu_enc->crtc_frame_event_cb) 1373 dpu_enc->crtc_frame_event_cb( 1374 dpu_enc->crtc_frame_event_cb_data, 1375 event); 1376 } 1377 } else { 1378 if (dpu_enc->crtc_frame_event_cb) 1379 dpu_enc->crtc_frame_event_cb( 1380 dpu_enc->crtc_frame_event_cb_data, event); 1381 } 1382 } 1383 1384 static void dpu_encoder_off_work(struct work_struct *work) 1385 { 1386 struct dpu_encoder_virt *dpu_enc = container_of(work, 1387 struct dpu_encoder_virt, delayed_off_work.work); 1388 1389 if (!dpu_enc) { 1390 DPU_ERROR("invalid dpu encoder\n"); 1391 return; 1392 } 1393 1394 dpu_encoder_resource_control(&dpu_enc->base, 1395 DPU_ENC_RC_EVENT_ENTER_IDLE); 1396 1397 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1398 DPU_ENCODER_FRAME_EVENT_IDLE); 1399 } 1400 1401 /** 1402 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1403 * drm_enc: Pointer to drm encoder structure 1404 * phys: Pointer to physical encoder structure 1405 * extra_flush_bits: Additional bit mask to include in flush trigger 1406 */ 1407 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1408 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1409 { 1410 struct dpu_hw_ctl *ctl; 1411 int pending_kickoff_cnt; 1412 u32 ret = UINT_MAX; 1413 1414 if (!phys->hw_pp) { 1415 DPU_ERROR("invalid pingpong hw\n"); 1416 return; 1417 } 1418 1419 ctl = phys->hw_ctl; 1420 if (!ctl->ops.trigger_flush) { 1421 DPU_ERROR("missing trigger cb\n"); 1422 return; 1423 } 1424 1425 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1426 1427 if (extra_flush_bits && ctl->ops.update_pending_flush) 1428 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1429 1430 ctl->ops.trigger_flush(ctl); 1431 1432 if (ctl->ops.get_pending_flush) 1433 ret = ctl->ops.get_pending_flush(ctl); 1434 1435 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, 1436 pending_kickoff_cnt, ctl->idx, 1437 extra_flush_bits, ret); 1438 } 1439 1440 /** 1441 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1442 * phys: Pointer to physical encoder structure 1443 */ 1444 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1445 { 1446 if (!phys) { 1447 DPU_ERROR("invalid argument(s)\n"); 1448 return; 1449 } 1450 1451 if (!phys->hw_pp) { 1452 DPU_ERROR("invalid pingpong hw\n"); 1453 return; 1454 } 1455 1456 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1457 phys->ops.trigger_start(phys); 1458 } 1459 1460 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1461 { 1462 struct dpu_hw_ctl *ctl; 1463 1464 ctl = phys_enc->hw_ctl; 1465 if (ctl->ops.trigger_start) { 1466 ctl->ops.trigger_start(ctl); 1467 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1468 } 1469 } 1470 1471 static int dpu_encoder_helper_wait_event_timeout( 1472 int32_t drm_id, 1473 int32_t hw_id, 1474 struct dpu_encoder_wait_info *info) 1475 { 1476 int rc = 0; 1477 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1478 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1479 s64 time; 1480 1481 do { 1482 rc = wait_event_timeout(*(info->wq), 1483 atomic_read(info->atomic_cnt) == 0, jiffies); 1484 time = ktime_to_ms(ktime_get()); 1485 1486 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, 1487 expected_time, 1488 atomic_read(info->atomic_cnt)); 1489 /* If we timed out, counter is valid and time is less, wait again */ 1490 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1491 (time < expected_time)); 1492 1493 return rc; 1494 } 1495 1496 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1497 { 1498 struct dpu_encoder_virt *dpu_enc; 1499 struct dpu_hw_ctl *ctl; 1500 int rc; 1501 1502 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1503 ctl = phys_enc->hw_ctl; 1504 1505 if (!ctl->ops.reset) 1506 return; 1507 1508 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), 1509 ctl->idx); 1510 1511 rc = ctl->ops.reset(ctl); 1512 if (rc) 1513 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1514 1515 phys_enc->enable_state = DPU_ENC_ENABLED; 1516 } 1517 1518 /** 1519 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1520 * Iterate through the physical encoders and perform consolidated flush 1521 * and/or control start triggering as needed. This is done in the virtual 1522 * encoder rather than the individual physical ones in order to handle 1523 * use cases that require visibility into multiple physical encoders at 1524 * a time. 1525 * dpu_enc: Pointer to virtual encoder structure 1526 */ 1527 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1528 { 1529 struct dpu_hw_ctl *ctl; 1530 uint32_t i, pending_flush; 1531 unsigned long lock_flags; 1532 1533 pending_flush = 0x0; 1534 1535 /* update pending counts and trigger kickoff ctl flush atomically */ 1536 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1537 1538 /* don't perform flush/start operations for slave encoders */ 1539 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1540 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1541 1542 if (phys->enable_state == DPU_ENC_DISABLED) 1543 continue; 1544 1545 ctl = phys->hw_ctl; 1546 1547 /* 1548 * This is cleared in frame_done worker, which isn't invoked 1549 * for async commits. So don't set this for async, since it'll 1550 * roll over to the next commit. 1551 */ 1552 if (phys->split_role != ENC_ROLE_SLAVE) 1553 set_bit(i, dpu_enc->frame_busy_mask); 1554 1555 if (!phys->ops.needs_single_flush || 1556 !phys->ops.needs_single_flush(phys)) 1557 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1558 else if (ctl->ops.get_pending_flush) 1559 pending_flush |= ctl->ops.get_pending_flush(ctl); 1560 } 1561 1562 /* for split flush, combine pending flush masks and send to master */ 1563 if (pending_flush && dpu_enc->cur_master) { 1564 _dpu_encoder_trigger_flush( 1565 &dpu_enc->base, 1566 dpu_enc->cur_master, 1567 pending_flush); 1568 } 1569 1570 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1571 1572 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1573 } 1574 1575 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1576 { 1577 struct dpu_encoder_virt *dpu_enc; 1578 struct dpu_encoder_phys *phys; 1579 unsigned int i; 1580 struct dpu_hw_ctl *ctl; 1581 struct msm_display_info *disp_info; 1582 1583 if (!drm_enc) { 1584 DPU_ERROR("invalid encoder\n"); 1585 return; 1586 } 1587 dpu_enc = to_dpu_encoder_virt(drm_enc); 1588 disp_info = &dpu_enc->disp_info; 1589 1590 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1591 phys = dpu_enc->phys_encs[i]; 1592 1593 ctl = phys->hw_ctl; 1594 if (ctl->ops.clear_pending_flush) 1595 ctl->ops.clear_pending_flush(ctl); 1596 1597 /* update only for command mode primary ctl */ 1598 if ((phys == dpu_enc->cur_master) && 1599 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) 1600 && ctl->ops.trigger_pending) 1601 ctl->ops.trigger_pending(ctl); 1602 } 1603 } 1604 1605 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1606 struct drm_display_mode *mode) 1607 { 1608 u64 pclk_rate; 1609 u32 pclk_period; 1610 u32 line_time; 1611 1612 /* 1613 * For linetime calculation, only operate on master encoder. 1614 */ 1615 if (!dpu_enc->cur_master) 1616 return 0; 1617 1618 if (!dpu_enc->cur_master->ops.get_line_count) { 1619 DPU_ERROR("get_line_count function not defined\n"); 1620 return 0; 1621 } 1622 1623 pclk_rate = mode->clock; /* pixel clock in kHz */ 1624 if (pclk_rate == 0) { 1625 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1626 return 0; 1627 } 1628 1629 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1630 if (pclk_period == 0) { 1631 DPU_ERROR("pclk period is 0\n"); 1632 return 0; 1633 } 1634 1635 /* 1636 * Line time calculation based on Pixel clock and HTOTAL. 1637 * Final unit is in ns. 1638 */ 1639 line_time = (pclk_period * mode->htotal) / 1000; 1640 if (line_time == 0) { 1641 DPU_ERROR("line time calculation is 0\n"); 1642 return 0; 1643 } 1644 1645 DPU_DEBUG_ENC(dpu_enc, 1646 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1647 pclk_rate, pclk_period, line_time); 1648 1649 return line_time; 1650 } 1651 1652 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1653 { 1654 struct drm_display_mode *mode; 1655 struct dpu_encoder_virt *dpu_enc; 1656 u32 cur_line; 1657 u32 line_time; 1658 u32 vtotal, time_to_vsync; 1659 ktime_t cur_time; 1660 1661 dpu_enc = to_dpu_encoder_virt(drm_enc); 1662 1663 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1664 DPU_ERROR("crtc/crtc state object is NULL\n"); 1665 return -EINVAL; 1666 } 1667 mode = &drm_enc->crtc->state->adjusted_mode; 1668 1669 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1670 if (!line_time) 1671 return -EINVAL; 1672 1673 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1674 1675 vtotal = mode->vtotal; 1676 if (cur_line >= vtotal) 1677 time_to_vsync = line_time * vtotal; 1678 else 1679 time_to_vsync = line_time * (vtotal - cur_line); 1680 1681 if (time_to_vsync == 0) { 1682 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1683 vtotal); 1684 return -EINVAL; 1685 } 1686 1687 cur_time = ktime_get(); 1688 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1689 1690 DPU_DEBUG_ENC(dpu_enc, 1691 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1692 cur_line, vtotal, time_to_vsync, 1693 ktime_to_ms(cur_time), 1694 ktime_to_ms(*wakeup_time)); 1695 return 0; 1696 } 1697 1698 static void dpu_encoder_vsync_event_handler(struct timer_list *t) 1699 { 1700 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 1701 vsync_event_timer); 1702 struct drm_encoder *drm_enc = &dpu_enc->base; 1703 struct msm_drm_private *priv; 1704 struct msm_drm_thread *event_thread; 1705 1706 if (!drm_enc->dev || !drm_enc->crtc) { 1707 DPU_ERROR("invalid parameters\n"); 1708 return; 1709 } 1710 1711 priv = drm_enc->dev->dev_private; 1712 1713 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { 1714 DPU_ERROR("invalid crtc index\n"); 1715 return; 1716 } 1717 event_thread = &priv->event_thread[drm_enc->crtc->index]; 1718 if (!event_thread) { 1719 DPU_ERROR("event_thread not found for crtc:%d\n", 1720 drm_enc->crtc->index); 1721 return; 1722 } 1723 1724 del_timer(&dpu_enc->vsync_event_timer); 1725 } 1726 1727 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) 1728 { 1729 struct dpu_encoder_virt *dpu_enc = container_of(work, 1730 struct dpu_encoder_virt, vsync_event_work); 1731 ktime_t wakeup_time; 1732 1733 if (!dpu_enc) { 1734 DPU_ERROR("invalid dpu encoder\n"); 1735 return; 1736 } 1737 1738 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) 1739 return; 1740 1741 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); 1742 mod_timer(&dpu_enc->vsync_event_timer, 1743 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1744 } 1745 1746 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1747 { 1748 struct dpu_encoder_virt *dpu_enc; 1749 struct dpu_encoder_phys *phys; 1750 bool needs_hw_reset = false; 1751 unsigned int i; 1752 1753 dpu_enc = to_dpu_encoder_virt(drm_enc); 1754 1755 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1756 1757 /* prepare for next kickoff, may include waiting on previous kickoff */ 1758 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1759 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1760 phys = dpu_enc->phys_encs[i]; 1761 if (phys->ops.prepare_for_kickoff) 1762 phys->ops.prepare_for_kickoff(phys); 1763 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1764 needs_hw_reset = true; 1765 } 1766 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1767 1768 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1769 1770 /* if any phys needs reset, reset all phys, in-order */ 1771 if (needs_hw_reset) { 1772 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1773 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1774 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1775 } 1776 } 1777 } 1778 1779 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1780 { 1781 struct dpu_encoder_virt *dpu_enc; 1782 struct dpu_encoder_phys *phys; 1783 ktime_t wakeup_time; 1784 unsigned long timeout_ms; 1785 unsigned int i; 1786 1787 DPU_ATRACE_BEGIN("encoder_kickoff"); 1788 dpu_enc = to_dpu_encoder_virt(drm_enc); 1789 1790 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1791 1792 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1793 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1794 1795 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1796 mod_timer(&dpu_enc->frame_done_timer, 1797 jiffies + msecs_to_jiffies(timeout_ms)); 1798 1799 /* All phys encs are ready to go, trigger the kickoff */ 1800 _dpu_encoder_kickoff_phys(dpu_enc); 1801 1802 /* allow phys encs to handle any post-kickoff business */ 1803 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1804 phys = dpu_enc->phys_encs[i]; 1805 if (phys->ops.handle_post_kickoff) 1806 phys->ops.handle_post_kickoff(phys); 1807 } 1808 1809 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1810 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) { 1811 trace_dpu_enc_early_kickoff(DRMID(drm_enc), 1812 ktime_to_ms(wakeup_time)); 1813 mod_timer(&dpu_enc->vsync_event_timer, 1814 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1815 } 1816 1817 DPU_ATRACE_END("encoder_kickoff"); 1818 } 1819 1820 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) 1821 { 1822 struct dpu_encoder_virt *dpu_enc; 1823 struct dpu_encoder_phys *phys; 1824 int i; 1825 1826 if (!drm_enc) { 1827 DPU_ERROR("invalid encoder\n"); 1828 return; 1829 } 1830 dpu_enc = to_dpu_encoder_virt(drm_enc); 1831 1832 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1833 phys = dpu_enc->phys_encs[i]; 1834 if (phys->ops.prepare_commit) 1835 phys->ops.prepare_commit(phys); 1836 } 1837 } 1838 1839 #ifdef CONFIG_DEBUG_FS 1840 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 1841 { 1842 struct dpu_encoder_virt *dpu_enc = s->private; 1843 int i; 1844 1845 mutex_lock(&dpu_enc->enc_lock); 1846 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1847 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1848 1849 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", 1850 phys->intf_idx - INTF_0, 1851 atomic_read(&phys->vsync_cnt), 1852 atomic_read(&phys->underrun_cnt)); 1853 1854 switch (phys->intf_mode) { 1855 case INTF_MODE_VIDEO: 1856 seq_puts(s, "mode: video\n"); 1857 break; 1858 case INTF_MODE_CMD: 1859 seq_puts(s, "mode: command\n"); 1860 break; 1861 default: 1862 seq_puts(s, "mode: ???\n"); 1863 break; 1864 } 1865 } 1866 mutex_unlock(&dpu_enc->enc_lock); 1867 1868 return 0; 1869 } 1870 1871 static int _dpu_encoder_debugfs_status_open(struct inode *inode, 1872 struct file *file) 1873 { 1874 return single_open(file, _dpu_encoder_status_show, inode->i_private); 1875 } 1876 1877 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1878 { 1879 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1880 int i; 1881 1882 static const struct file_operations debugfs_status_fops = { 1883 .open = _dpu_encoder_debugfs_status_open, 1884 .read = seq_read, 1885 .llseek = seq_lseek, 1886 .release = single_release, 1887 }; 1888 1889 char name[DPU_NAME_SIZE]; 1890 1891 if (!drm_enc->dev) { 1892 DPU_ERROR("invalid encoder or kms\n"); 1893 return -EINVAL; 1894 } 1895 1896 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); 1897 1898 /* create overall sub-directory for the encoder */ 1899 dpu_enc->debugfs_root = debugfs_create_dir(name, 1900 drm_enc->dev->primary->debugfs_root); 1901 1902 /* don't error check these */ 1903 debugfs_create_file("status", 0600, 1904 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); 1905 1906 for (i = 0; i < dpu_enc->num_phys_encs; i++) 1907 if (dpu_enc->phys_encs[i]->ops.late_register) 1908 dpu_enc->phys_encs[i]->ops.late_register( 1909 dpu_enc->phys_encs[i], 1910 dpu_enc->debugfs_root); 1911 1912 return 0; 1913 } 1914 #else 1915 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1916 { 1917 return 0; 1918 } 1919 #endif 1920 1921 static int dpu_encoder_late_register(struct drm_encoder *encoder) 1922 { 1923 return _dpu_encoder_init_debugfs(encoder); 1924 } 1925 1926 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 1927 { 1928 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 1929 1930 debugfs_remove_recursive(dpu_enc->debugfs_root); 1931 } 1932 1933 static int dpu_encoder_virt_add_phys_encs( 1934 u32 display_caps, 1935 struct dpu_encoder_virt *dpu_enc, 1936 struct dpu_enc_phys_init_params *params) 1937 { 1938 struct dpu_encoder_phys *enc = NULL; 1939 1940 DPU_DEBUG_ENC(dpu_enc, "\n"); 1941 1942 /* 1943 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 1944 * in this function, check up-front. 1945 */ 1946 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 1947 ARRAY_SIZE(dpu_enc->phys_encs)) { 1948 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 1949 dpu_enc->num_phys_encs); 1950 return -EINVAL; 1951 } 1952 1953 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { 1954 enc = dpu_encoder_phys_vid_init(params); 1955 1956 if (IS_ERR_OR_NULL(enc)) { 1957 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 1958 PTR_ERR(enc)); 1959 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1960 } 1961 1962 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1963 ++dpu_enc->num_phys_encs; 1964 } 1965 1966 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { 1967 enc = dpu_encoder_phys_cmd_init(params); 1968 1969 if (IS_ERR_OR_NULL(enc)) { 1970 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 1971 PTR_ERR(enc)); 1972 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1973 } 1974 1975 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1976 ++dpu_enc->num_phys_encs; 1977 } 1978 1979 if (params->split_role == ENC_ROLE_SLAVE) 1980 dpu_enc->cur_slave = enc; 1981 else 1982 dpu_enc->cur_master = enc; 1983 1984 return 0; 1985 } 1986 1987 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = { 1988 .handle_vblank_virt = dpu_encoder_vblank_callback, 1989 .handle_underrun_virt = dpu_encoder_underrun_callback, 1990 .handle_frame_done = dpu_encoder_frame_done_callback, 1991 }; 1992 1993 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 1994 struct dpu_kms *dpu_kms, 1995 struct msm_display_info *disp_info) 1996 { 1997 int ret = 0; 1998 int i = 0; 1999 enum dpu_intf_type intf_type; 2000 struct dpu_enc_phys_init_params phys_params; 2001 2002 if (!dpu_enc) { 2003 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2004 return -EINVAL; 2005 } 2006 2007 dpu_enc->cur_master = NULL; 2008 2009 memset(&phys_params, 0, sizeof(phys_params)); 2010 phys_params.dpu_kms = dpu_kms; 2011 phys_params.parent = &dpu_enc->base; 2012 phys_params.parent_ops = &dpu_encoder_parent_ops; 2013 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2014 2015 DPU_DEBUG("\n"); 2016 2017 switch (disp_info->intf_type) { 2018 case DRM_MODE_ENCODER_DSI: 2019 intf_type = INTF_DSI; 2020 break; 2021 default: 2022 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n"); 2023 return -EINVAL; 2024 } 2025 2026 WARN_ON(disp_info->num_of_h_tiles < 1); 2027 2028 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2029 2030 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || 2031 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) 2032 dpu_enc->idle_pc_supported = 2033 dpu_kms->catalog->caps->has_idle_pc; 2034 2035 mutex_lock(&dpu_enc->enc_lock); 2036 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2037 /* 2038 * Left-most tile is at index 0, content is controller id 2039 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2040 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2041 */ 2042 u32 controller_id = disp_info->h_tile_instance[i]; 2043 2044 if (disp_info->num_of_h_tiles > 1) { 2045 if (i == 0) 2046 phys_params.split_role = ENC_ROLE_MASTER; 2047 else 2048 phys_params.split_role = ENC_ROLE_SLAVE; 2049 } else { 2050 phys_params.split_role = ENC_ROLE_SOLO; 2051 } 2052 2053 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2054 i, controller_id, phys_params.split_role); 2055 2056 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, 2057 intf_type, 2058 controller_id); 2059 if (phys_params.intf_idx == INTF_MAX) { 2060 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", 2061 intf_type, controller_id); 2062 ret = -EINVAL; 2063 } 2064 2065 if (!ret) { 2066 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities, 2067 dpu_enc, 2068 &phys_params); 2069 if (ret) 2070 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2071 } 2072 } 2073 2074 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2075 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2076 atomic_set(&phys->vsync_cnt, 0); 2077 atomic_set(&phys->underrun_cnt, 0); 2078 } 2079 mutex_unlock(&dpu_enc->enc_lock); 2080 2081 return ret; 2082 } 2083 2084 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2085 { 2086 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2087 frame_done_timer); 2088 struct drm_encoder *drm_enc = &dpu_enc->base; 2089 u32 event; 2090 2091 if (!drm_enc->dev) { 2092 DPU_ERROR("invalid parameters\n"); 2093 return; 2094 } 2095 2096 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2097 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2098 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2099 return; 2100 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2101 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2102 return; 2103 } 2104 2105 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2106 2107 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2108 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2109 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2110 } 2111 2112 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2113 .mode_set = dpu_encoder_virt_mode_set, 2114 .disable = dpu_encoder_virt_disable, 2115 .enable = dpu_kms_encoder_enable, 2116 .atomic_check = dpu_encoder_virt_atomic_check, 2117 2118 /* This is called by dpu_kms_encoder_enable */ 2119 .commit = dpu_encoder_virt_enable, 2120 }; 2121 2122 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2123 .destroy = dpu_encoder_destroy, 2124 .late_register = dpu_encoder_late_register, 2125 .early_unregister = dpu_encoder_early_unregister, 2126 }; 2127 2128 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 2129 struct msm_display_info *disp_info) 2130 { 2131 struct msm_drm_private *priv = dev->dev_private; 2132 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2133 struct drm_encoder *drm_enc = NULL; 2134 struct dpu_encoder_virt *dpu_enc = NULL; 2135 int ret = 0; 2136 2137 dpu_enc = to_dpu_encoder_virt(enc); 2138 2139 mutex_init(&dpu_enc->enc_lock); 2140 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2141 if (ret) 2142 goto fail; 2143 2144 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2145 timer_setup(&dpu_enc->frame_done_timer, 2146 dpu_encoder_frame_done_timeout, 0); 2147 2148 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) 2149 timer_setup(&dpu_enc->vsync_event_timer, 2150 dpu_encoder_vsync_event_handler, 2151 0); 2152 2153 2154 mutex_init(&dpu_enc->rc_lock); 2155 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2156 dpu_encoder_off_work); 2157 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2158 2159 kthread_init_work(&dpu_enc->vsync_event_work, 2160 dpu_encoder_vsync_event_work_handler); 2161 2162 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2163 2164 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2165 2166 return ret; 2167 2168 fail: 2169 DPU_ERROR("failed to create encoder\n"); 2170 if (drm_enc) 2171 dpu_encoder_destroy(drm_enc); 2172 2173 return ret; 2174 2175 2176 } 2177 2178 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2179 int drm_enc_mode) 2180 { 2181 struct dpu_encoder_virt *dpu_enc = NULL; 2182 int rc = 0; 2183 2184 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2185 if (!dpu_enc) 2186 return ERR_PTR(ENOMEM); 2187 2188 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2189 drm_enc_mode, NULL); 2190 if (rc) { 2191 devm_kfree(dev->dev, dpu_enc); 2192 return ERR_PTR(rc); 2193 } 2194 2195 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2196 2197 spin_lock_init(&dpu_enc->enc_spinlock); 2198 dpu_enc->enabled = false; 2199 2200 return &dpu_enc->base; 2201 } 2202 2203 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2204 enum msm_event_wait event) 2205 { 2206 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2207 struct dpu_encoder_virt *dpu_enc = NULL; 2208 int i, ret = 0; 2209 2210 if (!drm_enc) { 2211 DPU_ERROR("invalid encoder\n"); 2212 return -EINVAL; 2213 } 2214 dpu_enc = to_dpu_encoder_virt(drm_enc); 2215 DPU_DEBUG_ENC(dpu_enc, "\n"); 2216 2217 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2218 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2219 2220 switch (event) { 2221 case MSM_ENC_COMMIT_DONE: 2222 fn_wait = phys->ops.wait_for_commit_done; 2223 break; 2224 case MSM_ENC_TX_COMPLETE: 2225 fn_wait = phys->ops.wait_for_tx_complete; 2226 break; 2227 case MSM_ENC_VBLANK: 2228 fn_wait = phys->ops.wait_for_vblank; 2229 break; 2230 default: 2231 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2232 event); 2233 return -EINVAL; 2234 } 2235 2236 if (fn_wait) { 2237 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2238 ret = fn_wait(phys); 2239 DPU_ATRACE_END("wait_for_completion_event"); 2240 if (ret) 2241 return ret; 2242 } 2243 } 2244 2245 return ret; 2246 } 2247 2248 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2249 { 2250 struct dpu_encoder_virt *dpu_enc = NULL; 2251 2252 if (!encoder) { 2253 DPU_ERROR("invalid encoder\n"); 2254 return INTF_MODE_NONE; 2255 } 2256 dpu_enc = to_dpu_encoder_virt(encoder); 2257 2258 if (dpu_enc->cur_master) 2259 return dpu_enc->cur_master->intf_mode; 2260 2261 if (dpu_enc->num_phys_encs) 2262 return dpu_enc->phys_encs[0]->intf_mode; 2263 2264 return INTF_MODE_NONE; 2265 } 2266