1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/power/xlnx-zynqmp-power.h> 16 17/ { 18 compatible = "xlnx,zynqmp"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 compatible = "arm,cortex-a53"; 28 device_type = "cpu"; 29 enable-method = "psci"; 30 operating-points-v2 = <&cpu_opp_table>; 31 reg = <0x0>; 32 cpu-idle-states = <&CPU_SLEEP_0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "arm,cortex-a53"; 37 device_type = "cpu"; 38 enable-method = "psci"; 39 reg = <0x1>; 40 operating-points-v2 = <&cpu_opp_table>; 41 cpu-idle-states = <&CPU_SLEEP_0>; 42 }; 43 44 cpu2: cpu@2 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 enable-method = "psci"; 48 reg = <0x2>; 49 operating-points-v2 = <&cpu_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP_0>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 reg = <0x3>; 58 operating-points-v2 = <&cpu_opp_table>; 59 cpu-idle-states = <&CPU_SLEEP_0>; 60 }; 61 62 idle-states { 63 entry-method = "psci"; 64 65 CPU_SLEEP_0: cpu-sleep-0 { 66 compatible = "arm,idle-state"; 67 arm,psci-suspend-param = <0x40000000>; 68 local-timer-stop; 69 entry-latency-us = <300>; 70 exit-latency-us = <600>; 71 min-residency-us = <10000>; 72 }; 73 }; 74 }; 75 76 cpu_opp_table: cpu-opp-table { 77 compatible = "operating-points-v2"; 78 opp-shared; 79 opp00 { 80 opp-hz = /bits/ 64 <1199999988>; 81 opp-microvolt = <1000000>; 82 clock-latency-ns = <500000>; 83 }; 84 opp01 { 85 opp-hz = /bits/ 64 <599999994>; 86 opp-microvolt = <1000000>; 87 clock-latency-ns = <500000>; 88 }; 89 opp02 { 90 opp-hz = /bits/ 64 <399999996>; 91 opp-microvolt = <1000000>; 92 clock-latency-ns = <500000>; 93 }; 94 opp03 { 95 opp-hz = /bits/ 64 <299999997>; 96 opp-microvolt = <1000000>; 97 clock-latency-ns = <500000>; 98 }; 99 }; 100 101 dcc: dcc { 102 compatible = "arm,dcc"; 103 status = "disabled"; 104 }; 105 106 pmu { 107 compatible = "arm,armv8-pmuv3"; 108 interrupt-parent = <&gic>; 109 interrupts = <0 143 4>, 110 <0 144 4>, 111 <0 145 4>, 112 <0 146 4>; 113 }; 114 115 psci { 116 compatible = "arm,psci-0.2"; 117 method = "smc"; 118 }; 119 120 firmware { 121 zynqmp_firmware: zynqmp-firmware { 122 compatible = "xlnx,zynqmp-firmware"; 123 #power-domain-cells = <1>; 124 method = "smc"; 125 126 zynqmp_power: zynqmp-power { 127 compatible = "xlnx,zynqmp-power"; 128 interrupt-parent = <&gic>; 129 interrupts = <0 35 4>; 130 }; 131 132 zynqmp_clk: clock-controller { 133 u-boot,dm-pre-reloc; 134 #clock-cells = <1>; 135 compatible = "xlnx,zynqmp-clk"; 136 clocks = <&pss_ref_clk>, 137 <&video_clk>, 138 <&pss_alt_ref_clk>, 139 <&aux_ref_clk>, 140 <>_crx_ref_clk>; 141 clock-names = "pss_ref_clk", 142 "video_clk", 143 "pss_alt_ref_clk", 144 "aux_ref_clk", 145 "gt_crx_ref_clk"; 146 }; 147 148 nvmem_firmware { 149 compatible = "xlnx,zynqmp-nvmem-fw"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 soc_revision: soc_revision@0 { 154 reg = <0x0 0x4>; 155 }; 156 }; 157 158 zynqmp_pcap: pcap { 159 compatible = "xlnx,zynqmp-pcap-fpga"; 160 }; 161 }; 162 }; 163 164 timer { 165 compatible = "arm,armv8-timer"; 166 interrupt-parent = <&gic>; 167 interrupts = <1 13 0xf08>, 168 <1 14 0xf08>, 169 <1 11 0xf08>, 170 <1 10 0xf08>; 171 }; 172 173 fpga_full: fpga-full { 174 compatible = "fpga-region"; 175 fpga-mgr = <&zynqmp_pcap>; 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges; 179 }; 180 181 amba_apu: amba-apu@0 { 182 compatible = "simple-bus"; 183 #address-cells = <2>; 184 #size-cells = <1>; 185 ranges = <0 0 0 0 0xffffffff>; 186 187 gic: interrupt-controller@f9010000 { 188 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 189 #interrupt-cells = <3>; 190 reg = <0x0 0xf9010000 0x10000>, 191 <0x0 0xf9020000 0x20000>, 192 <0x0 0xf9040000 0x20000>, 193 <0x0 0xf9060000 0x20000>; 194 interrupt-controller; 195 interrupt-parent = <&gic>; 196 interrupts = <1 9 0xf04>; 197 }; 198 }; 199 200 amba: amba { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 can0: can@ff060000 { 207 compatible = "xlnx,zynq-can-1.0"; 208 status = "disabled"; 209 clock-names = "can_clk", "pclk"; 210 reg = <0x0 0xff060000 0x0 0x1000>; 211 interrupts = <0 23 4>; 212 interrupt-parent = <&gic>; 213 tx-fifo-depth = <0x40>; 214 rx-fifo-depth = <0x40>; 215 power-domains = <&zynqmp_firmware PD_CAN_0>; 216 }; 217 218 can1: can@ff070000 { 219 compatible = "xlnx,zynq-can-1.0"; 220 status = "disabled"; 221 clock-names = "can_clk", "pclk"; 222 reg = <0x0 0xff070000 0x0 0x1000>; 223 interrupts = <0 24 4>; 224 interrupt-parent = <&gic>; 225 tx-fifo-depth = <0x40>; 226 rx-fifo-depth = <0x40>; 227 power-domains = <&zynqmp_firmware PD_CAN_1>; 228 }; 229 230 cci: cci@fd6e0000 { 231 compatible = "arm,cci-400"; 232 reg = <0x0 0xfd6e0000 0x0 0x9000>; 233 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 237 pmu@9000 { 238 compatible = "arm,cci-400-pmu,r1"; 239 reg = <0x9000 0x5000>; 240 interrupt-parent = <&gic>; 241 interrupts = <0 123 4>, 242 <0 123 4>, 243 <0 123 4>, 244 <0 123 4>, 245 <0 123 4>; 246 }; 247 }; 248 249 /* GDMA */ 250 fpd_dma_chan1: dma@fd500000 { 251 status = "disabled"; 252 compatible = "xlnx,zynqmp-dma-1.0"; 253 reg = <0x0 0xfd500000 0x0 0x1000>; 254 interrupt-parent = <&gic>; 255 interrupts = <0 124 4>; 256 clock-names = "clk_main", "clk_apb"; 257 xlnx,bus-width = <128>; 258 power-domains = <&zynqmp_firmware PD_GDMA>; 259 }; 260 261 fpd_dma_chan2: dma@fd510000 { 262 status = "disabled"; 263 compatible = "xlnx,zynqmp-dma-1.0"; 264 reg = <0x0 0xfd510000 0x0 0x1000>; 265 interrupt-parent = <&gic>; 266 interrupts = <0 125 4>; 267 clock-names = "clk_main", "clk_apb"; 268 xlnx,bus-width = <128>; 269 power-domains = <&zynqmp_firmware PD_GDMA>; 270 }; 271 272 fpd_dma_chan3: dma@fd520000 { 273 status = "disabled"; 274 compatible = "xlnx,zynqmp-dma-1.0"; 275 reg = <0x0 0xfd520000 0x0 0x1000>; 276 interrupt-parent = <&gic>; 277 interrupts = <0 126 4>; 278 clock-names = "clk_main", "clk_apb"; 279 xlnx,bus-width = <128>; 280 power-domains = <&zynqmp_firmware PD_GDMA>; 281 }; 282 283 fpd_dma_chan4: dma@fd530000 { 284 status = "disabled"; 285 compatible = "xlnx,zynqmp-dma-1.0"; 286 reg = <0x0 0xfd530000 0x0 0x1000>; 287 interrupt-parent = <&gic>; 288 interrupts = <0 127 4>; 289 clock-names = "clk_main", "clk_apb"; 290 xlnx,bus-width = <128>; 291 power-domains = <&zynqmp_firmware PD_GDMA>; 292 }; 293 294 fpd_dma_chan5: dma@fd540000 { 295 status = "disabled"; 296 compatible = "xlnx,zynqmp-dma-1.0"; 297 reg = <0x0 0xfd540000 0x0 0x1000>; 298 interrupt-parent = <&gic>; 299 interrupts = <0 128 4>; 300 clock-names = "clk_main", "clk_apb"; 301 xlnx,bus-width = <128>; 302 power-domains = <&zynqmp_firmware PD_GDMA>; 303 }; 304 305 fpd_dma_chan6: dma@fd550000 { 306 status = "disabled"; 307 compatible = "xlnx,zynqmp-dma-1.0"; 308 reg = <0x0 0xfd550000 0x0 0x1000>; 309 interrupt-parent = <&gic>; 310 interrupts = <0 129 4>; 311 clock-names = "clk_main", "clk_apb"; 312 xlnx,bus-width = <128>; 313 power-domains = <&zynqmp_firmware PD_GDMA>; 314 }; 315 316 fpd_dma_chan7: dma@fd560000 { 317 status = "disabled"; 318 compatible = "xlnx,zynqmp-dma-1.0"; 319 reg = <0x0 0xfd560000 0x0 0x1000>; 320 interrupt-parent = <&gic>; 321 interrupts = <0 130 4>; 322 clock-names = "clk_main", "clk_apb"; 323 xlnx,bus-width = <128>; 324 power-domains = <&zynqmp_firmware PD_GDMA>; 325 }; 326 327 fpd_dma_chan8: dma@fd570000 { 328 status = "disabled"; 329 compatible = "xlnx,zynqmp-dma-1.0"; 330 reg = <0x0 0xfd570000 0x0 0x1000>; 331 interrupt-parent = <&gic>; 332 interrupts = <0 131 4>; 333 clock-names = "clk_main", "clk_apb"; 334 xlnx,bus-width = <128>; 335 power-domains = <&zynqmp_firmware PD_GDMA>; 336 }; 337 338 /* LPDDMA default allows only secured access. inorder to enable 339 * These dma channels, Users should ensure that these dma 340 * Channels are allowed for non secure access. 341 */ 342 lpd_dma_chan1: dma@ffa80000 { 343 status = "disabled"; 344 compatible = "xlnx,zynqmp-dma-1.0"; 345 reg = <0x0 0xffa80000 0x0 0x1000>; 346 interrupt-parent = <&gic>; 347 interrupts = <0 77 4>; 348 clock-names = "clk_main", "clk_apb"; 349 xlnx,bus-width = <64>; 350 power-domains = <&zynqmp_firmware PD_ADMA>; 351 }; 352 353 lpd_dma_chan2: dma@ffa90000 { 354 status = "disabled"; 355 compatible = "xlnx,zynqmp-dma-1.0"; 356 reg = <0x0 0xffa90000 0x0 0x1000>; 357 interrupt-parent = <&gic>; 358 interrupts = <0 78 4>; 359 clock-names = "clk_main", "clk_apb"; 360 xlnx,bus-width = <64>; 361 power-domains = <&zynqmp_firmware PD_ADMA>; 362 }; 363 364 lpd_dma_chan3: dma@ffaa0000 { 365 status = "disabled"; 366 compatible = "xlnx,zynqmp-dma-1.0"; 367 reg = <0x0 0xffaa0000 0x0 0x1000>; 368 interrupt-parent = <&gic>; 369 interrupts = <0 79 4>; 370 clock-names = "clk_main", "clk_apb"; 371 xlnx,bus-width = <64>; 372 power-domains = <&zynqmp_firmware PD_ADMA>; 373 }; 374 375 lpd_dma_chan4: dma@ffab0000 { 376 status = "disabled"; 377 compatible = "xlnx,zynqmp-dma-1.0"; 378 reg = <0x0 0xffab0000 0x0 0x1000>; 379 interrupt-parent = <&gic>; 380 interrupts = <0 80 4>; 381 clock-names = "clk_main", "clk_apb"; 382 xlnx,bus-width = <64>; 383 power-domains = <&zynqmp_firmware PD_ADMA>; 384 }; 385 386 lpd_dma_chan5: dma@ffac0000 { 387 status = "disabled"; 388 compatible = "xlnx,zynqmp-dma-1.0"; 389 reg = <0x0 0xffac0000 0x0 0x1000>; 390 interrupt-parent = <&gic>; 391 interrupts = <0 81 4>; 392 clock-names = "clk_main", "clk_apb"; 393 xlnx,bus-width = <64>; 394 power-domains = <&zynqmp_firmware PD_ADMA>; 395 }; 396 397 lpd_dma_chan6: dma@ffad0000 { 398 status = "disabled"; 399 compatible = "xlnx,zynqmp-dma-1.0"; 400 reg = <0x0 0xffad0000 0x0 0x1000>; 401 interrupt-parent = <&gic>; 402 interrupts = <0 82 4>; 403 clock-names = "clk_main", "clk_apb"; 404 xlnx,bus-width = <64>; 405 power-domains = <&zynqmp_firmware PD_ADMA>; 406 }; 407 408 lpd_dma_chan7: dma@ffae0000 { 409 status = "disabled"; 410 compatible = "xlnx,zynqmp-dma-1.0"; 411 reg = <0x0 0xffae0000 0x0 0x1000>; 412 interrupt-parent = <&gic>; 413 interrupts = <0 83 4>; 414 clock-names = "clk_main", "clk_apb"; 415 xlnx,bus-width = <64>; 416 power-domains = <&zynqmp_firmware PD_ADMA>; 417 }; 418 419 lpd_dma_chan8: dma@ffaf0000 { 420 status = "disabled"; 421 compatible = "xlnx,zynqmp-dma-1.0"; 422 reg = <0x0 0xffaf0000 0x0 0x1000>; 423 interrupt-parent = <&gic>; 424 interrupts = <0 84 4>; 425 clock-names = "clk_main", "clk_apb"; 426 xlnx,bus-width = <64>; 427 power-domains = <&zynqmp_firmware PD_ADMA>; 428 }; 429 430 mc: memory-controller@fd070000 { 431 compatible = "xlnx,zynqmp-ddrc-2.40a"; 432 reg = <0x0 0xfd070000 0x0 0x30000>; 433 interrupt-parent = <&gic>; 434 interrupts = <0 112 4>; 435 }; 436 437 gem0: ethernet@ff0b0000 { 438 compatible = "cdns,zynqmp-gem", "cdns,gem"; 439 status = "disabled"; 440 interrupt-parent = <&gic>; 441 interrupts = <0 57 4>, <0 57 4>; 442 reg = <0x0 0xff0b0000 0x0 0x1000>; 443 clock-names = "pclk", "hclk", "tx_clk"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 power-domains = <&zynqmp_firmware PD_ETH_0>; 447 }; 448 449 gem1: ethernet@ff0c0000 { 450 compatible = "cdns,zynqmp-gem", "cdns,gem"; 451 status = "disabled"; 452 interrupt-parent = <&gic>; 453 interrupts = <0 59 4>, <0 59 4>; 454 reg = <0x0 0xff0c0000 0x0 0x1000>; 455 clock-names = "pclk", "hclk", "tx_clk"; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 power-domains = <&zynqmp_firmware PD_ETH_1>; 459 }; 460 461 gem2: ethernet@ff0d0000 { 462 compatible = "cdns,zynqmp-gem", "cdns,gem"; 463 status = "disabled"; 464 interrupt-parent = <&gic>; 465 interrupts = <0 61 4>, <0 61 4>; 466 reg = <0x0 0xff0d0000 0x0 0x1000>; 467 clock-names = "pclk", "hclk", "tx_clk"; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 power-domains = <&zynqmp_firmware PD_ETH_2>; 471 }; 472 473 gem3: ethernet@ff0e0000 { 474 compatible = "cdns,zynqmp-gem", "cdns,gem"; 475 status = "disabled"; 476 interrupt-parent = <&gic>; 477 interrupts = <0 63 4>, <0 63 4>; 478 reg = <0x0 0xff0e0000 0x0 0x1000>; 479 clock-names = "pclk", "hclk", "tx_clk"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 power-domains = <&zynqmp_firmware PD_ETH_3>; 483 }; 484 485 gpio: gpio@ff0a0000 { 486 compatible = "xlnx,zynqmp-gpio-1.0"; 487 status = "disabled"; 488 #gpio-cells = <0x2>; 489 gpio-controller; 490 interrupt-parent = <&gic>; 491 interrupts = <0 16 4>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 reg = <0x0 0xff0a0000 0x0 0x1000>; 495 power-domains = <&zynqmp_firmware PD_GPIO>; 496 }; 497 498 i2c0: i2c@ff020000 { 499 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 500 status = "disabled"; 501 interrupt-parent = <&gic>; 502 interrupts = <0 17 4>; 503 reg = <0x0 0xff020000 0x0 0x1000>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 power-domains = <&zynqmp_firmware PD_I2C_0>; 507 }; 508 509 i2c1: i2c@ff030000 { 510 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 511 status = "disabled"; 512 interrupt-parent = <&gic>; 513 interrupts = <0 18 4>; 514 reg = <0x0 0xff030000 0x0 0x1000>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 power-domains = <&zynqmp_firmware PD_I2C_1>; 518 }; 519 520 pcie: pcie@fd0e0000 { 521 compatible = "xlnx,nwl-pcie-2.11"; 522 status = "disabled"; 523 #address-cells = <3>; 524 #size-cells = <2>; 525 #interrupt-cells = <1>; 526 msi-controller; 527 device_type = "pci"; 528 interrupt-parent = <&gic>; 529 interrupts = <0 118 4>, 530 <0 117 4>, 531 <0 116 4>, 532 <0 115 4>, /* MSI_1 [63...32] */ 533 <0 114 4>; /* MSI_0 [31...0] */ 534 interrupt-names = "misc", "dummy", "intx", 535 "msi1", "msi0"; 536 msi-parent = <&pcie>; 537 reg = <0x0 0xfd0e0000 0x0 0x1000>, 538 <0x0 0xfd480000 0x0 0x1000>, 539 <0x80 0x00000000 0x0 0x1000000>; 540 reg-names = "breg", "pcireg", "cfg"; 541 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 542 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 543 bus-range = <0x00 0xff>; 544 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 545 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 546 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 547 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 548 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 549 power-domains = <&zynqmp_firmware PD_PCIE>; 550 pcie_intc: legacy-interrupt-controller { 551 interrupt-controller; 552 #address-cells = <0>; 553 #interrupt-cells = <1>; 554 }; 555 }; 556 557 rtc: rtc@ffa60000 { 558 compatible = "xlnx,zynqmp-rtc"; 559 status = "disabled"; 560 reg = <0x0 0xffa60000 0x0 0x100>; 561 interrupt-parent = <&gic>; 562 interrupts = <0 26 4>, <0 27 4>; 563 interrupt-names = "alarm", "sec"; 564 calibration = <0x8000>; 565 }; 566 567 sata: ahci@fd0c0000 { 568 compatible = "ceva,ahci-1v84"; 569 status = "disabled"; 570 reg = <0x0 0xfd0c0000 0x0 0x2000>; 571 interrupt-parent = <&gic>; 572 interrupts = <0 133 4>; 573 power-domains = <&zynqmp_firmware PD_SATA>; 574 }; 575 576 sdhci0: mmc@ff160000 { 577 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 578 status = "disabled"; 579 interrupt-parent = <&gic>; 580 interrupts = <0 48 4>; 581 reg = <0x0 0xff160000 0x0 0x1000>; 582 clock-names = "clk_xin", "clk_ahb"; 583 #clock-cells = <1>; 584 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 585 power-domains = <&zynqmp_firmware PD_SD_0>; 586 }; 587 588 sdhci1: mmc@ff170000 { 589 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 590 status = "disabled"; 591 interrupt-parent = <&gic>; 592 interrupts = <0 49 4>; 593 reg = <0x0 0xff170000 0x0 0x1000>; 594 clock-names = "clk_xin", "clk_ahb"; 595 #clock-cells = <1>; 596 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 597 power-domains = <&zynqmp_firmware PD_SD_1>; 598 }; 599 600 smmu: smmu@fd800000 { 601 compatible = "arm,mmu-500"; 602 reg = <0x0 0xfd800000 0x0 0x20000>; 603 status = "disabled"; 604 #global-interrupts = <1>; 605 interrupt-parent = <&gic>; 606 interrupts = <0 155 4>, 607 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 608 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 609 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 610 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 611 }; 612 613 spi0: spi@ff040000 { 614 compatible = "cdns,spi-r1p6"; 615 status = "disabled"; 616 interrupt-parent = <&gic>; 617 interrupts = <0 19 4>; 618 reg = <0x0 0xff040000 0x0 0x1000>; 619 clock-names = "ref_clk", "pclk"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 power-domains = <&zynqmp_firmware PD_SPI_0>; 623 }; 624 625 spi1: spi@ff050000 { 626 compatible = "cdns,spi-r1p6"; 627 status = "disabled"; 628 interrupt-parent = <&gic>; 629 interrupts = <0 20 4>; 630 reg = <0x0 0xff050000 0x0 0x1000>; 631 clock-names = "ref_clk", "pclk"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 power-domains = <&zynqmp_firmware PD_SPI_1>; 635 }; 636 637 ttc0: timer@ff110000 { 638 compatible = "cdns,ttc"; 639 status = "disabled"; 640 interrupt-parent = <&gic>; 641 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 642 reg = <0x0 0xff110000 0x0 0x1000>; 643 timer-width = <32>; 644 power-domains = <&zynqmp_firmware PD_TTC_0>; 645 }; 646 647 ttc1: timer@ff120000 { 648 compatible = "cdns,ttc"; 649 status = "disabled"; 650 interrupt-parent = <&gic>; 651 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 652 reg = <0x0 0xff120000 0x0 0x1000>; 653 timer-width = <32>; 654 power-domains = <&zynqmp_firmware PD_TTC_1>; 655 }; 656 657 ttc2: timer@ff130000 { 658 compatible = "cdns,ttc"; 659 status = "disabled"; 660 interrupt-parent = <&gic>; 661 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 662 reg = <0x0 0xff130000 0x0 0x1000>; 663 timer-width = <32>; 664 power-domains = <&zynqmp_firmware PD_TTC_2>; 665 }; 666 667 ttc3: timer@ff140000 { 668 compatible = "cdns,ttc"; 669 status = "disabled"; 670 interrupt-parent = <&gic>; 671 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 672 reg = <0x0 0xff140000 0x0 0x1000>; 673 timer-width = <32>; 674 power-domains = <&zynqmp_firmware PD_TTC_3>; 675 }; 676 677 uart0: serial@ff000000 { 678 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 679 status = "disabled"; 680 interrupt-parent = <&gic>; 681 interrupts = <0 21 4>; 682 reg = <0x0 0xff000000 0x0 0x1000>; 683 clock-names = "uart_clk", "pclk"; 684 power-domains = <&zynqmp_firmware PD_UART_0>; 685 }; 686 687 uart1: serial@ff010000 { 688 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 689 status = "disabled"; 690 interrupt-parent = <&gic>; 691 interrupts = <0 22 4>; 692 reg = <0x0 0xff010000 0x0 0x1000>; 693 clock-names = "uart_clk", "pclk"; 694 power-domains = <&zynqmp_firmware PD_UART_1>; 695 }; 696 697 usb0: usb@fe200000 { 698 compatible = "snps,dwc3"; 699 status = "disabled"; 700 interrupt-parent = <&gic>; 701 interrupts = <0 65 4>; 702 reg = <0x0 0xfe200000 0x0 0x40000>; 703 clock-names = "clk_xin", "clk_ahb"; 704 power-domains = <&zynqmp_firmware PD_USB_0>; 705 }; 706 707 usb1: usb@fe300000 { 708 compatible = "snps,dwc3"; 709 status = "disabled"; 710 interrupt-parent = <&gic>; 711 interrupts = <0 70 4>; 712 reg = <0x0 0xfe300000 0x0 0x40000>; 713 clock-names = "clk_xin", "clk_ahb"; 714 power-domains = <&zynqmp_firmware PD_USB_1>; 715 }; 716 717 watchdog0: watchdog@fd4d0000 { 718 compatible = "cdns,wdt-r1p2"; 719 status = "disabled"; 720 interrupt-parent = <&gic>; 721 interrupts = <0 113 1>; 722 reg = <0x0 0xfd4d0000 0x0 0x1000>; 723 timeout-sec = <10>; 724 }; 725 }; 726}; 727