1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Jike Song <jike.song@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Min He <min.he@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * 32 */ 33 34 #include "i915_drv.h" 35 #include "gvt.h" 36 37 enum { 38 INTEL_GVT_PCI_BAR_GTTMMIO = 0, 39 INTEL_GVT_PCI_BAR_APERTURE, 40 INTEL_GVT_PCI_BAR_PIO, 41 INTEL_GVT_PCI_BAR_MAX, 42 }; 43 44 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one 45 * byte) byte by byte in standard pci configuration space. (not the full 46 * 256 bytes.) 47 */ 48 static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = { 49 [PCI_COMMAND] = 0xff, 0x07, 50 [PCI_STATUS] = 0x00, 0xf9, /* the only one RW1C byte */ 51 [PCI_CACHE_LINE_SIZE] = 0xff, 52 [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff, 53 [PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff, 54 [PCI_INTERRUPT_LINE] = 0xff, 55 }; 56 57 /** 58 * vgpu_pci_cfg_mem_write - write virtual cfg space memory 59 * @vgpu: target vgpu 60 * @off: offset 61 * @src: src ptr to write 62 * @bytes: number of bytes 63 * 64 * Use this function to write virtual cfg space memory. 65 * For standard cfg space, only RW bits can be changed, 66 * and we emulates the RW1C behavior of PCI_STATUS register. 67 */ 68 static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 69 u8 *src, unsigned int bytes) 70 { 71 u8 *cfg_base = vgpu_cfg_space(vgpu); 72 u8 mask, new, old; 73 int i = 0; 74 75 for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) { 76 mask = pci_cfg_space_rw_bmp[off + i]; 77 old = cfg_base[off + i]; 78 new = src[i] & mask; 79 80 /** 81 * The PCI_STATUS high byte has RW1C bits, here 82 * emulates clear by writing 1 for these bits. 83 * Writing a 0b to RW1C bits has no effect. 84 */ 85 if (off + i == PCI_STATUS + 1) 86 new = (~new & old) & mask; 87 88 cfg_base[off + i] = (old & ~mask) | new; 89 } 90 91 /* For other configuration space directly copy as it is. */ 92 if (i < bytes) 93 memcpy(cfg_base + off + i, src + i, bytes - i); 94 } 95 96 /** 97 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read 98 * @vgpu: target vgpu 99 * @offset: offset 100 * @p_data: return data ptr 101 * @bytes: number of bytes to read 102 * 103 * Returns: 104 * Zero on success, negative error code if failed. 105 */ 106 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 107 void *p_data, unsigned int bytes) 108 { 109 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 110 111 if (drm_WARN_ON(&i915->drm, bytes > 4)) 112 return -EINVAL; 113 114 if (drm_WARN_ON(&i915->drm, 115 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 116 return -EINVAL; 117 118 memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes); 119 return 0; 120 } 121 122 static int map_aperture(struct intel_vgpu *vgpu, bool map) 123 { 124 phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu); 125 unsigned long aperture_sz = vgpu_aperture_sz(vgpu); 126 u64 first_gfn; 127 u64 val; 128 int ret; 129 130 if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) 131 return 0; 132 133 val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2]; 134 if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) 135 val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); 136 else 137 val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); 138 139 first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; 140 141 ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, 142 aperture_pa >> PAGE_SHIFT, 143 aperture_sz >> PAGE_SHIFT, 144 map); 145 if (ret) 146 return ret; 147 148 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; 149 return 0; 150 } 151 152 static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap) 153 { 154 u64 start, end; 155 u64 val; 156 int ret; 157 158 if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) 159 return 0; 160 161 val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0]; 162 if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) 163 start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); 164 else 165 start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); 166 167 start &= ~GENMASK(3, 0); 168 end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1; 169 170 ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap); 171 if (ret) 172 return ret; 173 174 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; 175 return 0; 176 } 177 178 static int emulate_pci_command_write(struct intel_vgpu *vgpu, 179 unsigned int offset, void *p_data, unsigned int bytes) 180 { 181 u8 old = vgpu_cfg_space(vgpu)[offset]; 182 u8 new = *(u8 *)p_data; 183 u8 changed = old ^ new; 184 int ret; 185 186 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 187 if (!(changed & PCI_COMMAND_MEMORY)) 188 return 0; 189 190 if (old & PCI_COMMAND_MEMORY) { 191 ret = trap_gttmmio(vgpu, false); 192 if (ret) 193 return ret; 194 ret = map_aperture(vgpu, false); 195 if (ret) 196 return ret; 197 } else { 198 ret = trap_gttmmio(vgpu, true); 199 if (ret) 200 return ret; 201 ret = map_aperture(vgpu, true); 202 if (ret) 203 return ret; 204 } 205 206 return 0; 207 } 208 209 static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, 210 unsigned int offset, void *p_data, unsigned int bytes) 211 { 212 u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 213 u32 new = *(u32 *)(p_data); 214 215 if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK) 216 /* We don't have rom, return size of 0. */ 217 *pval = 0; 218 else 219 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 220 return 0; 221 } 222 223 static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 224 void *p_data, unsigned int bytes) 225 { 226 u32 new = *(u32 *)(p_data); 227 bool lo = IS_ALIGNED(offset, 8); 228 u64 size; 229 int ret = 0; 230 bool mmio_enabled = 231 vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; 232 struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; 233 234 /* 235 * Power-up software can determine how much address 236 * space the device requires by writing a value of 237 * all 1's to the register and then reading the value 238 * back. The device will return 0's in all don't-care 239 * address bits. 240 */ 241 if (new == 0xffffffff) { 242 switch (offset) { 243 case PCI_BASE_ADDRESS_0: 244 case PCI_BASE_ADDRESS_1: 245 size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1); 246 intel_vgpu_write_pci_bar(vgpu, offset, 247 size >> (lo ? 0 : 32), lo); 248 /* 249 * Untrap the BAR, since guest hasn't configured a 250 * valid GPA 251 */ 252 ret = trap_gttmmio(vgpu, false); 253 break; 254 case PCI_BASE_ADDRESS_2: 255 case PCI_BASE_ADDRESS_3: 256 size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); 257 intel_vgpu_write_pci_bar(vgpu, offset, 258 size >> (lo ? 0 : 32), lo); 259 ret = map_aperture(vgpu, false); 260 break; 261 default: 262 /* Unimplemented BARs */ 263 intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false); 264 } 265 } else { 266 switch (offset) { 267 case PCI_BASE_ADDRESS_0: 268 case PCI_BASE_ADDRESS_1: 269 /* 270 * Untrap the old BAR first, since guest has 271 * re-configured the BAR 272 */ 273 trap_gttmmio(vgpu, false); 274 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 275 ret = trap_gttmmio(vgpu, mmio_enabled); 276 break; 277 case PCI_BASE_ADDRESS_2: 278 case PCI_BASE_ADDRESS_3: 279 map_aperture(vgpu, false); 280 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 281 ret = map_aperture(vgpu, mmio_enabled); 282 break; 283 default: 284 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 285 } 286 } 287 return ret; 288 } 289 290 /** 291 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write 292 * @vgpu: target vgpu 293 * @offset: offset 294 * @p_data: write data ptr 295 * @bytes: number of bytes to write 296 * 297 * Returns: 298 * Zero on success, negative error code if failed. 299 */ 300 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 301 void *p_data, unsigned int bytes) 302 { 303 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 304 int ret; 305 306 if (drm_WARN_ON(&i915->drm, bytes > 4)) 307 return -EINVAL; 308 309 if (drm_WARN_ON(&i915->drm, 310 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 311 return -EINVAL; 312 313 /* First check if it's PCI_COMMAND */ 314 if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) { 315 if (drm_WARN_ON(&i915->drm, bytes > 2)) 316 return -EINVAL; 317 return emulate_pci_command_write(vgpu, offset, p_data, bytes); 318 } 319 320 switch (rounddown(offset, 4)) { 321 case PCI_ROM_ADDRESS: 322 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 323 return -EINVAL; 324 return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes); 325 326 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: 327 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 328 return -EINVAL; 329 return emulate_pci_bar_write(vgpu, offset, p_data, bytes); 330 331 case INTEL_GVT_PCI_SWSCI: 332 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 333 return -EINVAL; 334 ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data); 335 if (ret) 336 return ret; 337 break; 338 339 case INTEL_GVT_PCI_OPREGION: 340 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 341 return -EINVAL; 342 ret = intel_vgpu_opregion_base_write_handler(vgpu, 343 *(u32 *)p_data); 344 if (ret) 345 return ret; 346 347 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 348 break; 349 default: 350 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 351 break; 352 } 353 return 0; 354 } 355 356 /** 357 * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU 358 * 359 * @vgpu: a vGPU 360 * @primary: is the vGPU presented as primary 361 * 362 */ 363 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 364 bool primary) 365 { 366 struct intel_gvt *gvt = vgpu->gvt; 367 const struct intel_gvt_device_info *info = &gvt->device_info; 368 u16 *gmch_ctl; 369 370 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, 371 info->cfg_space_size); 372 373 if (!primary) { 374 vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = 375 INTEL_GVT_PCI_CLASS_VGA_OTHER; 376 vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = 377 INTEL_GVT_PCI_CLASS_VGA_OTHER; 378 } 379 380 /* Show guest that there isn't any stolen memory.*/ 381 gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); 382 *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT); 383 384 intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, 385 gvt_aperture_pa_base(gvt), true); 386 387 vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO 388 | PCI_COMMAND_MEMORY 389 | PCI_COMMAND_MASTER); 390 /* 391 * Clear the bar upper 32bit and let guest to assign the new value 392 */ 393 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); 394 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); 395 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8); 396 memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); 397 398 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = 399 pci_resource_len(gvt->gt->i915->drm.pdev, 0); 400 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = 401 pci_resource_len(gvt->gt->i915->drm.pdev, 2); 402 403 memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); 404 } 405 406 /** 407 * intel_vgpu_reset_cfg_space - reset vGPU configuration space 408 * 409 * @vgpu: a vGPU 410 * 411 */ 412 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu) 413 { 414 u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND]; 415 bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] != 416 INTEL_GVT_PCI_CLASS_VGA_OTHER; 417 418 if (cmd & PCI_COMMAND_MEMORY) { 419 trap_gttmmio(vgpu, false); 420 map_aperture(vgpu, false); 421 } 422 423 /** 424 * Currently we only do such reset when vGPU is not 425 * owned by any VM, so we simply restore entire cfg 426 * space to default value. 427 */ 428 intel_vgpu_init_cfg_space(vgpu, primary); 429 } 430