1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cht-bsw-max98090.c - ASoc Machine driver for Intel Cherryview-based 4 * platforms Cherrytrail and Braswell, with max98090 & TI codec. 5 * 6 * Copyright (C) 2015 Intel Corp 7 * Author: Fang, Yang A <yang.a.fang@intel.com> 8 * This file is modified from cht_bsw_rt5645.c 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 * 11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 12 */ 13 14 #include <linux/dmi.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/clk.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/soc-acpi.h> 25 #include <sound/jack.h> 26 #include "../../codecs/max98090.h" 27 #include "../atom/sst-atom-controls.h" 28 #include "../../codecs/ts3a227e.h" 29 30 #define CHT_PLAT_CLK_3_HZ 19200000 31 #define CHT_CODEC_DAI "HiFi" 32 33 #define QUIRK_PMC_PLT_CLK_0 0x01 34 35 struct cht_mc_private { 36 struct clk *mclk; 37 struct snd_soc_jack jack; 38 bool ts3a227e_present; 39 int quirks; 40 }; 41 42 static int platform_clock_control(struct snd_soc_dapm_widget *w, 43 struct snd_kcontrol *k, int event) 44 { 45 struct snd_soc_dapm_context *dapm = w->dapm; 46 struct snd_soc_card *card = dapm->card; 47 struct snd_soc_dai *codec_dai; 48 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 49 int ret; 50 51 /* See the comment in snd_cht_mc_probe() */ 52 if (ctx->quirks & QUIRK_PMC_PLT_CLK_0) 53 return 0; 54 55 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI); 56 if (!codec_dai) { 57 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); 58 return -EIO; 59 } 60 61 if (SND_SOC_DAPM_EVENT_ON(event)) { 62 ret = clk_prepare_enable(ctx->mclk); 63 if (ret < 0) { 64 dev_err(card->dev, 65 "could not configure MCLK state"); 66 return ret; 67 } 68 } else { 69 clk_disable_unprepare(ctx->mclk); 70 } 71 72 return 0; 73 } 74 75 static const struct snd_soc_dapm_widget cht_dapm_widgets[] = { 76 SND_SOC_DAPM_HP("Headphone", NULL), 77 SND_SOC_DAPM_MIC("Headset Mic", NULL), 78 SND_SOC_DAPM_MIC("Int Mic", NULL), 79 SND_SOC_DAPM_SPK("Ext Spk", NULL), 80 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0, 81 platform_clock_control, SND_SOC_DAPM_PRE_PMU | 82 SND_SOC_DAPM_POST_PMD), 83 }; 84 85 static const struct snd_soc_dapm_route cht_audio_map[] = { 86 {"IN34", NULL, "Headset Mic"}, 87 {"Headset Mic", NULL, "MICBIAS"}, 88 {"DMICL", NULL, "Int Mic"}, 89 {"Headphone", NULL, "HPL"}, 90 {"Headphone", NULL, "HPR"}, 91 {"Ext Spk", NULL, "SPKL"}, 92 {"Ext Spk", NULL, "SPKR"}, 93 {"HiFi Playback", NULL, "ssp2 Tx"}, 94 {"ssp2 Tx", NULL, "codec_out0"}, 95 {"ssp2 Tx", NULL, "codec_out1"}, 96 {"codec_in0", NULL, "ssp2 Rx" }, 97 {"codec_in1", NULL, "ssp2 Rx" }, 98 {"ssp2 Rx", NULL, "HiFi Capture"}, 99 {"Headphone", NULL, "Platform Clock"}, 100 {"Headset Mic", NULL, "Platform Clock"}, 101 {"Int Mic", NULL, "Platform Clock"}, 102 {"Ext Spk", NULL, "Platform Clock"}, 103 }; 104 105 static const struct snd_kcontrol_new cht_mc_controls[] = { 106 SOC_DAPM_PIN_SWITCH("Headphone"), 107 SOC_DAPM_PIN_SWITCH("Headset Mic"), 108 SOC_DAPM_PIN_SWITCH("Int Mic"), 109 SOC_DAPM_PIN_SWITCH("Ext Spk"), 110 }; 111 112 static int cht_aif1_hw_params(struct snd_pcm_substream *substream, 113 struct snd_pcm_hw_params *params) 114 { 115 struct snd_soc_pcm_runtime *rtd = substream->private_data; 116 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 117 int ret; 118 119 ret = snd_soc_dai_set_sysclk(codec_dai, M98090_REG_SYSTEM_CLOCK, 120 CHT_PLAT_CLK_3_HZ, SND_SOC_CLOCK_IN); 121 if (ret < 0) { 122 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); 123 return ret; 124 } 125 126 return 0; 127 } 128 129 static int cht_ti_jack_event(struct notifier_block *nb, 130 unsigned long event, void *data) 131 { 132 struct snd_soc_jack *jack = (struct snd_soc_jack *)data; 133 struct snd_soc_dapm_context *dapm = &jack->card->dapm; 134 135 if (event & SND_JACK_MICROPHONE) { 136 snd_soc_dapm_force_enable_pin(dapm, "SHDN"); 137 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 138 snd_soc_dapm_sync(dapm); 139 } else { 140 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 141 snd_soc_dapm_disable_pin(dapm, "SHDN"); 142 snd_soc_dapm_sync(dapm); 143 } 144 145 return 0; 146 } 147 148 static struct notifier_block cht_jack_nb = { 149 .notifier_call = cht_ti_jack_event, 150 }; 151 152 static struct snd_soc_jack_pin hs_jack_pins[] = { 153 { 154 .pin = "Headphone", 155 .mask = SND_JACK_HEADPHONE, 156 }, 157 { 158 .pin = "Headset Mic", 159 .mask = SND_JACK_MICROPHONE, 160 }, 161 }; 162 163 static struct snd_soc_jack_gpio hs_jack_gpios[] = { 164 { 165 .name = "hp", 166 .report = SND_JACK_HEADPHONE | SND_JACK_LINEOUT, 167 .debounce_time = 200, 168 }, 169 { 170 .name = "mic", 171 .invert = 1, 172 .report = SND_JACK_MICROPHONE, 173 .debounce_time = 200, 174 }, 175 }; 176 177 static const struct acpi_gpio_params hp_gpios = { 0, 0, false }; 178 static const struct acpi_gpio_params mic_gpios = { 1, 0, false }; 179 180 static const struct acpi_gpio_mapping acpi_max98090_gpios[] = { 181 { "hp-gpios", &hp_gpios, 1 }, 182 { "mic-gpios", &mic_gpios, 1 }, 183 {}, 184 }; 185 186 static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 187 { 188 int ret; 189 int jack_type; 190 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); 191 struct snd_soc_jack *jack = &ctx->jack; 192 193 if (ctx->ts3a227e_present) { 194 /* 195 * The jack has already been created in the 196 * cht_max98090_headset_init() function. 197 */ 198 snd_soc_jack_notifier_register(jack, &cht_jack_nb); 199 return 0; 200 } 201 202 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE; 203 204 ret = snd_soc_card_jack_new(runtime->card, "Headset Jack", 205 jack_type, jack, 206 hs_jack_pins, ARRAY_SIZE(hs_jack_pins)); 207 if (ret) { 208 dev_err(runtime->dev, "Headset Jack creation failed %d\n", ret); 209 return ret; 210 } 211 212 ret = snd_soc_jack_add_gpiods(runtime->card->dev->parent, jack, 213 ARRAY_SIZE(hs_jack_gpios), 214 hs_jack_gpios); 215 if (ret) { 216 /* 217 * flag error but don't bail if jack detect is broken 218 * due to platform issues or bad BIOS/configuration 219 */ 220 dev_err(runtime->dev, 221 "jack detection gpios not added, error %d\n", ret); 222 } 223 224 /* See the comment in snd_cht_mc_probe() */ 225 if (ctx->quirks & QUIRK_PMC_PLT_CLK_0) 226 return 0; 227 228 /* 229 * The firmware might enable the clock at 230 * boot (this information may or may not 231 * be reflected in the enable clock register). 232 * To change the rate we must disable the clock 233 * first to cover these cases. Due to common 234 * clock framework restrictions that do not allow 235 * to disable a clock that has not been enabled, 236 * we need to enable the clock first. 237 */ 238 ret = clk_prepare_enable(ctx->mclk); 239 if (!ret) 240 clk_disable_unprepare(ctx->mclk); 241 242 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); 243 244 if (ret) 245 dev_err(runtime->dev, "unable to set MCLK rate\n"); 246 247 return ret; 248 } 249 250 static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd, 251 struct snd_pcm_hw_params *params) 252 { 253 struct snd_interval *rate = hw_param_interval(params, 254 SNDRV_PCM_HW_PARAM_RATE); 255 struct snd_interval *channels = hw_param_interval(params, 256 SNDRV_PCM_HW_PARAM_CHANNELS); 257 int ret = 0; 258 unsigned int fmt = 0; 259 260 ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_cpu(rtd, 0), 0x3, 0x3, 2, 16); 261 if (ret < 0) { 262 dev_err(rtd->dev, "can't set cpu_dai slot fmt: %d\n", ret); 263 return ret; 264 } 265 266 fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF 267 | SND_SOC_DAIFMT_CBS_CFS; 268 269 ret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0), fmt); 270 if (ret < 0) { 271 dev_err(rtd->dev, "can't set cpu_dai set fmt: %d\n", ret); 272 return ret; 273 } 274 275 /* The DSP will covert the FE rate to 48k, stereo, 24bits */ 276 rate->min = rate->max = 48000; 277 channels->min = channels->max = 2; 278 279 /* set SSP2 to 16-bit */ 280 params_set_format(params, SNDRV_PCM_FORMAT_S16_LE); 281 return 0; 282 } 283 284 static int cht_aif1_startup(struct snd_pcm_substream *substream) 285 { 286 return snd_pcm_hw_constraint_single(substream->runtime, 287 SNDRV_PCM_HW_PARAM_RATE, 48000); 288 } 289 290 static int cht_max98090_headset_init(struct snd_soc_component *component) 291 { 292 struct snd_soc_card *card = component->card; 293 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 294 struct snd_soc_jack *jack = &ctx->jack; 295 int jack_type; 296 int ret; 297 298 /* 299 * TI supports 4 butons headset detection 300 * KEY_MEDIA 301 * KEY_VOICECOMMAND 302 * KEY_VOLUMEUP 303 * KEY_VOLUMEDOWN 304 */ 305 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE | 306 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 307 SND_JACK_BTN_2 | SND_JACK_BTN_3; 308 309 ret = snd_soc_card_jack_new(card, "Headset Jack", jack_type, 310 jack, NULL, 0); 311 if (ret) { 312 dev_err(card->dev, "Headset Jack creation failed %d\n", ret); 313 return ret; 314 } 315 316 return ts3a227e_enable_jack_detect(component, jack); 317 } 318 319 static const struct snd_soc_ops cht_aif1_ops = { 320 .startup = cht_aif1_startup, 321 }; 322 323 static const struct snd_soc_ops cht_be_ssp2_ops = { 324 .hw_params = cht_aif1_hw_params, 325 }; 326 327 static struct snd_soc_aux_dev cht_max98090_headset_dev = { 328 .dlc = COMP_AUX("i2c-104C227E:00"), 329 .init = cht_max98090_headset_init, 330 }; 331 332 SND_SOC_DAILINK_DEF(dummy, 333 DAILINK_COMP_ARRAY(COMP_DUMMY())); 334 335 SND_SOC_DAILINK_DEF(media, 336 DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai"))); 337 338 SND_SOC_DAILINK_DEF(deepbuffer, 339 DAILINK_COMP_ARRAY(COMP_CPU("deepbuffer-cpu-dai"))); 340 341 SND_SOC_DAILINK_DEF(ssp2_port, 342 DAILINK_COMP_ARRAY(COMP_CPU("ssp2-port"))); 343 SND_SOC_DAILINK_DEF(ssp2_codec, 344 DAILINK_COMP_ARRAY(COMP_CODEC("i2c-193C9890:00", "HiFi"))); 345 346 SND_SOC_DAILINK_DEF(platform, 347 DAILINK_COMP_ARRAY(COMP_PLATFORM("sst-mfld-platform"))); 348 349 static struct snd_soc_dai_link cht_dailink[] = { 350 [MERR_DPCM_AUDIO] = { 351 .name = "Audio Port", 352 .stream_name = "Audio", 353 .nonatomic = true, 354 .dynamic = 1, 355 .dpcm_playback = 1, 356 .dpcm_capture = 1, 357 .ops = &cht_aif1_ops, 358 SND_SOC_DAILINK_REG(media, dummy, platform), 359 }, 360 [MERR_DPCM_DEEP_BUFFER] = { 361 .name = "Deep-Buffer Audio Port", 362 .stream_name = "Deep-Buffer Audio", 363 .nonatomic = true, 364 .dynamic = 1, 365 .dpcm_playback = 1, 366 .ops = &cht_aif1_ops, 367 SND_SOC_DAILINK_REG(deepbuffer, dummy, platform), 368 }, 369 /* back ends */ 370 { 371 .name = "SSP2-Codec", 372 .id = 0, 373 .no_pcm = 1, 374 .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF 375 | SND_SOC_DAIFMT_CBS_CFS, 376 .init = cht_codec_init, 377 .be_hw_params_fixup = cht_codec_fixup, 378 .dpcm_playback = 1, 379 .dpcm_capture = 1, 380 .ops = &cht_be_ssp2_ops, 381 SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform), 382 }, 383 }; 384 385 /* SoC card */ 386 static struct snd_soc_card snd_soc_card_cht = { 387 .name = "chtmax98090", 388 .owner = THIS_MODULE, 389 .dai_link = cht_dailink, 390 .num_links = ARRAY_SIZE(cht_dailink), 391 .aux_dev = &cht_max98090_headset_dev, 392 .num_aux_devs = 1, 393 .dapm_widgets = cht_dapm_widgets, 394 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets), 395 .dapm_routes = cht_audio_map, 396 .num_dapm_routes = ARRAY_SIZE(cht_audio_map), 397 .controls = cht_mc_controls, 398 .num_controls = ARRAY_SIZE(cht_mc_controls), 399 }; 400 401 static const struct dmi_system_id cht_max98090_quirk_table[] = { 402 { 403 /* Banjo model Chromebook */ 404 .matches = { 405 DMI_MATCH(DMI_PRODUCT_NAME, "Banjo"), 406 }, 407 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 408 }, 409 { 410 /* Candy model Chromebook */ 411 .matches = { 412 DMI_MATCH(DMI_PRODUCT_NAME, "Candy"), 413 }, 414 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 415 }, 416 { 417 /* Clapper model Chromebook */ 418 .matches = { 419 DMI_MATCH(DMI_PRODUCT_NAME, "Clapper"), 420 }, 421 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 422 }, 423 { 424 /* Cyan model Chromebook */ 425 .matches = { 426 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 427 }, 428 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 429 }, 430 { 431 /* Enguarde model Chromebook */ 432 .matches = { 433 DMI_MATCH(DMI_PRODUCT_NAME, "Enguarde"), 434 }, 435 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 436 }, 437 { 438 /* Glimmer model Chromebook */ 439 .matches = { 440 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"), 441 }, 442 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 443 }, 444 { 445 /* Gnawty model Chromebook (Acer Chromebook CB3-111) */ 446 .matches = { 447 DMI_MATCH(DMI_PRODUCT_NAME, "Gnawty"), 448 }, 449 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 450 }, 451 { 452 /* Heli model Chromebook */ 453 .matches = { 454 DMI_MATCH(DMI_PRODUCT_NAME, "Heli"), 455 }, 456 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 457 }, 458 { 459 /* Kip model Chromebook */ 460 .matches = { 461 DMI_MATCH(DMI_PRODUCT_NAME, "Kip"), 462 }, 463 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 464 }, 465 { 466 /* Ninja model Chromebook */ 467 .matches = { 468 DMI_MATCH(DMI_PRODUCT_NAME, "Ninja"), 469 }, 470 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 471 }, 472 { 473 /* Orco model Chromebook */ 474 .matches = { 475 DMI_MATCH(DMI_PRODUCT_NAME, "Orco"), 476 }, 477 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 478 }, 479 { 480 /* Quawks model Chromebook */ 481 .matches = { 482 DMI_MATCH(DMI_PRODUCT_NAME, "Quawks"), 483 }, 484 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 485 }, 486 { 487 /* Rambi model Chromebook */ 488 .matches = { 489 DMI_MATCH(DMI_PRODUCT_NAME, "Rambi"), 490 }, 491 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 492 }, 493 { 494 /* Squawks model Chromebook */ 495 .matches = { 496 DMI_MATCH(DMI_PRODUCT_NAME, "Squawks"), 497 }, 498 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 499 }, 500 { 501 /* Sumo model Chromebook */ 502 .matches = { 503 DMI_MATCH(DMI_PRODUCT_NAME, "Sumo"), 504 }, 505 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 506 }, 507 { 508 /* Swanky model Chromebook (Toshiba Chromebook 2) */ 509 .matches = { 510 DMI_MATCH(DMI_PRODUCT_NAME, "Swanky"), 511 }, 512 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 513 }, 514 { 515 /* Winky model Chromebook */ 516 .matches = { 517 DMI_MATCH(DMI_PRODUCT_NAME, "Winky"), 518 }, 519 .driver_data = (void *)QUIRK_PMC_PLT_CLK_0, 520 }, 521 {} 522 }; 523 524 static int snd_cht_mc_probe(struct platform_device *pdev) 525 { 526 const struct dmi_system_id *dmi_id; 527 struct device *dev = &pdev->dev; 528 int ret_val = 0; 529 struct cht_mc_private *drv; 530 const char *mclk_name; 531 struct snd_soc_acpi_mach *mach; 532 const char *platform_name; 533 534 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); 535 if (!drv) 536 return -ENOMEM; 537 538 dmi_id = dmi_first_match(cht_max98090_quirk_table); 539 if (dmi_id) 540 drv->quirks = (unsigned long)dmi_id->driver_data; 541 542 drv->ts3a227e_present = acpi_dev_found("104C227E"); 543 if (!drv->ts3a227e_present) { 544 /* no need probe TI jack detection chip */ 545 snd_soc_card_cht.aux_dev = NULL; 546 snd_soc_card_cht.num_aux_devs = 0; 547 548 ret_val = devm_acpi_dev_add_driver_gpios(dev->parent, 549 acpi_max98090_gpios); 550 if (ret_val) 551 dev_dbg(dev, "Unable to add GPIO mapping table\n"); 552 } 553 554 /* override plaform name, if required */ 555 snd_soc_card_cht.dev = &pdev->dev; 556 mach = pdev->dev.platform_data; 557 platform_name = mach->mach_params.platform; 558 559 ret_val = snd_soc_fixup_dai_links_platform_name(&snd_soc_card_cht, 560 platform_name); 561 if (ret_val) 562 return ret_val; 563 564 /* register the soc card */ 565 snd_soc_card_set_drvdata(&snd_soc_card_cht, drv); 566 567 if (drv->quirks & QUIRK_PMC_PLT_CLK_0) 568 mclk_name = "pmc_plt_clk_0"; 569 else 570 mclk_name = "pmc_plt_clk_3"; 571 572 drv->mclk = devm_clk_get(&pdev->dev, mclk_name); 573 if (IS_ERR(drv->mclk)) { 574 dev_err(&pdev->dev, 575 "Failed to get MCLK from %s: %ld\n", 576 mclk_name, PTR_ERR(drv->mclk)); 577 return PTR_ERR(drv->mclk); 578 } 579 580 /* 581 * Boards which have the MAX98090's clk connected to clk_0 do not seem 582 * to like it if we muck with the clock. If we disable the clock when 583 * it is unused we get "max98090 i2c-193C9890:00: PLL unlocked" errors 584 * and the PLL never seems to lock again. 585 * So for these boards we enable it here once and leave it at that. 586 */ 587 if (drv->quirks & QUIRK_PMC_PLT_CLK_0) { 588 ret_val = clk_prepare_enable(drv->mclk); 589 if (ret_val < 0) { 590 dev_err(&pdev->dev, "MCLK enable error: %d\n", ret_val); 591 return ret_val; 592 } 593 } 594 595 ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht); 596 if (ret_val) { 597 dev_err(&pdev->dev, 598 "snd_soc_register_card failed %d\n", ret_val); 599 return ret_val; 600 } 601 platform_set_drvdata(pdev, &snd_soc_card_cht); 602 return ret_val; 603 } 604 605 static int snd_cht_mc_remove(struct platform_device *pdev) 606 { 607 struct snd_soc_card *card = platform_get_drvdata(pdev); 608 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 609 610 if (ctx->quirks & QUIRK_PMC_PLT_CLK_0) 611 clk_disable_unprepare(ctx->mclk); 612 613 return 0; 614 } 615 616 static struct platform_driver snd_cht_mc_driver = { 617 .driver = { 618 .name = "cht-bsw-max98090", 619 }, 620 .probe = snd_cht_mc_probe, 621 .remove = snd_cht_mc_remove, 622 }; 623 624 module_platform_driver(snd_cht_mc_driver) 625 626 MODULE_DESCRIPTION("ASoC Intel(R) Braswell Machine driver"); 627 MODULE_AUTHOR("Fang, Yang A <yang.a.fang@intel.com>"); 628 MODULE_LICENSE("GPL v2"); 629 MODULE_ALIAS("platform:cht-bsw-max98090"); 630