1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "hdp/hdp_4_0_offset.h" 35 #include "hdp/hdp_4_0_sh_mask.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "dce/dce_12_0_offset.h" 38 #include "dce/dce_12_0_sh_mask.h" 39 #include "vega10_enum.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "athub/athub_1_0_sh_mask.h" 42 #include "athub/athub_1_0_offset.h" 43 #include "oss/osssys_4_0_offset.h" 44 45 #include "soc15.h" 46 #include "soc15d.h" 47 #include "soc15_common.h" 48 #include "umc/umc_6_0_sh_mask.h" 49 50 #include "gfxhub_v1_0.h" 51 #include "mmhub_v1_0.h" 52 #include "athub_v1_0.h" 53 #include "gfxhub_v1_1.h" 54 #include "mmhub_v9_4.h" 55 #include "umc_v6_1.h" 56 #include "umc_v6_0.h" 57 58 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 59 60 #include "amdgpu_ras.h" 61 #include "amdgpu_xgmi.h" 62 63 /* add these here since we already include dce12 headers and these are for DCN */ 64 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 65 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 70 71 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 72 #define AMDGPU_NUM_OF_VMIDS 8 73 74 static const u32 golden_settings_vega10_hdp[] = 75 { 76 0xf64, 0x0fffffff, 0x00000000, 77 0xf65, 0x0fffffff, 0x00000000, 78 0xf66, 0x0fffffff, 0x00000000, 79 0xf67, 0x0fffffff, 0x00000000, 80 0xf68, 0x0fffffff, 0x00000000, 81 0xf6a, 0x0fffffff, 0x00000000, 82 0xf6b, 0x0fffffff, 0x00000000, 83 0xf6c, 0x0fffffff, 0x00000000, 84 0xf6d, 0x0fffffff, 0x00000000, 85 0xf6e, 0x0fffffff, 0x00000000, 86 }; 87 88 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 89 { 90 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 91 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 92 }; 93 94 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 95 { 96 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 97 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 98 }; 99 100 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 101 (0x000143c0 + 0x00000000), 102 (0x000143c0 + 0x00000800), 103 (0x000143c0 + 0x00001000), 104 (0x000143c0 + 0x00001800), 105 (0x000543c0 + 0x00000000), 106 (0x000543c0 + 0x00000800), 107 (0x000543c0 + 0x00001000), 108 (0x000543c0 + 0x00001800), 109 (0x000943c0 + 0x00000000), 110 (0x000943c0 + 0x00000800), 111 (0x000943c0 + 0x00001000), 112 (0x000943c0 + 0x00001800), 113 (0x000d43c0 + 0x00000000), 114 (0x000d43c0 + 0x00000800), 115 (0x000d43c0 + 0x00001000), 116 (0x000d43c0 + 0x00001800), 117 (0x001143c0 + 0x00000000), 118 (0x001143c0 + 0x00000800), 119 (0x001143c0 + 0x00001000), 120 (0x001143c0 + 0x00001800), 121 (0x001543c0 + 0x00000000), 122 (0x001543c0 + 0x00000800), 123 (0x001543c0 + 0x00001000), 124 (0x001543c0 + 0x00001800), 125 (0x001943c0 + 0x00000000), 126 (0x001943c0 + 0x00000800), 127 (0x001943c0 + 0x00001000), 128 (0x001943c0 + 0x00001800), 129 (0x001d43c0 + 0x00000000), 130 (0x001d43c0 + 0x00000800), 131 (0x001d43c0 + 0x00001000), 132 (0x001d43c0 + 0x00001800), 133 }; 134 135 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 136 (0x000143e0 + 0x00000000), 137 (0x000143e0 + 0x00000800), 138 (0x000143e0 + 0x00001000), 139 (0x000143e0 + 0x00001800), 140 (0x000543e0 + 0x00000000), 141 (0x000543e0 + 0x00000800), 142 (0x000543e0 + 0x00001000), 143 (0x000543e0 + 0x00001800), 144 (0x000943e0 + 0x00000000), 145 (0x000943e0 + 0x00000800), 146 (0x000943e0 + 0x00001000), 147 (0x000943e0 + 0x00001800), 148 (0x000d43e0 + 0x00000000), 149 (0x000d43e0 + 0x00000800), 150 (0x000d43e0 + 0x00001000), 151 (0x000d43e0 + 0x00001800), 152 (0x001143e0 + 0x00000000), 153 (0x001143e0 + 0x00000800), 154 (0x001143e0 + 0x00001000), 155 (0x001143e0 + 0x00001800), 156 (0x001543e0 + 0x00000000), 157 (0x001543e0 + 0x00000800), 158 (0x001543e0 + 0x00001000), 159 (0x001543e0 + 0x00001800), 160 (0x001943e0 + 0x00000000), 161 (0x001943e0 + 0x00000800), 162 (0x001943e0 + 0x00001000), 163 (0x001943e0 + 0x00001800), 164 (0x001d43e0 + 0x00000000), 165 (0x001d43e0 + 0x00000800), 166 (0x001d43e0 + 0x00001000), 167 (0x001d43e0 + 0x00001800), 168 }; 169 170 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 171 (0x000143c2 + 0x00000000), 172 (0x000143c2 + 0x00000800), 173 (0x000143c2 + 0x00001000), 174 (0x000143c2 + 0x00001800), 175 (0x000543c2 + 0x00000000), 176 (0x000543c2 + 0x00000800), 177 (0x000543c2 + 0x00001000), 178 (0x000543c2 + 0x00001800), 179 (0x000943c2 + 0x00000000), 180 (0x000943c2 + 0x00000800), 181 (0x000943c2 + 0x00001000), 182 (0x000943c2 + 0x00001800), 183 (0x000d43c2 + 0x00000000), 184 (0x000d43c2 + 0x00000800), 185 (0x000d43c2 + 0x00001000), 186 (0x000d43c2 + 0x00001800), 187 (0x001143c2 + 0x00000000), 188 (0x001143c2 + 0x00000800), 189 (0x001143c2 + 0x00001000), 190 (0x001143c2 + 0x00001800), 191 (0x001543c2 + 0x00000000), 192 (0x001543c2 + 0x00000800), 193 (0x001543c2 + 0x00001000), 194 (0x001543c2 + 0x00001800), 195 (0x001943c2 + 0x00000000), 196 (0x001943c2 + 0x00000800), 197 (0x001943c2 + 0x00001000), 198 (0x001943c2 + 0x00001800), 199 (0x001d43c2 + 0x00000000), 200 (0x001d43c2 + 0x00000800), 201 (0x001d43c2 + 0x00001000), 202 (0x001d43c2 + 0x00001800), 203 }; 204 205 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 206 struct amdgpu_irq_src *src, 207 unsigned type, 208 enum amdgpu_interrupt_state state) 209 { 210 u32 bits, i, tmp, reg; 211 212 /* Devices newer then VEGA10/12 shall have these programming 213 sequences performed by PSP BL */ 214 if (adev->asic_type >= CHIP_VEGA20) 215 return 0; 216 217 bits = 0x7f; 218 219 switch (state) { 220 case AMDGPU_IRQ_STATE_DISABLE: 221 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 222 reg = ecc_umc_mcumc_ctrl_addrs[i]; 223 tmp = RREG32(reg); 224 tmp &= ~bits; 225 WREG32(reg, tmp); 226 } 227 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 228 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 229 tmp = RREG32(reg); 230 tmp &= ~bits; 231 WREG32(reg, tmp); 232 } 233 break; 234 case AMDGPU_IRQ_STATE_ENABLE: 235 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 236 reg = ecc_umc_mcumc_ctrl_addrs[i]; 237 tmp = RREG32(reg); 238 tmp |= bits; 239 WREG32(reg, tmp); 240 } 241 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 242 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 243 tmp = RREG32(reg); 244 tmp |= bits; 245 WREG32(reg, tmp); 246 } 247 break; 248 default: 249 break; 250 } 251 252 return 0; 253 } 254 255 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 256 struct amdgpu_irq_src *src, 257 unsigned type, 258 enum amdgpu_interrupt_state state) 259 { 260 struct amdgpu_vmhub *hub; 261 u32 tmp, reg, bits, i, j; 262 263 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 264 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 265 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 266 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 267 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 268 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 269 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 270 271 switch (state) { 272 case AMDGPU_IRQ_STATE_DISABLE: 273 for (j = 0; j < adev->num_vmhubs; j++) { 274 hub = &adev->vmhub[j]; 275 for (i = 0; i < 16; i++) { 276 reg = hub->vm_context0_cntl + i; 277 tmp = RREG32(reg); 278 tmp &= ~bits; 279 WREG32(reg, tmp); 280 } 281 } 282 break; 283 case AMDGPU_IRQ_STATE_ENABLE: 284 for (j = 0; j < adev->num_vmhubs; j++) { 285 hub = &adev->vmhub[j]; 286 for (i = 0; i < 16; i++) { 287 reg = hub->vm_context0_cntl + i; 288 tmp = RREG32(reg); 289 tmp |= bits; 290 WREG32(reg, tmp); 291 } 292 } 293 default: 294 break; 295 } 296 297 return 0; 298 } 299 300 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 301 struct amdgpu_irq_src *source, 302 struct amdgpu_iv_entry *entry) 303 { 304 struct amdgpu_vmhub *hub; 305 bool retry_fault = !!(entry->src_data[1] & 0x80); 306 uint32_t status = 0; 307 u64 addr; 308 char hub_name[10]; 309 310 addr = (u64)entry->src_data[0] << 12; 311 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 312 313 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 314 entry->timestamp)) 315 return 1; /* This also prevents sending it to KFD */ 316 317 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 318 snprintf(hub_name, sizeof(hub_name), "mmhub0"); 319 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 320 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 321 snprintf(hub_name, sizeof(hub_name), "mmhub1"); 322 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 323 } else { 324 snprintf(hub_name, sizeof(hub_name), "gfxhub0"); 325 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 326 } 327 328 /* If it's the first fault for this address, process it normally */ 329 if (retry_fault && !in_interrupt() && 330 amdgpu_vm_handle_fault(adev, entry->pasid, addr)) 331 return 1; /* This also prevents sending it to KFD */ 332 333 if (!amdgpu_sriov_vf(adev)) { 334 /* 335 * Issue a dummy read to wait for the status register to 336 * be updated to avoid reading an incorrect value due to 337 * the new fast GRBM interface. 338 */ 339 if (entry->vmid_src == AMDGPU_GFXHUB_0) 340 RREG32(hub->vm_l2_pro_fault_status); 341 342 status = RREG32(hub->vm_l2_pro_fault_status); 343 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 344 } 345 346 if (printk_ratelimit()) { 347 struct amdgpu_task_info task_info; 348 349 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 350 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 351 352 dev_err(adev->dev, 353 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 354 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 355 hub_name, retry_fault ? "retry" : "no-retry", 356 entry->src_id, entry->ring_id, entry->vmid, 357 entry->pasid, task_info.process_name, task_info.tgid, 358 task_info.task_name, task_info.pid); 359 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 360 addr, entry->client_id); 361 if (!amdgpu_sriov_vf(adev)) { 362 dev_err(adev->dev, 363 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 364 status); 365 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 366 REG_GET_FIELD(status, 367 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 368 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 369 REG_GET_FIELD(status, 370 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 371 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 372 REG_GET_FIELD(status, 373 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 374 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 375 REG_GET_FIELD(status, 376 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 377 dev_err(adev->dev, "\t RW: 0x%lx\n", 378 REG_GET_FIELD(status, 379 VM_L2_PROTECTION_FAULT_STATUS, RW)); 380 381 } 382 } 383 384 return 0; 385 } 386 387 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 388 .set = gmc_v9_0_vm_fault_interrupt_state, 389 .process = gmc_v9_0_process_interrupt, 390 }; 391 392 393 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 394 .set = gmc_v9_0_ecc_interrupt_state, 395 .process = amdgpu_umc_process_ecc_irq, 396 }; 397 398 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 399 { 400 adev->gmc.vm_fault.num_types = 1; 401 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 402 403 if (!amdgpu_sriov_vf(adev)) { 404 adev->gmc.ecc_irq.num_types = 1; 405 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 406 } 407 } 408 409 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 410 uint32_t flush_type) 411 { 412 u32 req = 0; 413 414 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 415 PER_VMID_INVALIDATE_REQ, 1 << vmid); 416 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 417 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 418 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 419 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 420 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 421 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 422 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 423 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 424 425 return req; 426 } 427 428 /** 429 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 430 * 431 * @adev: amdgpu_device pointer 432 * @vmhub: vmhub type 433 * 434 */ 435 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 436 uint32_t vmhub) 437 { 438 return ((vmhub == AMDGPU_MMHUB_0 || 439 vmhub == AMDGPU_MMHUB_1) && 440 (!amdgpu_sriov_vf(adev)) && 441 (!(adev->asic_type == CHIP_RAVEN && 442 adev->rev_id < 0x8 && 443 adev->pdev->device == 0x15d8))); 444 } 445 446 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 447 uint8_t vmid, uint16_t *p_pasid) 448 { 449 uint32_t value; 450 451 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 452 + vmid); 453 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 454 455 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 456 } 457 458 /* 459 * GART 460 * VMID 0 is the physical GPU addresses as used by the kernel. 461 * VMIDs 1-15 are used for userspace clients and are handled 462 * by the amdgpu vm/hsa code. 463 */ 464 465 /** 466 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 467 * 468 * @adev: amdgpu_device pointer 469 * @vmid: vm instance to flush 470 * @flush_type: the flush type 471 * 472 * Flush the TLB for the requested page table using certain type. 473 */ 474 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 475 uint32_t vmhub, uint32_t flush_type) 476 { 477 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 478 const unsigned eng = 17; 479 u32 j, inv_req, tmp; 480 struct amdgpu_vmhub *hub; 481 482 BUG_ON(vmhub >= adev->num_vmhubs); 483 484 hub = &adev->vmhub[vmhub]; 485 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 486 487 /* This is necessary for a HW workaround under SRIOV as well 488 * as GFXOFF under bare metal 489 */ 490 if (adev->gfx.kiq.ring.sched.ready && 491 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 492 !adev->in_gpu_reset) { 493 uint32_t req = hub->vm_inv_eng0_req + eng; 494 uint32_t ack = hub->vm_inv_eng0_ack + eng; 495 496 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 497 1 << vmid); 498 return; 499 } 500 501 spin_lock(&adev->gmc.invalidate_lock); 502 503 /* 504 * It may lose gpuvm invalidate acknowldege state across power-gating 505 * off cycle, add semaphore acquire before invalidation and semaphore 506 * release after invalidation to avoid entering power gated state 507 * to WA the Issue 508 */ 509 510 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 511 if (use_semaphore) { 512 for (j = 0; j < adev->usec_timeout; j++) { 513 /* a read return value of 1 means semaphore acuqire */ 514 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); 515 if (tmp & 0x1) 516 break; 517 udelay(1); 518 } 519 520 if (j >= adev->usec_timeout) 521 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 522 } 523 524 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req); 525 526 /* 527 * Issue a dummy read to wait for the ACK register to be cleared 528 * to avoid a false ACK due to the new fast GRBM interface. 529 */ 530 if (vmhub == AMDGPU_GFXHUB_0) 531 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 532 533 for (j = 0; j < adev->usec_timeout; j++) { 534 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 535 if (tmp & (1 << vmid)) 536 break; 537 udelay(1); 538 } 539 540 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 541 if (use_semaphore) 542 /* 543 * add semaphore release after invalidation, 544 * write with 0 means semaphore release 545 */ 546 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0); 547 548 spin_unlock(&adev->gmc.invalidate_lock); 549 550 if (j < adev->usec_timeout) 551 return; 552 553 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 554 } 555 556 /** 557 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 558 * 559 * @adev: amdgpu_device pointer 560 * @pasid: pasid to be flush 561 * 562 * Flush the TLB for the requested pasid. 563 */ 564 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 565 uint16_t pasid, uint32_t flush_type, 566 bool all_hub) 567 { 568 int vmid, i; 569 signed long r; 570 uint32_t seq; 571 uint16_t queried_pasid; 572 bool ret; 573 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 574 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 575 576 if (adev->in_gpu_reset) 577 return -EIO; 578 579 if (ring->sched.ready) { 580 spin_lock(&adev->gfx.kiq.ring_lock); 581 /* 2 dwords flush + 8 dwords fence */ 582 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 583 kiq->pmf->kiq_invalidate_tlbs(ring, 584 pasid, flush_type, all_hub); 585 amdgpu_fence_emit_polling(ring, &seq); 586 amdgpu_ring_commit(ring); 587 spin_unlock(&adev->gfx.kiq.ring_lock); 588 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 589 if (r < 1) { 590 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 591 return -ETIME; 592 } 593 594 return 0; 595 } 596 597 for (vmid = 1; vmid < 16; vmid++) { 598 599 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 600 &queried_pasid); 601 if (ret && queried_pasid == pasid) { 602 if (all_hub) { 603 for (i = 0; i < adev->num_vmhubs; i++) 604 gmc_v9_0_flush_gpu_tlb(adev, vmid, 605 i, flush_type); 606 } else { 607 gmc_v9_0_flush_gpu_tlb(adev, vmid, 608 AMDGPU_GFXHUB_0, flush_type); 609 } 610 break; 611 } 612 } 613 614 return 0; 615 616 } 617 618 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 619 unsigned vmid, uint64_t pd_addr) 620 { 621 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 622 struct amdgpu_device *adev = ring->adev; 623 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 624 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 625 unsigned eng = ring->vm_inv_eng; 626 627 /* 628 * It may lose gpuvm invalidate acknowldege state across power-gating 629 * off cycle, add semaphore acquire before invalidation and semaphore 630 * release after invalidation to avoid entering power gated state 631 * to WA the Issue 632 */ 633 634 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 635 if (use_semaphore) 636 /* a read return value of 1 means semaphore acuqire */ 637 amdgpu_ring_emit_reg_wait(ring, 638 hub->vm_inv_eng0_sem + eng, 0x1, 0x1); 639 640 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 641 lower_32_bits(pd_addr)); 642 643 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 644 upper_32_bits(pd_addr)); 645 646 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 647 hub->vm_inv_eng0_ack + eng, 648 req, 1 << vmid); 649 650 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 651 if (use_semaphore) 652 /* 653 * add semaphore release after invalidation, 654 * write with 0 means semaphore release 655 */ 656 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); 657 658 return pd_addr; 659 } 660 661 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 662 unsigned pasid) 663 { 664 struct amdgpu_device *adev = ring->adev; 665 uint32_t reg; 666 667 /* Do nothing because there's no lut register for mmhub1. */ 668 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 669 return; 670 671 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 672 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 673 else 674 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 675 676 amdgpu_ring_emit_wreg(ring, reg, pasid); 677 } 678 679 /* 680 * PTE format on VEGA 10: 681 * 63:59 reserved 682 * 58:57 mtype 683 * 56 F 684 * 55 L 685 * 54 P 686 * 53 SW 687 * 52 T 688 * 50:48 reserved 689 * 47:12 4k physical page base address 690 * 11:7 fragment 691 * 6 write 692 * 5 read 693 * 4 exe 694 * 3 Z 695 * 2 snooped 696 * 1 system 697 * 0 valid 698 * 699 * PDE format on VEGA 10: 700 * 63:59 block fragment size 701 * 58:55 reserved 702 * 54 P 703 * 53:48 reserved 704 * 47:6 physical base address of PD or PTE 705 * 5:3 reserved 706 * 2 C 707 * 1 system 708 * 0 valid 709 */ 710 711 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 712 713 { 714 switch (flags) { 715 case AMDGPU_VM_MTYPE_DEFAULT: 716 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 717 case AMDGPU_VM_MTYPE_NC: 718 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 719 case AMDGPU_VM_MTYPE_WC: 720 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 721 case AMDGPU_VM_MTYPE_RW: 722 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 723 case AMDGPU_VM_MTYPE_CC: 724 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 725 case AMDGPU_VM_MTYPE_UC: 726 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 727 default: 728 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 729 } 730 } 731 732 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 733 uint64_t *addr, uint64_t *flags) 734 { 735 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 736 *addr = adev->vm_manager.vram_base_offset + *addr - 737 adev->gmc.vram_start; 738 BUG_ON(*addr & 0xFFFF00000000003FULL); 739 740 if (!adev->gmc.translate_further) 741 return; 742 743 if (level == AMDGPU_VM_PDB1) { 744 /* Set the block fragment size */ 745 if (!(*flags & AMDGPU_PDE_PTE)) 746 *flags |= AMDGPU_PDE_BFS(0x9); 747 748 } else if (level == AMDGPU_VM_PDB0) { 749 if (*flags & AMDGPU_PDE_PTE) 750 *flags &= ~AMDGPU_PDE_PTE; 751 else 752 *flags |= AMDGPU_PTE_TF; 753 } 754 } 755 756 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 757 struct amdgpu_bo_va_mapping *mapping, 758 uint64_t *flags) 759 { 760 *flags &= ~AMDGPU_PTE_EXECUTABLE; 761 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 762 763 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 764 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 765 766 if (mapping->flags & AMDGPU_PTE_PRT) { 767 *flags |= AMDGPU_PTE_PRT; 768 *flags &= ~AMDGPU_PTE_VALID; 769 } 770 771 if (adev->asic_type == CHIP_ARCTURUS && 772 !(*flags & AMDGPU_PTE_SYSTEM) && 773 mapping->bo_va->is_xgmi) 774 *flags |= AMDGPU_PTE_SNOOPED; 775 } 776 777 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 778 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 779 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 780 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 781 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 782 .map_mtype = gmc_v9_0_map_mtype, 783 .get_vm_pde = gmc_v9_0_get_vm_pde, 784 .get_vm_pte = gmc_v9_0_get_vm_pte 785 }; 786 787 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 788 { 789 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 790 } 791 792 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 793 { 794 switch (adev->asic_type) { 795 case CHIP_VEGA10: 796 adev->umc.funcs = &umc_v6_0_funcs; 797 break; 798 case CHIP_VEGA20: 799 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 800 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 801 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 802 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 803 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 804 adev->umc.funcs = &umc_v6_1_funcs; 805 break; 806 case CHIP_ARCTURUS: 807 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 808 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 809 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 810 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 811 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 812 adev->umc.funcs = &umc_v6_1_funcs; 813 break; 814 default: 815 break; 816 } 817 } 818 819 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 820 { 821 switch (adev->asic_type) { 822 case CHIP_VEGA20: 823 adev->mmhub.funcs = &mmhub_v1_0_funcs; 824 break; 825 case CHIP_ARCTURUS: 826 adev->mmhub.funcs = &mmhub_v9_4_funcs; 827 break; 828 default: 829 break; 830 } 831 } 832 833 static int gmc_v9_0_early_init(void *handle) 834 { 835 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 836 837 gmc_v9_0_set_gmc_funcs(adev); 838 gmc_v9_0_set_irq_funcs(adev); 839 gmc_v9_0_set_umc_funcs(adev); 840 gmc_v9_0_set_mmhub_funcs(adev); 841 842 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 843 adev->gmc.shared_aperture_end = 844 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 845 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 846 adev->gmc.private_aperture_end = 847 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 848 849 return 0; 850 } 851 852 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 853 { 854 855 /* 856 * TODO: 857 * Currently there is a bug where some memory client outside 858 * of the driver writes to first 8M of VRAM on S3 resume, 859 * this overrides GART which by default gets placed in first 8M and 860 * causes VM_FAULTS once GTT is accessed. 861 * Keep the stolen memory reservation until the while this is not solved. 862 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 863 */ 864 switch (adev->asic_type) { 865 case CHIP_VEGA10: 866 case CHIP_RAVEN: 867 case CHIP_ARCTURUS: 868 case CHIP_RENOIR: 869 return true; 870 case CHIP_VEGA12: 871 case CHIP_VEGA20: 872 default: 873 return false; 874 } 875 } 876 877 static int gmc_v9_0_late_init(void *handle) 878 { 879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 880 int r; 881 882 if (!gmc_v9_0_keep_stolen_memory(adev)) 883 amdgpu_bo_late_init(adev); 884 885 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 886 if (r) 887 return r; 888 /* Check if ecc is available */ 889 if (!amdgpu_sriov_vf(adev)) { 890 switch (adev->asic_type) { 891 case CHIP_VEGA10: 892 case CHIP_VEGA20: 893 case CHIP_ARCTURUS: 894 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 895 if (!r) { 896 DRM_INFO("ECC is not present.\n"); 897 if (adev->df.funcs->enable_ecc_force_par_wr_rmw) 898 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 899 } else { 900 DRM_INFO("ECC is active.\n"); 901 } 902 903 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 904 if (!r) { 905 DRM_INFO("SRAM ECC is not present.\n"); 906 } else { 907 DRM_INFO("SRAM ECC is active.\n"); 908 } 909 break; 910 default: 911 break; 912 } 913 } 914 915 r = amdgpu_gmc_ras_late_init(adev); 916 if (r) 917 return r; 918 919 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 920 } 921 922 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 923 struct amdgpu_gmc *mc) 924 { 925 u64 base = 0; 926 927 if (adev->asic_type == CHIP_ARCTURUS) 928 base = mmhub_v9_4_get_fb_location(adev); 929 else if (!amdgpu_sriov_vf(adev)) 930 base = mmhub_v1_0_get_fb_location(adev); 931 932 /* add the xgmi offset of the physical node */ 933 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 934 amdgpu_gmc_vram_location(adev, mc, base); 935 amdgpu_gmc_gart_location(adev, mc); 936 amdgpu_gmc_agp_location(adev, mc); 937 /* base offset of vram pages */ 938 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 939 940 /* XXX: add the xgmi offset of the physical node? */ 941 adev->vm_manager.vram_base_offset += 942 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 943 } 944 945 /** 946 * gmc_v9_0_mc_init - initialize the memory controller driver params 947 * 948 * @adev: amdgpu_device pointer 949 * 950 * Look up the amount of vram, vram width, and decide how to place 951 * vram and gart within the GPU's physical address space. 952 * Returns 0 for success. 953 */ 954 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 955 { 956 int r; 957 958 /* size in MB on si */ 959 adev->gmc.mc_vram_size = 960 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 961 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 962 963 if (!(adev->flags & AMD_IS_APU)) { 964 r = amdgpu_device_resize_fb_bar(adev); 965 if (r) 966 return r; 967 } 968 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 969 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 970 971 #ifdef CONFIG_X86_64 972 if (adev->flags & AMD_IS_APU) { 973 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 974 adev->gmc.aper_size = adev->gmc.real_vram_size; 975 } 976 #endif 977 /* In case the PCI BAR is larger than the actual amount of vram */ 978 adev->gmc.visible_vram_size = adev->gmc.aper_size; 979 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 980 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 981 982 /* set the gart size */ 983 if (amdgpu_gart_size == -1) { 984 switch (adev->asic_type) { 985 case CHIP_VEGA10: /* all engines support GPUVM */ 986 case CHIP_VEGA12: /* all engines support GPUVM */ 987 case CHIP_VEGA20: 988 case CHIP_ARCTURUS: 989 default: 990 adev->gmc.gart_size = 512ULL << 20; 991 break; 992 case CHIP_RAVEN: /* DCE SG support */ 993 case CHIP_RENOIR: 994 adev->gmc.gart_size = 1024ULL << 20; 995 break; 996 } 997 } else { 998 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 999 } 1000 1001 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1002 1003 return 0; 1004 } 1005 1006 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1007 { 1008 int r; 1009 1010 if (adev->gart.bo) { 1011 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1012 return 0; 1013 } 1014 /* Initialize common gart structure */ 1015 r = amdgpu_gart_init(adev); 1016 if (r) 1017 return r; 1018 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1019 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1020 AMDGPU_PTE_EXECUTABLE; 1021 return amdgpu_gart_table_vram_alloc(adev); 1022 } 1023 1024 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1025 { 1026 u32 d1vga_control; 1027 unsigned size; 1028 1029 /* 1030 * TODO Remove once GART corruption is resolved 1031 * Check related code in gmc_v9_0_sw_fini 1032 * */ 1033 if (gmc_v9_0_keep_stolen_memory(adev)) 1034 return 9 * 1024 * 1024; 1035 1036 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1037 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1038 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1039 } else { 1040 u32 viewport; 1041 1042 switch (adev->asic_type) { 1043 case CHIP_RAVEN: 1044 case CHIP_RENOIR: 1045 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1046 size = (REG_GET_FIELD(viewport, 1047 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1048 REG_GET_FIELD(viewport, 1049 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1050 4); 1051 break; 1052 case CHIP_VEGA10: 1053 case CHIP_VEGA12: 1054 case CHIP_VEGA20: 1055 default: 1056 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1057 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1058 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1059 4); 1060 break; 1061 } 1062 } 1063 /* return 0 if the pre-OS buffer uses up most of vram */ 1064 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1065 return 0; 1066 1067 return size; 1068 } 1069 1070 static int gmc_v9_0_sw_init(void *handle) 1071 { 1072 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1074 1075 gfxhub_v1_0_init(adev); 1076 if (adev->asic_type == CHIP_ARCTURUS) 1077 mmhub_v9_4_init(adev); 1078 else 1079 mmhub_v1_0_init(adev); 1080 1081 spin_lock_init(&adev->gmc.invalidate_lock); 1082 1083 r = amdgpu_atomfirmware_get_vram_info(adev, 1084 &vram_width, &vram_type, &vram_vendor); 1085 if (amdgpu_sriov_vf(adev)) 1086 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1087 * and DF related registers is not readable, seems hardcord is the 1088 * only way to set the correct vram_width 1089 */ 1090 adev->gmc.vram_width = 2048; 1091 else if (amdgpu_emu_mode != 1) 1092 adev->gmc.vram_width = vram_width; 1093 1094 if (!adev->gmc.vram_width) { 1095 int chansize, numchan; 1096 1097 /* hbm memory channel size */ 1098 if (adev->flags & AMD_IS_APU) 1099 chansize = 64; 1100 else 1101 chansize = 128; 1102 1103 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1104 adev->gmc.vram_width = numchan * chansize; 1105 } 1106 1107 adev->gmc.vram_type = vram_type; 1108 adev->gmc.vram_vendor = vram_vendor; 1109 switch (adev->asic_type) { 1110 case CHIP_RAVEN: 1111 adev->num_vmhubs = 2; 1112 1113 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1114 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1115 } else { 1116 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1117 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1118 adev->gmc.translate_further = 1119 adev->vm_manager.num_level > 1; 1120 } 1121 break; 1122 case CHIP_VEGA10: 1123 case CHIP_VEGA12: 1124 case CHIP_VEGA20: 1125 case CHIP_RENOIR: 1126 adev->num_vmhubs = 2; 1127 1128 1129 /* 1130 * To fulfill 4-level page support, 1131 * vm size is 256TB (48bit), maximum size of Vega10, 1132 * block size 512 (9bit) 1133 */ 1134 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1135 if (amdgpu_sriov_vf(adev)) 1136 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1137 else 1138 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1139 break; 1140 case CHIP_ARCTURUS: 1141 adev->num_vmhubs = 3; 1142 1143 /* Keep the vm size same with Vega20 */ 1144 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1145 break; 1146 default: 1147 break; 1148 } 1149 1150 /* This interrupt is VMC page fault.*/ 1151 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1152 &adev->gmc.vm_fault); 1153 if (r) 1154 return r; 1155 1156 if (adev->asic_type == CHIP_ARCTURUS) { 1157 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1158 &adev->gmc.vm_fault); 1159 if (r) 1160 return r; 1161 } 1162 1163 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1164 &adev->gmc.vm_fault); 1165 1166 if (r) 1167 return r; 1168 1169 if (!amdgpu_sriov_vf(adev)) { 1170 /* interrupt sent to DF. */ 1171 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1172 &adev->gmc.ecc_irq); 1173 if (r) 1174 return r; 1175 } 1176 1177 /* Set the internal MC address mask 1178 * This is the max address of the GPU's 1179 * internal address space. 1180 */ 1181 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1182 1183 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1184 if (r) { 1185 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1186 return r; 1187 } 1188 adev->need_swiotlb = drm_need_swiotlb(44); 1189 1190 if (adev->gmc.xgmi.supported) { 1191 r = gfxhub_v1_1_get_xgmi_info(adev); 1192 if (r) 1193 return r; 1194 } 1195 1196 r = gmc_v9_0_mc_init(adev); 1197 if (r) 1198 return r; 1199 1200 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1201 1202 /* Memory manager */ 1203 r = amdgpu_bo_init(adev); 1204 if (r) 1205 return r; 1206 1207 r = gmc_v9_0_gart_init(adev); 1208 if (r) 1209 return r; 1210 1211 /* 1212 * number of VMs 1213 * VMID 0 is reserved for System 1214 * amdgpu graphics/compute will use VMIDs 1-7 1215 * amdkfd will use VMIDs 8-15 1216 */ 1217 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1218 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1219 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; 1220 1221 amdgpu_vm_manager_init(adev); 1222 1223 return 0; 1224 } 1225 1226 static int gmc_v9_0_sw_fini(void *handle) 1227 { 1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1229 void *stolen_vga_buf; 1230 1231 amdgpu_gmc_ras_fini(adev); 1232 amdgpu_gem_force_release(adev); 1233 amdgpu_vm_manager_fini(adev); 1234 1235 if (gmc_v9_0_keep_stolen_memory(adev)) 1236 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 1237 1238 amdgpu_gart_table_vram_free(adev); 1239 amdgpu_bo_fini(adev); 1240 amdgpu_gart_fini(adev); 1241 1242 return 0; 1243 } 1244 1245 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1246 { 1247 1248 switch (adev->asic_type) { 1249 case CHIP_VEGA10: 1250 if (amdgpu_sriov_vf(adev)) 1251 break; 1252 /* fall through */ 1253 case CHIP_VEGA20: 1254 soc15_program_register_sequence(adev, 1255 golden_settings_mmhub_1_0_0, 1256 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1257 soc15_program_register_sequence(adev, 1258 golden_settings_athub_1_0_0, 1259 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1260 break; 1261 case CHIP_VEGA12: 1262 break; 1263 case CHIP_RAVEN: 1264 /* TODO for renoir */ 1265 soc15_program_register_sequence(adev, 1266 golden_settings_athub_1_0_0, 1267 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1268 break; 1269 default: 1270 break; 1271 } 1272 } 1273 1274 /** 1275 * gmc_v9_0_gart_enable - gart enable 1276 * 1277 * @adev: amdgpu_device pointer 1278 */ 1279 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1280 { 1281 int r; 1282 1283 if (adev->gart.bo == NULL) { 1284 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1285 return -EINVAL; 1286 } 1287 r = amdgpu_gart_table_vram_pin(adev); 1288 if (r) 1289 return r; 1290 1291 r = gfxhub_v1_0_gart_enable(adev); 1292 if (r) 1293 return r; 1294 1295 if (adev->asic_type == CHIP_ARCTURUS) 1296 r = mmhub_v9_4_gart_enable(adev); 1297 else 1298 r = mmhub_v1_0_gart_enable(adev); 1299 if (r) 1300 return r; 1301 1302 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1303 (unsigned)(adev->gmc.gart_size >> 20), 1304 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1305 adev->gart.ready = true; 1306 return 0; 1307 } 1308 1309 static int gmc_v9_0_hw_init(void *handle) 1310 { 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 bool value; 1313 int r, i; 1314 u32 tmp; 1315 1316 /* The sequence of these two function calls matters.*/ 1317 gmc_v9_0_init_golden_registers(adev); 1318 1319 if (adev->mode_info.num_crtc) { 1320 if (adev->asic_type != CHIP_ARCTURUS) { 1321 /* Lockout access through VGA aperture*/ 1322 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1323 1324 /* disable VGA render */ 1325 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1326 } 1327 } 1328 1329 amdgpu_device_program_register_sequence(adev, 1330 golden_settings_vega10_hdp, 1331 ARRAY_SIZE(golden_settings_vega10_hdp)); 1332 1333 switch (adev->asic_type) { 1334 case CHIP_RAVEN: 1335 /* TODO for renoir */ 1336 mmhub_v1_0_update_power_gating(adev, true); 1337 break; 1338 case CHIP_ARCTURUS: 1339 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); 1340 break; 1341 default: 1342 break; 1343 } 1344 1345 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1346 1347 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1348 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1349 1350 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1351 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1352 1353 /* After HDP is initialized, flush HDP.*/ 1354 adev->nbio.funcs->hdp_flush(adev, NULL); 1355 1356 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1357 value = false; 1358 else 1359 value = true; 1360 1361 if (!amdgpu_sriov_vf(adev)) { 1362 gfxhub_v1_0_set_fault_enable_default(adev, value); 1363 if (adev->asic_type == CHIP_ARCTURUS) 1364 mmhub_v9_4_set_fault_enable_default(adev, value); 1365 else 1366 mmhub_v1_0_set_fault_enable_default(adev, value); 1367 } 1368 for (i = 0; i < adev->num_vmhubs; ++i) 1369 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1370 1371 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1372 adev->umc.funcs->init_registers(adev); 1373 1374 r = gmc_v9_0_gart_enable(adev); 1375 1376 return r; 1377 } 1378 1379 /** 1380 * gmc_v9_0_gart_disable - gart disable 1381 * 1382 * @adev: amdgpu_device pointer 1383 * 1384 * This disables all VM page table. 1385 */ 1386 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1387 { 1388 gfxhub_v1_0_gart_disable(adev); 1389 if (adev->asic_type == CHIP_ARCTURUS) 1390 mmhub_v9_4_gart_disable(adev); 1391 else 1392 mmhub_v1_0_gart_disable(adev); 1393 amdgpu_gart_table_vram_unpin(adev); 1394 } 1395 1396 static int gmc_v9_0_hw_fini(void *handle) 1397 { 1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1399 1400 if (amdgpu_sriov_vf(adev)) { 1401 /* full access mode, so don't touch any GMC register */ 1402 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1403 return 0; 1404 } 1405 1406 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1407 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1408 gmc_v9_0_gart_disable(adev); 1409 1410 return 0; 1411 } 1412 1413 static int gmc_v9_0_suspend(void *handle) 1414 { 1415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1416 1417 return gmc_v9_0_hw_fini(adev); 1418 } 1419 1420 static int gmc_v9_0_resume(void *handle) 1421 { 1422 int r; 1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1424 1425 r = gmc_v9_0_hw_init(adev); 1426 if (r) 1427 return r; 1428 1429 amdgpu_vmid_reset_all(adev); 1430 1431 return 0; 1432 } 1433 1434 static bool gmc_v9_0_is_idle(void *handle) 1435 { 1436 /* MC is always ready in GMC v9.*/ 1437 return true; 1438 } 1439 1440 static int gmc_v9_0_wait_for_idle(void *handle) 1441 { 1442 /* There is no need to wait for MC idle in GMC v9.*/ 1443 return 0; 1444 } 1445 1446 static int gmc_v9_0_soft_reset(void *handle) 1447 { 1448 /* XXX for emulation.*/ 1449 return 0; 1450 } 1451 1452 static int gmc_v9_0_set_clockgating_state(void *handle, 1453 enum amd_clockgating_state state) 1454 { 1455 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1456 1457 if (adev->asic_type == CHIP_ARCTURUS) 1458 mmhub_v9_4_set_clockgating(adev, state); 1459 else 1460 mmhub_v1_0_set_clockgating(adev, state); 1461 1462 athub_v1_0_set_clockgating(adev, state); 1463 1464 return 0; 1465 } 1466 1467 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1468 { 1469 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1470 1471 if (adev->asic_type == CHIP_ARCTURUS) 1472 mmhub_v9_4_get_clockgating(adev, flags); 1473 else 1474 mmhub_v1_0_get_clockgating(adev, flags); 1475 1476 athub_v1_0_get_clockgating(adev, flags); 1477 } 1478 1479 static int gmc_v9_0_set_powergating_state(void *handle, 1480 enum amd_powergating_state state) 1481 { 1482 return 0; 1483 } 1484 1485 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1486 .name = "gmc_v9_0", 1487 .early_init = gmc_v9_0_early_init, 1488 .late_init = gmc_v9_0_late_init, 1489 .sw_init = gmc_v9_0_sw_init, 1490 .sw_fini = gmc_v9_0_sw_fini, 1491 .hw_init = gmc_v9_0_hw_init, 1492 .hw_fini = gmc_v9_0_hw_fini, 1493 .suspend = gmc_v9_0_suspend, 1494 .resume = gmc_v9_0_resume, 1495 .is_idle = gmc_v9_0_is_idle, 1496 .wait_for_idle = gmc_v9_0_wait_for_idle, 1497 .soft_reset = gmc_v9_0_soft_reset, 1498 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1499 .set_powergating_state = gmc_v9_0_set_powergating_state, 1500 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1501 }; 1502 1503 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1504 { 1505 .type = AMD_IP_BLOCK_TYPE_GMC, 1506 .major = 9, 1507 .minor = 0, 1508 .rev = 0, 1509 .funcs = &gmc_v9_0_ip_funcs, 1510 }; 1511