1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7180.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/phy/phy-qcom-qusb2.h> 15#include <dt-bindings/power/qcom-aoss-qmp.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 spi0 = &spi0; 44 spi1 = &spi1; 45 spi3 = &spi3; 46 spi5 = &spi5; 47 spi6 = &spi6; 48 spi8 = &spi8; 49 spi10 = &spi10; 50 spi11 = &spi11; 51 }; 52 53 clocks { 54 xo_board: xo-board { 55 compatible = "fixed-clock"; 56 clock-frequency = <38400000>; 57 #clock-cells = <0>; 58 }; 59 60 sleep_clk: sleep-clk { 61 compatible = "fixed-clock"; 62 clock-frequency = <32764>; 63 #clock-cells = <0>; 64 }; 65 }; 66 67 reserved_memory: reserved-memory { 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 72 aop_cmd_db_mem: memory@80820000 { 73 reg = <0x0 0x80820000 0x0 0x20000>; 74 compatible = "qcom,cmd-db"; 75 }; 76 77 smem_mem: memory@80900000 { 78 reg = <0x0 0x80900000 0x0 0x200000>; 79 no-map; 80 }; 81 82 venus_mem: memory@8f600000 { 83 reg = <0 0x8f600000 0 0x500000>; 84 no-map; 85 }; 86 }; 87 88 cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "arm,armv8"; 95 reg = <0x0 0x0>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1024>; 98 dynamic-power-coefficient = <100>; 99 next-level-cache = <&L2_0>; 100 #cooling-cells = <2>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 L2_0: l2-cache { 103 compatible = "cache"; 104 next-level-cache = <&L3_0>; 105 L3_0: l3-cache { 106 compatible = "cache"; 107 }; 108 }; 109 }; 110 111 CPU1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,armv8"; 114 reg = <0x0 0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 next-level-cache = <&L2_100>; 119 #cooling-cells = <2>; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 L2_100: l2-cache { 122 compatible = "cache"; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU2: cpu@200 { 128 device_type = "cpu"; 129 compatible = "arm,armv8"; 130 reg = <0x0 0x200>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <1024>; 133 dynamic-power-coefficient = <100>; 134 next-level-cache = <&L2_200>; 135 #cooling-cells = <2>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 L2_200: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU3: cpu@300 { 144 device_type = "cpu"; 145 compatible = "arm,armv8"; 146 reg = <0x0 0x300>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <1024>; 149 dynamic-power-coefficient = <100>; 150 next-level-cache = <&L2_300>; 151 #cooling-cells = <2>; 152 qcom,freq-domain = <&cpufreq_hw 0>; 153 L2_300: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU4: cpu@400 { 160 device_type = "cpu"; 161 compatible = "arm,armv8"; 162 reg = <0x0 0x400>; 163 enable-method = "psci"; 164 capacity-dmips-mhz = <1024>; 165 dynamic-power-coefficient = <100>; 166 next-level-cache = <&L2_400>; 167 #cooling-cells = <2>; 168 qcom,freq-domain = <&cpufreq_hw 0>; 169 L2_400: l2-cache { 170 compatible = "cache"; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 CPU5: cpu@500 { 176 device_type = "cpu"; 177 compatible = "arm,armv8"; 178 reg = <0x0 0x500>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <100>; 182 next-level-cache = <&L2_500>; 183 #cooling-cells = <2>; 184 qcom,freq-domain = <&cpufreq_hw 0>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,armv8"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 capacity-dmips-mhz = <1740>; 197 dynamic-power-coefficient = <405>; 198 next-level-cache = <&L2_600>; 199 #cooling-cells = <2>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 L2_600: l2-cache { 202 compatible = "cache"; 203 next-level-cache = <&L3_0>; 204 }; 205 }; 206 207 CPU7: cpu@700 { 208 device_type = "cpu"; 209 compatible = "arm,armv8"; 210 reg = <0x0 0x700>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1740>; 213 dynamic-power-coefficient = <405>; 214 next-level-cache = <&L2_700>; 215 #cooling-cells = <2>; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 L2_700: l2-cache { 218 compatible = "cache"; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 cpu-map { 224 cluster0 { 225 core0 { 226 cpu = <&CPU0>; 227 }; 228 229 core1 { 230 cpu = <&CPU1>; 231 }; 232 233 core2 { 234 cpu = <&CPU2>; 235 }; 236 237 core3 { 238 cpu = <&CPU3>; 239 }; 240 241 core4 { 242 cpu = <&CPU4>; 243 }; 244 245 core5 { 246 cpu = <&CPU5>; 247 }; 248 249 core6 { 250 cpu = <&CPU6>; 251 }; 252 253 core7 { 254 cpu = <&CPU7>; 255 }; 256 }; 257 }; 258 }; 259 260 memory@80000000 { 261 device_type = "memory"; 262 /* We expect the bootloader to fill in the size */ 263 reg = <0 0x80000000 0 0>; 264 }; 265 266 pmu { 267 compatible = "arm,armv8-pmuv3"; 268 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 271 firmware { 272 scm { 273 compatible = "qcom,scm-sc7180", "qcom,scm"; 274 }; 275 }; 276 277 tcsr_mutex: hwlock { 278 compatible = "qcom,tcsr-mutex"; 279 syscon = <&tcsr_mutex_regs 0 0x1000>; 280 #hwlock-cells = <1>; 281 }; 282 283 smem { 284 compatible = "qcom,smem"; 285 memory-region = <&smem_mem>; 286 hwlocks = <&tcsr_mutex 3>; 287 }; 288 289 smp2p-cdsp { 290 compatible = "qcom,smp2p"; 291 qcom,smem = <94>, <432>; 292 293 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 294 295 mboxes = <&apss_shared 6>; 296 297 qcom,local-pid = <0>; 298 qcom,remote-pid = <5>; 299 300 cdsp_smp2p_out: master-kernel { 301 qcom,entry-name = "master-kernel"; 302 #qcom,smem-state-cells = <1>; 303 }; 304 305 cdsp_smp2p_in: slave-kernel { 306 qcom,entry-name = "slave-kernel"; 307 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 }; 311 }; 312 313 smp2p-lpass { 314 compatible = "qcom,smp2p"; 315 qcom,smem = <443>, <429>; 316 317 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 318 319 mboxes = <&apss_shared 10>; 320 321 qcom,local-pid = <0>; 322 qcom,remote-pid = <2>; 323 324 adsp_smp2p_out: master-kernel { 325 qcom,entry-name = "master-kernel"; 326 #qcom,smem-state-cells = <1>; 327 }; 328 329 adsp_smp2p_in: slave-kernel { 330 qcom,entry-name = "slave-kernel"; 331 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 }; 336 337 smp2p-mpss { 338 compatible = "qcom,smp2p"; 339 qcom,smem = <435>, <428>; 340 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 341 mboxes = <&apss_shared 14>; 342 qcom,local-pid = <0>; 343 qcom,remote-pid = <1>; 344 345 modem_smp2p_out: master-kernel { 346 qcom,entry-name = "master-kernel"; 347 #qcom,smem-state-cells = <1>; 348 }; 349 350 modem_smp2p_in: slave-kernel { 351 qcom,entry-name = "slave-kernel"; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 }; 355 }; 356 357 psci { 358 compatible = "arm,psci-1.0"; 359 method = "smc"; 360 }; 361 362 soc: soc@0 { 363 #address-cells = <2>; 364 #size-cells = <2>; 365 ranges = <0 0 0 0 0x10 0>; 366 dma-ranges = <0 0 0 0 0x10 0>; 367 compatible = "simple-bus"; 368 369 gcc: clock-controller@100000 { 370 compatible = "qcom,gcc-sc7180"; 371 reg = <0 0x00100000 0 0x1f0000>; 372 clocks = <&rpmhcc RPMH_CXO_CLK>, 373 <&rpmhcc RPMH_CXO_CLK_A>, 374 <&sleep_clk>; 375 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 376 #clock-cells = <1>; 377 #reset-cells = <1>; 378 #power-domain-cells = <1>; 379 }; 380 381 qfprom@784000 { 382 compatible = "qcom,qfprom"; 383 reg = <0 0x00784000 0 0x8ff>; 384 #address-cells = <1>; 385 #size-cells = <1>; 386 387 qusb2p_hstx_trim: hstx-trim-primary@25b { 388 reg = <0x25b 0x1>; 389 bits = <1 3>; 390 }; 391 }; 392 393 sdhc_1: sdhci@7c4000 { 394 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 395 reg = <0 0x7c4000 0 0x1000>, 396 <0 0x07c5000 0 0x1000>; 397 reg-names = "hc", "cqhci"; 398 399 iommus = <&apps_smmu 0x60 0x0>; 400 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "hc_irq", "pwr_irq"; 403 404 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 405 <&gcc GCC_SDCC1_AHB_CLK>; 406 clock-names = "core", "iface"; 407 408 bus-width = <8>; 409 non-removable; 410 supports-cqe; 411 412 mmc-ddr-1_8v; 413 mmc-hs200-1_8v; 414 mmc-hs400-1_8v; 415 mmc-hs400-enhanced-strobe; 416 417 status = "disabled"; 418 }; 419 420 qupv3_id_0: geniqup@8c0000 { 421 compatible = "qcom,geni-se-qup"; 422 reg = <0 0x008c0000 0 0x6000>; 423 clock-names = "m-ahb", "s-ahb"; 424 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 425 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 426 #address-cells = <2>; 427 #size-cells = <2>; 428 ranges; 429 iommus = <&apps_smmu 0x43 0x0>; 430 status = "disabled"; 431 432 i2c0: i2c@880000 { 433 compatible = "qcom,geni-i2c"; 434 reg = <0 0x00880000 0 0x4000>; 435 clock-names = "se"; 436 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&qup_i2c0_default>; 439 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 spi0: spi@880000 { 446 compatible = "qcom,geni-spi"; 447 reg = <0 0x00880000 0 0x4000>; 448 clock-names = "se"; 449 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&qup_spi0_default>; 452 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 uart0: serial@880000 { 459 compatible = "qcom,geni-uart"; 460 reg = <0 0x00880000 0 0x4000>; 461 clock-names = "se"; 462 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&qup_uart0_default>; 465 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 466 status = "disabled"; 467 }; 468 469 i2c1: i2c@884000 { 470 compatible = "qcom,geni-i2c"; 471 reg = <0 0x00884000 0 0x4000>; 472 clock-names = "se"; 473 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&qup_i2c1_default>; 476 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 spi1: spi@884000 { 483 compatible = "qcom,geni-spi"; 484 reg = <0 0x00884000 0 0x4000>; 485 clock-names = "se"; 486 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&qup_spi1_default>; 489 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 status = "disabled"; 493 }; 494 495 uart1: serial@884000 { 496 compatible = "qcom,geni-uart"; 497 reg = <0 0x00884000 0 0x4000>; 498 clock-names = "se"; 499 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&qup_uart1_default>; 502 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 503 status = "disabled"; 504 }; 505 506 i2c2: i2c@888000 { 507 compatible = "qcom,geni-i2c"; 508 reg = <0 0x00888000 0 0x4000>; 509 clock-names = "se"; 510 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&qup_i2c2_default>; 513 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 uart2: serial@888000 { 520 compatible = "qcom,geni-uart"; 521 reg = <0 0x00888000 0 0x4000>; 522 clock-names = "se"; 523 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&qup_uart2_default>; 526 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 527 status = "disabled"; 528 }; 529 530 i2c3: i2c@88c000 { 531 compatible = "qcom,geni-i2c"; 532 reg = <0 0x0088c000 0 0x4000>; 533 clock-names = "se"; 534 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&qup_i2c3_default>; 537 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 spi3: spi@88c000 { 544 compatible = "qcom,geni-spi"; 545 reg = <0 0x0088c000 0 0x4000>; 546 clock-names = "se"; 547 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&qup_spi3_default>; 550 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 uart3: serial@88c000 { 557 compatible = "qcom,geni-uart"; 558 reg = <0 0x0088c000 0 0x4000>; 559 clock-names = "se"; 560 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&qup_uart3_default>; 563 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 564 status = "disabled"; 565 }; 566 567 i2c4: i2c@890000 { 568 compatible = "qcom,geni-i2c"; 569 reg = <0 0x00890000 0 0x4000>; 570 clock-names = "se"; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&qup_i2c4_default>; 574 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 uart4: serial@890000 { 581 compatible = "qcom,geni-uart"; 582 reg = <0 0x00890000 0 0x4000>; 583 clock-names = "se"; 584 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&qup_uart4_default>; 587 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 588 status = "disabled"; 589 }; 590 591 i2c5: i2c@894000 { 592 compatible = "qcom,geni-i2c"; 593 reg = <0 0x00894000 0 0x4000>; 594 clock-names = "se"; 595 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&qup_i2c5_default>; 598 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 spi5: spi@894000 { 605 compatible = "qcom,geni-spi"; 606 reg = <0 0x00894000 0 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&qup_spi5_default>; 611 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 uart5: serial@894000 { 618 compatible = "qcom,geni-uart"; 619 reg = <0 0x00894000 0 0x4000>; 620 clock-names = "se"; 621 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&qup_uart5_default>; 624 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 625 status = "disabled"; 626 }; 627 }; 628 629 qupv3_id_1: geniqup@ac0000 { 630 compatible = "qcom,geni-se-qup"; 631 reg = <0 0x00ac0000 0 0x6000>; 632 clock-names = "m-ahb", "s-ahb"; 633 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 634 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 ranges; 638 iommus = <&apps_smmu 0x4c3 0x0>; 639 status = "disabled"; 640 641 i2c6: i2c@a80000 { 642 compatible = "qcom,geni-i2c"; 643 reg = <0 0x00a80000 0 0x4000>; 644 clock-names = "se"; 645 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&qup_i2c6_default>; 648 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 status = "disabled"; 652 }; 653 654 spi6: spi@a80000 { 655 compatible = "qcom,geni-spi"; 656 reg = <0 0x00a80000 0 0x4000>; 657 clock-names = "se"; 658 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&qup_spi6_default>; 661 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 667 uart6: serial@a80000 { 668 compatible = "qcom,geni-uart"; 669 reg = <0 0x00a80000 0 0x4000>; 670 clock-names = "se"; 671 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&qup_uart6_default>; 674 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 675 status = "disabled"; 676 }; 677 678 i2c7: i2c@a84000 { 679 compatible = "qcom,geni-i2c"; 680 reg = <0 0x00a84000 0 0x4000>; 681 clock-names = "se"; 682 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&qup_i2c7_default>; 685 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 }; 690 691 uart7: serial@a84000 { 692 compatible = "qcom,geni-uart"; 693 reg = <0 0x00a84000 0 0x4000>; 694 clock-names = "se"; 695 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&qup_uart7_default>; 698 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 699 status = "disabled"; 700 }; 701 702 i2c8: i2c@a88000 { 703 compatible = "qcom,geni-i2c"; 704 reg = <0 0x00a88000 0 0x4000>; 705 clock-names = "se"; 706 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 707 pinctrl-names = "default"; 708 pinctrl-0 = <&qup_i2c8_default>; 709 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 spi8: spi@a88000 { 716 compatible = "qcom,geni-spi"; 717 reg = <0 0x00a88000 0 0x4000>; 718 clock-names = "se"; 719 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&qup_spi8_default>; 722 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 status = "disabled"; 726 }; 727 728 uart8: serial@a88000 { 729 compatible = "qcom,geni-debug-uart"; 730 reg = <0 0x00a88000 0 0x4000>; 731 clock-names = "se"; 732 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_uart8_default>; 735 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 736 status = "disabled"; 737 }; 738 739 i2c9: i2c@a8c000 { 740 compatible = "qcom,geni-i2c"; 741 reg = <0 0x00a8c000 0 0x4000>; 742 clock-names = "se"; 743 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&qup_i2c9_default>; 746 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 status = "disabled"; 750 }; 751 752 uart9: serial@a8c000 { 753 compatible = "qcom,geni-uart"; 754 reg = <0 0x00a8c000 0 0x4000>; 755 clock-names = "se"; 756 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&qup_uart9_default>; 759 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 760 status = "disabled"; 761 }; 762 763 i2c10: i2c@a90000 { 764 compatible = "qcom,geni-i2c"; 765 reg = <0 0x00a90000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_i2c10_default>; 770 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 spi10: spi@a90000 { 777 compatible = "qcom,geni-spi"; 778 reg = <0 0x00a90000 0 0x4000>; 779 clock-names = "se"; 780 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&qup_spi10_default>; 783 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 uart10: serial@a90000 { 790 compatible = "qcom,geni-uart"; 791 reg = <0 0x00a90000 0 0x4000>; 792 clock-names = "se"; 793 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&qup_uart10_default>; 796 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 797 status = "disabled"; 798 }; 799 800 i2c11: i2c@a94000 { 801 compatible = "qcom,geni-i2c"; 802 reg = <0 0x00a94000 0 0x4000>; 803 clock-names = "se"; 804 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&qup_i2c11_default>; 807 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 spi11: spi@a94000 { 814 compatible = "qcom,geni-spi"; 815 reg = <0 0x00a94000 0 0x4000>; 816 clock-names = "se"; 817 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 818 pinctrl-names = "default"; 819 pinctrl-0 = <&qup_spi11_default>; 820 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 uart11: serial@a94000 { 827 compatible = "qcom,geni-uart"; 828 reg = <0 0x00a94000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_uart11_default>; 833 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 834 status = "disabled"; 835 }; 836 }; 837 838 config_noc: interconnect@1500000 { 839 compatible = "qcom,sc7180-config-noc"; 840 reg = <0 0x01500000 0 0x28000>; 841 #interconnect-cells = <1>; 842 qcom,bcm-voters = <&apps_bcm_voter>; 843 }; 844 845 system_noc: interconnect@1620000 { 846 compatible = "qcom,sc7180-system-noc"; 847 reg = <0 0x01620000 0 0x17080>; 848 #interconnect-cells = <1>; 849 qcom,bcm-voters = <&apps_bcm_voter>; 850 }; 851 852 mc_virt: interconnect@1638000 { 853 compatible = "qcom,sc7180-mc-virt"; 854 reg = <0 0x01638000 0 0x1000>; 855 #interconnect-cells = <1>; 856 qcom,bcm-voters = <&apps_bcm_voter>; 857 }; 858 859 qup_virt: interconnect@1650000 { 860 compatible = "qcom,sc7180-qup-virt"; 861 reg = <0 0x01650000 0 0x1000>; 862 #interconnect-cells = <1>; 863 qcom,bcm-voters = <&apps_bcm_voter>; 864 }; 865 866 aggre1_noc: interconnect@16e0000 { 867 compatible = "qcom,sc7180-aggre1-noc"; 868 reg = <0 0x016e0000 0 0x15080>; 869 #interconnect-cells = <1>; 870 qcom,bcm-voters = <&apps_bcm_voter>; 871 }; 872 873 aggre2_noc: interconnect@1705000 { 874 compatible = "qcom,sc7180-aggre2-noc"; 875 reg = <0 0x01705000 0 0x9000>; 876 #interconnect-cells = <1>; 877 qcom,bcm-voters = <&apps_bcm_voter>; 878 }; 879 880 compute_noc: interconnect@170e000 { 881 compatible = "qcom,sc7180-compute-noc"; 882 reg = <0 0x0170e000 0 0x6000>; 883 #interconnect-cells = <1>; 884 qcom,bcm-voters = <&apps_bcm_voter>; 885 }; 886 887 mmss_noc: interconnect@1740000 { 888 compatible = "qcom,sc7180-mmss-noc"; 889 reg = <0 0x01740000 0 0x1c100>; 890 #interconnect-cells = <1>; 891 qcom,bcm-voters = <&apps_bcm_voter>; 892 }; 893 894 ipa_virt: interconnect@1e00000 { 895 compatible = "qcom,sc7180-ipa-virt"; 896 reg = <0 0x01e00000 0 0x1000>; 897 #interconnect-cells = <1>; 898 qcom,bcm-voters = <&apps_bcm_voter>; 899 }; 900 901 tcsr_mutex_regs: syscon@1f40000 { 902 compatible = "syscon"; 903 reg = <0 0x01f40000 0 0x40000>; 904 }; 905 906 tlmm: pinctrl@3500000 { 907 compatible = "qcom,sc7180-pinctrl"; 908 reg = <0 0x03500000 0 0x300000>, 909 <0 0x03900000 0 0x300000>, 910 <0 0x03d00000 0 0x300000>; 911 reg-names = "west", "north", "south"; 912 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 913 gpio-controller; 914 #gpio-cells = <2>; 915 interrupt-controller; 916 #interrupt-cells = <2>; 917 gpio-ranges = <&tlmm 0 0 120>; 918 wakeup-parent = <&pdc>; 919 920 qspi_clk: qspi-clk { 921 pinmux { 922 pins = "gpio63"; 923 function = "qspi_clk"; 924 }; 925 }; 926 927 qspi_cs0: qspi-cs0 { 928 pinmux { 929 pins = "gpio68"; 930 function = "qspi_cs"; 931 }; 932 }; 933 934 qspi_cs1: qspi-cs1 { 935 pinmux { 936 pins = "gpio72"; 937 function = "qspi_cs"; 938 }; 939 }; 940 941 qspi_data01: qspi-data01 { 942 pinmux-data { 943 pins = "gpio64", "gpio65"; 944 function = "qspi_data"; 945 }; 946 }; 947 948 qspi_data12: qspi-data12 { 949 pinmux-data { 950 pins = "gpio66", "gpio67"; 951 function = "qspi_data"; 952 }; 953 }; 954 955 qup_i2c0_default: qup-i2c0-default { 956 pinmux { 957 pins = "gpio34", "gpio35"; 958 function = "qup00"; 959 }; 960 }; 961 962 qup_i2c1_default: qup-i2c1-default { 963 pinmux { 964 pins = "gpio0", "gpio1"; 965 function = "qup01"; 966 }; 967 }; 968 969 qup_i2c2_default: qup-i2c2-default { 970 pinmux { 971 pins = "gpio15", "gpio16"; 972 function = "qup02_i2c"; 973 }; 974 }; 975 976 qup_i2c3_default: qup-i2c3-default { 977 pinmux { 978 pins = "gpio38", "gpio39"; 979 function = "qup03"; 980 }; 981 }; 982 983 qup_i2c4_default: qup-i2c4-default { 984 pinmux { 985 pins = "gpio115", "gpio116"; 986 function = "qup04_i2c"; 987 }; 988 }; 989 990 qup_i2c5_default: qup-i2c5-default { 991 pinmux { 992 pins = "gpio25", "gpio26"; 993 function = "qup05"; 994 }; 995 }; 996 997 qup_i2c6_default: qup-i2c6-default { 998 pinmux { 999 pins = "gpio59", "gpio60"; 1000 function = "qup10"; 1001 }; 1002 }; 1003 1004 qup_i2c7_default: qup-i2c7-default { 1005 pinmux { 1006 pins = "gpio6", "gpio7"; 1007 function = "qup11_i2c"; 1008 }; 1009 }; 1010 1011 qup_i2c8_default: qup-i2c8-default { 1012 pinmux { 1013 pins = "gpio42", "gpio43"; 1014 function = "qup12"; 1015 }; 1016 }; 1017 1018 qup_i2c9_default: qup-i2c9-default { 1019 pinmux { 1020 pins = "gpio46", "gpio47"; 1021 function = "qup13_i2c"; 1022 }; 1023 }; 1024 1025 qup_i2c10_default: qup-i2c10-default { 1026 pinmux { 1027 pins = "gpio86", "gpio87"; 1028 function = "qup14"; 1029 }; 1030 }; 1031 1032 qup_i2c11_default: qup-i2c11-default { 1033 pinmux { 1034 pins = "gpio53", "gpio54"; 1035 function = "qup15"; 1036 }; 1037 }; 1038 1039 qup_spi0_default: qup-spi0-default { 1040 pinmux { 1041 pins = "gpio34", "gpio35", 1042 "gpio36", "gpio37"; 1043 function = "qup00"; 1044 }; 1045 }; 1046 1047 qup_spi1_default: qup-spi1-default { 1048 pinmux { 1049 pins = "gpio0", "gpio1", 1050 "gpio2", "gpio3"; 1051 function = "qup01"; 1052 }; 1053 }; 1054 1055 qup_spi3_default: qup-spi3-default { 1056 pinmux { 1057 pins = "gpio38", "gpio39", 1058 "gpio40", "gpio41"; 1059 function = "qup03"; 1060 }; 1061 }; 1062 1063 qup_spi5_default: qup-spi5-default { 1064 pinmux { 1065 pins = "gpio25", "gpio26", 1066 "gpio27", "gpio28"; 1067 function = "qup05"; 1068 }; 1069 }; 1070 1071 qup_spi6_default: qup-spi6-default { 1072 pinmux { 1073 pins = "gpio59", "gpio60", 1074 "gpio61", "gpio62"; 1075 function = "qup10"; 1076 }; 1077 }; 1078 1079 qup_spi8_default: qup-spi8-default { 1080 pinmux { 1081 pins = "gpio42", "gpio43", 1082 "gpio44", "gpio45"; 1083 function = "qup12"; 1084 }; 1085 }; 1086 1087 qup_spi10_default: qup-spi10-default { 1088 pinmux { 1089 pins = "gpio86", "gpio87", 1090 "gpio88", "gpio89"; 1091 function = "qup14"; 1092 }; 1093 }; 1094 1095 qup_spi11_default: qup-spi11-default { 1096 pinmux { 1097 pins = "gpio53", "gpio54", 1098 "gpio55", "gpio56"; 1099 function = "qup15"; 1100 }; 1101 }; 1102 1103 qup_uart0_default: qup-uart0-default { 1104 pinmux { 1105 pins = "gpio34", "gpio35", 1106 "gpio36", "gpio37"; 1107 function = "qup00"; 1108 }; 1109 }; 1110 1111 qup_uart1_default: qup-uart1-default { 1112 pinmux { 1113 pins = "gpio0", "gpio1", 1114 "gpio2", "gpio3"; 1115 function = "qup01"; 1116 }; 1117 }; 1118 1119 qup_uart2_default: qup-uart2-default { 1120 pinmux { 1121 pins = "gpio15", "gpio16"; 1122 function = "qup02_uart"; 1123 }; 1124 }; 1125 1126 qup_uart3_default: qup-uart3-default { 1127 pinmux { 1128 pins = "gpio38", "gpio39", 1129 "gpio40", "gpio41"; 1130 function = "qup03"; 1131 }; 1132 }; 1133 1134 qup_uart4_default: qup-uart4-default { 1135 pinmux { 1136 pins = "gpio115", "gpio116"; 1137 function = "qup04_uart"; 1138 }; 1139 }; 1140 1141 qup_uart5_default: qup-uart5-default { 1142 pinmux { 1143 pins = "gpio25", "gpio26", 1144 "gpio27", "gpio28"; 1145 function = "qup05"; 1146 }; 1147 }; 1148 1149 qup_uart6_default: qup-uart6-default { 1150 pinmux { 1151 pins = "gpio59", "gpio60", 1152 "gpio61", "gpio62"; 1153 function = "qup10"; 1154 }; 1155 }; 1156 1157 qup_uart7_default: qup-uart7-default { 1158 pinmux { 1159 pins = "gpio6", "gpio7"; 1160 function = "qup11_uart"; 1161 }; 1162 }; 1163 1164 qup_uart8_default: qup-uart8-default { 1165 pinmux { 1166 pins = "gpio44", "gpio45"; 1167 function = "qup12"; 1168 }; 1169 }; 1170 1171 qup_uart9_default: qup-uart9-default { 1172 pinmux { 1173 pins = "gpio46", "gpio47"; 1174 function = "qup13_uart"; 1175 }; 1176 }; 1177 1178 qup_uart10_default: qup-uart10-default { 1179 pinmux { 1180 pins = "gpio86", "gpio87", 1181 "gpio88", "gpio89"; 1182 function = "qup14"; 1183 }; 1184 }; 1185 1186 qup_uart11_default: qup-uart11-default { 1187 pinmux { 1188 pins = "gpio53", "gpio54", 1189 "gpio55", "gpio56"; 1190 function = "qup15"; 1191 }; 1192 }; 1193 1194 sdc1_on: sdc1-on { 1195 pinconf-clk { 1196 pins = "sdc1_clk"; 1197 bias-disable; 1198 drive-strength = <16>; 1199 }; 1200 1201 pinconf-cmd { 1202 pins = "sdc1_cmd"; 1203 bias-pull-up; 1204 drive-strength = <10>; 1205 }; 1206 1207 pinconf-data { 1208 pins = "sdc1_data"; 1209 bias-pull-up; 1210 drive-strength = <10>; 1211 }; 1212 1213 pinconf-rclk { 1214 pins = "sdc1_rclk"; 1215 bias-pull-down; 1216 }; 1217 }; 1218 1219 sdc1_off: sdc1-off { 1220 pinconf-clk { 1221 pins = "sdc1_clk"; 1222 bias-disable; 1223 drive-strength = <2>; 1224 }; 1225 1226 pinconf-cmd { 1227 pins = "sdc1_cmd"; 1228 bias-pull-up; 1229 drive-strength = <2>; 1230 }; 1231 1232 pinconf-data { 1233 pins = "sdc1_data"; 1234 bias-pull-up; 1235 drive-strength = <2>; 1236 }; 1237 1238 pinconf-rclk { 1239 pins = "sdc1_rclk"; 1240 bias-pull-down; 1241 }; 1242 }; 1243 1244 sdc2_on: sdc2-on { 1245 pinconf-clk { 1246 pins = "sdc2_clk"; 1247 bias-disable; 1248 drive-strength = <16>; 1249 }; 1250 1251 pinconf-cmd { 1252 pins = "sdc2_cmd"; 1253 bias-pull-up; 1254 drive-strength = <10>; 1255 }; 1256 1257 pinconf-data { 1258 pins = "sdc2_data"; 1259 bias-pull-up; 1260 drive-strength = <10>; 1261 }; 1262 1263 pinconf-sd-cd { 1264 pins = "gpio69"; 1265 bias-pull-up; 1266 drive-strength = <2>; 1267 }; 1268 }; 1269 1270 sdc2_off: sdc2-off { 1271 pinconf-clk { 1272 pins = "sdc2_clk"; 1273 bias-disable; 1274 drive-strength = <2>; 1275 }; 1276 1277 pinconf-cmd { 1278 pins = "sdc2_cmd"; 1279 bias-pull-up; 1280 drive-strength = <2>; 1281 }; 1282 1283 pinconf-data { 1284 pins = "sdc2_data"; 1285 bias-pull-up; 1286 drive-strength = <2>; 1287 }; 1288 1289 pinconf-sd-cd { 1290 pins = "gpio69"; 1291 bias-disable; 1292 drive-strength = <2>; 1293 }; 1294 }; 1295 }; 1296 1297 sdhc_2: sdhci@8804000 { 1298 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 1299 reg = <0 0x08804000 0 0x1000>; 1300 1301 iommus = <&apps_smmu 0x80 0>; 1302 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1304 interrupt-names = "hc_irq", "pwr_irq"; 1305 1306 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1307 <&gcc GCC_SDCC2_AHB_CLK>; 1308 clock-names = "core", "iface"; 1309 1310 bus-width = <4>; 1311 1312 status = "disabled"; 1313 }; 1314 1315 gpucc: clock-controller@5090000 { 1316 compatible = "qcom,sc7180-gpucc"; 1317 reg = <0 0x05090000 0 0x9000>; 1318 clocks = <&rpmhcc RPMH_CXO_CLK>, 1319 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1320 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1321 clock-names = "bi_tcxo", 1322 "gcc_gpu_gpll0_clk_src", 1323 "gcc_gpu_gpll0_div_clk_src"; 1324 #clock-cells = <1>; 1325 #reset-cells = <1>; 1326 #power-domain-cells = <1>; 1327 }; 1328 1329 qspi: spi@88dc000 { 1330 compatible = "qcom,qspi-v1"; 1331 reg = <0 0x088dc000 0 0x600>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1336 <&gcc GCC_QSPI_CORE_CLK>; 1337 clock-names = "iface", "core"; 1338 status = "disabled"; 1339 }; 1340 1341 usb_1_hsphy: phy@88e3000 { 1342 compatible = "qcom,sc7180-qusb2-phy"; 1343 reg = <0 0x088e3000 0 0x400>; 1344 status = "disabled"; 1345 #phy-cells = <0>; 1346 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1347 <&rpmhcc RPMH_CXO_CLK>; 1348 clock-names = "cfg_ahb", "ref"; 1349 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1350 1351 nvmem-cells = <&qusb2p_hstx_trim>; 1352 }; 1353 1354 usb_1_qmpphy: phy-wrapper@88e9000 { 1355 compatible = "qcom,sc7180-qmp-usb3-phy"; 1356 reg = <0 0x088e9000 0 0x18c>, 1357 <0 0x088e8000 0 0x38>; 1358 reg-names = "reg-base", "dp_com"; 1359 status = "disabled"; 1360 #clock-cells = <1>; 1361 #address-cells = <2>; 1362 #size-cells = <2>; 1363 ranges; 1364 1365 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1366 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1367 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1368 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1369 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1370 1371 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1372 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1373 reset-names = "phy", "common"; 1374 1375 usb_1_ssphy: phy@88e9200 { 1376 reg = <0 0x088e9200 0 0x128>, 1377 <0 0x088e9400 0 0x200>, 1378 <0 0x088e9c00 0 0x218>, 1379 <0 0x088e9600 0 0x128>, 1380 <0 0x088e9800 0 0x200>, 1381 <0 0x088e9a00 0 0x18>; 1382 #clock-cells = <0>; 1383 #phy-cells = <0>; 1384 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1385 clock-names = "pipe0"; 1386 clock-output-names = "usb3_phy_pipe_clk_src"; 1387 }; 1388 }; 1389 1390 dc_noc: interconnect@9160000 { 1391 compatible = "qcom,sc7180-dc-noc"; 1392 reg = <0 0x09160000 0 0x03200>; 1393 #interconnect-cells = <1>; 1394 qcom,bcm-voters = <&apps_bcm_voter>; 1395 }; 1396 1397 system-cache-controller@9200000 { 1398 compatible = "qcom,sc7180-llcc"; 1399 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1400 reg-names = "llcc_base", "llcc_broadcast_base"; 1401 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1402 }; 1403 1404 gem_noc: interconnect@9680000 { 1405 compatible = "qcom,sc7180-gem-noc"; 1406 reg = <0 0x09680000 0 0x3e200>; 1407 #interconnect-cells = <1>; 1408 qcom,bcm-voters = <&apps_bcm_voter>; 1409 }; 1410 1411 npu_noc: interconnect@9990000 { 1412 compatible = "qcom,sc7180-npu-noc"; 1413 reg = <0 0x09990000 0 0x1600>; 1414 #interconnect-cells = <1>; 1415 qcom,bcm-voters = <&apps_bcm_voter>; 1416 }; 1417 1418 usb_1: usb@a6f8800 { 1419 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 1420 reg = <0 0x0a6f8800 0 0x400>; 1421 status = "disabled"; 1422 #address-cells = <2>; 1423 #size-cells = <2>; 1424 ranges; 1425 dma-ranges; 1426 1427 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1428 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1429 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1430 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1431 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1432 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1433 "sleep"; 1434 1435 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1436 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1437 assigned-clock-rates = <19200000>, <150000000>; 1438 1439 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1443 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1444 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1445 1446 power-domains = <&gcc USB30_PRIM_GDSC>; 1447 1448 resets = <&gcc GCC_USB30_PRIM_BCR>; 1449 1450 usb_1_dwc3: dwc3@a600000 { 1451 compatible = "snps,dwc3"; 1452 reg = <0 0x0a600000 0 0xe000>; 1453 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1454 iommus = <&apps_smmu 0x540 0>; 1455 snps,dis_u2_susphy_quirk; 1456 snps,dis_enblslpm_quirk; 1457 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1458 phy-names = "usb2-phy", "usb3-phy"; 1459 }; 1460 }; 1461 1462 venus: video-codec@aa00000 { 1463 compatible = "qcom,sc7180-venus"; 1464 reg = <0 0x0aa00000 0 0xff000>; 1465 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&videocc VENUS_GDSC>, 1467 <&videocc VCODEC0_GDSC>; 1468 power-domain-names = "venus", "vcodec0"; 1469 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 1470 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 1471 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 1472 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 1473 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 1474 clock-names = "core", "iface", "bus", 1475 "vcodec0_core", "vcodec0_bus"; 1476 iommus = <&apps_smmu 0x0c00 0x60>; 1477 memory-region = <&venus_mem>; 1478 1479 video-decoder { 1480 compatible = "venus-decoder"; 1481 }; 1482 1483 video-encoder { 1484 compatible = "venus-encoder"; 1485 }; 1486 }; 1487 1488 videocc: clock-controller@ab00000 { 1489 compatible = "qcom,sc7180-videocc"; 1490 reg = <0 0x0ab00000 0 0x10000>; 1491 clocks = <&rpmhcc RPMH_CXO_CLK>; 1492 clock-names = "bi_tcxo"; 1493 #clock-cells = <1>; 1494 #reset-cells = <1>; 1495 #power-domain-cells = <1>; 1496 }; 1497 1498 camnoc_virt: interconnect@ac00000 { 1499 compatible = "qcom,sc7180-camnoc-virt"; 1500 reg = <0 0x0ac00000 0 0x1000>; 1501 #interconnect-cells = <1>; 1502 qcom,bcm-voters = <&apps_bcm_voter>; 1503 }; 1504 1505 mdss: mdss@ae00000 { 1506 compatible = "qcom,sc7180-mdss"; 1507 reg = <0 0x0ae00000 0 0x1000>; 1508 reg-names = "mdss"; 1509 1510 power-domains = <&dispcc MDSS_GDSC>; 1511 1512 clocks = <&gcc GCC_DISP_AHB_CLK>, 1513 <&gcc GCC_DISP_HF_AXI_CLK>, 1514 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1515 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1516 clock-names = "iface", "bus", "ahb", "core"; 1517 1518 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 1519 assigned-clock-rates = <300000000>; 1520 1521 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1522 interrupt-controller; 1523 #interrupt-cells = <1>; 1524 1525 iommus = <&apps_smmu 0x800 0x2>; 1526 1527 #address-cells = <2>; 1528 #size-cells = <2>; 1529 ranges; 1530 1531 status = "disabled"; 1532 1533 mdp: mdp@ae01000 { 1534 compatible = "qcom,sc7180-dpu"; 1535 reg = <0 0x0ae01000 0 0x8f000>, 1536 <0 0x0aeb0000 0 0x2008>; 1537 reg-names = "mdp", "vbif"; 1538 1539 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1540 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1541 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1542 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1543 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1544 clock-names = "iface", "rot", "lut", "core", 1545 "vsync"; 1546 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 1547 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1548 assigned-clock-rates = <300000000>, 1549 <19200000>; 1550 1551 interrupt-parent = <&mdss>; 1552 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1553 1554 status = "disabled"; 1555 1556 ports { 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 1560 port@0 { 1561 reg = <0>; 1562 dpu_intf1_out: endpoint { 1563 remote-endpoint = <&dsi0_in>; 1564 }; 1565 }; 1566 }; 1567 }; 1568 1569 dsi0: dsi@ae94000 { 1570 compatible = "qcom,mdss-dsi-ctrl"; 1571 reg = <0 0x0ae94000 0 0x400>; 1572 reg-names = "dsi_ctrl"; 1573 1574 interrupt-parent = <&mdss>; 1575 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1576 1577 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1578 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1579 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1580 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1581 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1582 <&gcc GCC_DISP_HF_AXI_CLK>; 1583 clock-names = "byte", 1584 "byte_intf", 1585 "pixel", 1586 "core", 1587 "iface", 1588 "bus"; 1589 1590 phys = <&dsi_phy>; 1591 phy-names = "dsi"; 1592 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 1596 status = "disabled"; 1597 1598 ports { 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 1602 port@0 { 1603 reg = <0>; 1604 dsi0_in: endpoint { 1605 remote-endpoint = <&dpu_intf1_out>; 1606 }; 1607 }; 1608 1609 port@1 { 1610 reg = <1>; 1611 dsi0_out: endpoint { 1612 }; 1613 }; 1614 }; 1615 }; 1616 1617 dsi_phy: dsi-phy@ae94400 { 1618 compatible = "qcom,dsi-phy-10nm"; 1619 reg = <0 0x0ae94400 0 0x200>, 1620 <0 0x0ae94600 0 0x280>, 1621 <0 0x0ae94a00 0 0x1e0>; 1622 reg-names = "dsi_phy", 1623 "dsi_phy_lane", 1624 "dsi_pll"; 1625 1626 #clock-cells = <1>; 1627 #phy-cells = <0>; 1628 1629 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1630 <&rpmhcc RPMH_CXO_CLK>; 1631 clock-names = "iface", "ref"; 1632 1633 status = "disabled"; 1634 }; 1635 }; 1636 1637 dispcc: clock-controller@af00000 { 1638 compatible = "qcom,sc7180-dispcc"; 1639 reg = <0 0x0af00000 0 0x200000>; 1640 clocks = <&rpmhcc RPMH_CXO_CLK>, 1641 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1642 <&dsi_phy 0>, 1643 <&dsi_phy 1>, 1644 <0>, 1645 <0>; 1646 clock-names = "bi_tcxo", 1647 "gcc_disp_gpll0_clk_src", 1648 "dsi0_phy_pll_out_byteclk", 1649 "dsi0_phy_pll_out_dsiclk", 1650 "dp_phy_pll_link_clk", 1651 "dp_phy_pll_vco_div_clk"; 1652 #clock-cells = <1>; 1653 #reset-cells = <1>; 1654 #power-domain-cells = <1>; 1655 }; 1656 1657 pdc: interrupt-controller@b220000 { 1658 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 1659 reg = <0 0x0b220000 0 0x30000>; 1660 qcom,pdc-ranges = <0 480 15>, <17 497 98>, 1661 <119 634 4>, <124 639 1>; 1662 #interrupt-cells = <2>; 1663 interrupt-parent = <&intc>; 1664 interrupt-controller; 1665 }; 1666 1667 pdc_reset: reset-controller@b2e0000 { 1668 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 1669 reg = <0 0x0b2e0000 0 0x20000>; 1670 #reset-cells = <1>; 1671 }; 1672 1673 tsens0: thermal-sensor@c263000 { 1674 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 1675 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1676 <0 0x0c222000 0 0x1ff>; /* SROT */ 1677 #qcom,sensors = <15>; 1678 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1680 interrupt-names = "uplow","critical"; 1681 #thermal-sensor-cells = <1>; 1682 }; 1683 1684 tsens1: thermal-sensor@c265000 { 1685 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 1686 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1687 <0 0x0c223000 0 0x1ff>; /* SROT */ 1688 #qcom,sensors = <10>; 1689 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1691 interrupt-names = "uplow","critical"; 1692 #thermal-sensor-cells = <1>; 1693 }; 1694 1695 aoss_reset: reset-controller@c2a0000 { 1696 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 1697 reg = <0 0x0c2a0000 0 0x31000>; 1698 #reset-cells = <1>; 1699 }; 1700 1701 aoss_qmp: qmp@c300000 { 1702 compatible = "qcom,sc7180-aoss-qmp"; 1703 reg = <0 0x0c300000 0 0x100000>; 1704 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 1705 mboxes = <&apss_shared 0>; 1706 1707 #clock-cells = <0>; 1708 #power-domain-cells = <1>; 1709 }; 1710 1711 spmi_bus: spmi@c440000 { 1712 compatible = "qcom,spmi-pmic-arb"; 1713 reg = <0 0x0c440000 0 0x1100>, 1714 <0 0x0c600000 0 0x2000000>, 1715 <0 0x0e600000 0 0x100000>, 1716 <0 0x0e700000 0 0xa0000>, 1717 <0 0x0c40a000 0 0x26000>; 1718 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1719 interrupt-names = "periph_irq"; 1720 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1721 qcom,ee = <0>; 1722 qcom,channel = <0>; 1723 #address-cells = <1>; 1724 #size-cells = <1>; 1725 interrupt-controller; 1726 #interrupt-cells = <4>; 1727 cell-index = <0>; 1728 }; 1729 1730 apps_smmu: iommu@15000000 { 1731 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 1732 reg = <0 0x15000000 0 0x100000>; 1733 #iommu-cells = <2>; 1734 #global-interrupts = <1>; 1735 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 1816 }; 1817 1818 intc: interrupt-controller@17a00000 { 1819 compatible = "arm,gic-v3"; 1820 #address-cells = <2>; 1821 #size-cells = <2>; 1822 ranges; 1823 #interrupt-cells = <3>; 1824 interrupt-controller; 1825 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1826 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1828 1829 msi-controller@17a40000 { 1830 compatible = "arm,gic-v3-its"; 1831 msi-controller; 1832 #msi-cells = <1>; 1833 reg = <0 0x17a40000 0 0x20000>; 1834 status = "disabled"; 1835 }; 1836 }; 1837 1838 apss_shared: mailbox@17c00000 { 1839 compatible = "qcom,sc7180-apss-shared"; 1840 reg = <0 0x17c00000 0 0x10000>; 1841 #mbox-cells = <1>; 1842 }; 1843 1844 watchdog@17c10000 { 1845 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 1846 reg = <0 0x17c10000 0 0x1000>; 1847 clocks = <&sleep_clk>; 1848 }; 1849 1850 timer@17c20000{ 1851 #address-cells = <2>; 1852 #size-cells = <2>; 1853 ranges; 1854 compatible = "arm,armv7-timer-mem"; 1855 reg = <0 0x17c20000 0 0x1000>; 1856 1857 frame@17c21000 { 1858 frame-number = <0>; 1859 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1861 reg = <0 0x17c21000 0 0x1000>, 1862 <0 0x17c22000 0 0x1000>; 1863 }; 1864 1865 frame@17c23000 { 1866 frame-number = <1>; 1867 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1868 reg = <0 0x17c23000 0 0x1000>; 1869 status = "disabled"; 1870 }; 1871 1872 frame@17c25000 { 1873 frame-number = <2>; 1874 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1875 reg = <0 0x17c25000 0 0x1000>; 1876 status = "disabled"; 1877 }; 1878 1879 frame@17c27000 { 1880 frame-number = <3>; 1881 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1882 reg = <0 0x17c27000 0 0x1000>; 1883 status = "disabled"; 1884 }; 1885 1886 frame@17c29000 { 1887 frame-number = <4>; 1888 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1889 reg = <0 0x17c29000 0 0x1000>; 1890 status = "disabled"; 1891 }; 1892 1893 frame@17c2b000 { 1894 frame-number = <5>; 1895 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1896 reg = <0 0x17c2b000 0 0x1000>; 1897 status = "disabled"; 1898 }; 1899 1900 frame@17c2d000 { 1901 frame-number = <6>; 1902 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1903 reg = <0 0x17c2d000 0 0x1000>; 1904 status = "disabled"; 1905 }; 1906 }; 1907 1908 apps_rsc: rsc@18200000 { 1909 compatible = "qcom,rpmh-rsc"; 1910 reg = <0 0x18200000 0 0x10000>, 1911 <0 0x18210000 0 0x10000>, 1912 <0 0x18220000 0 0x10000>; 1913 reg-names = "drv-0", "drv-1", "drv-2"; 1914 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1917 qcom,tcs-offset = <0xd00>; 1918 qcom,drv-id = <2>; 1919 qcom,tcs-config = <ACTIVE_TCS 2>, 1920 <SLEEP_TCS 3>, 1921 <WAKE_TCS 3>, 1922 <CONTROL_TCS 1>; 1923 1924 rpmhcc: clock-controller { 1925 compatible = "qcom,sc7180-rpmh-clk"; 1926 clocks = <&xo_board>; 1927 clock-names = "xo"; 1928 #clock-cells = <1>; 1929 }; 1930 1931 rpmhpd: power-controller { 1932 compatible = "qcom,sc7180-rpmhpd"; 1933 #power-domain-cells = <1>; 1934 operating-points-v2 = <&rpmhpd_opp_table>; 1935 1936 rpmhpd_opp_table: opp-table { 1937 compatible = "operating-points-v2"; 1938 1939 rpmhpd_opp_ret: opp1 { 1940 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1941 }; 1942 1943 rpmhpd_opp_min_svs: opp2 { 1944 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1945 }; 1946 1947 rpmhpd_opp_low_svs: opp3 { 1948 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1949 }; 1950 1951 rpmhpd_opp_svs: opp4 { 1952 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1953 }; 1954 1955 rpmhpd_opp_svs_l1: opp5 { 1956 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1957 }; 1958 1959 rpmhpd_opp_svs_l2: opp6 { 1960 opp-level = <224>; 1961 }; 1962 1963 rpmhpd_opp_nom: opp7 { 1964 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1965 }; 1966 1967 rpmhpd_opp_nom_l1: opp8 { 1968 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1969 }; 1970 1971 rpmhpd_opp_nom_l2: opp9 { 1972 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1973 }; 1974 1975 rpmhpd_opp_turbo: opp10 { 1976 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1977 }; 1978 1979 rpmhpd_opp_turbo_l1: opp11 { 1980 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1981 }; 1982 }; 1983 }; 1984 1985 apps_bcm_voter: bcm_voter { 1986 compatible = "qcom,bcm-voter"; 1987 }; 1988 }; 1989 1990 osm_l3: interconnect@18321000 { 1991 compatible = "qcom,sc7180-osm-l3"; 1992 reg = <0 0x18321000 0 0x1400>; 1993 1994 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1995 clock-names = "xo", "alternate"; 1996 1997 #interconnect-cells = <1>; 1998 }; 1999 2000 cpufreq_hw: cpufreq@18323000 { 2001 compatible = "qcom,cpufreq-hw"; 2002 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 2003 reg-names = "freq-domain0", "freq-domain1"; 2004 2005 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2006 clock-names = "xo", "alternate"; 2007 2008 #freq-domain-cells = <1>; 2009 }; 2010 }; 2011 2012 thermal-zones { 2013 cpu0-thermal { 2014 polling-delay-passive = <250>; 2015 polling-delay = <1000>; 2016 2017 thermal-sensors = <&tsens0 1>; 2018 2019 trips { 2020 cpu0_alert0: trip-point0 { 2021 temperature = <90000>; 2022 hysteresis = <2000>; 2023 type = "passive"; 2024 }; 2025 2026 cpu0_alert1: trip-point1 { 2027 temperature = <95000>; 2028 hysteresis = <2000>; 2029 type = "passive"; 2030 }; 2031 2032 cpu0_crit: cpu_crit { 2033 temperature = <110000>; 2034 hysteresis = <1000>; 2035 type = "critical"; 2036 }; 2037 }; 2038 2039 cooling-maps { 2040 map0 { 2041 trip = <&cpu0_alert0>; 2042 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2043 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2044 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2045 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2046 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2047 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2048 }; 2049 map1 { 2050 trip = <&cpu0_alert1>; 2051 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2052 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2053 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2054 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2055 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2057 }; 2058 }; 2059 }; 2060 2061 cpu1-thermal { 2062 polling-delay-passive = <250>; 2063 polling-delay = <1000>; 2064 2065 thermal-sensors = <&tsens0 2>; 2066 2067 trips { 2068 cpu1_alert0: trip-point0 { 2069 temperature = <90000>; 2070 hysteresis = <2000>; 2071 type = "passive"; 2072 }; 2073 2074 cpu1_alert1: trip-point1 { 2075 temperature = <95000>; 2076 hysteresis = <2000>; 2077 type = "passive"; 2078 }; 2079 2080 cpu1_crit: cpu_crit { 2081 temperature = <110000>; 2082 hysteresis = <1000>; 2083 type = "critical"; 2084 }; 2085 }; 2086 2087 cooling-maps { 2088 map0 { 2089 trip = <&cpu1_alert0>; 2090 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2091 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2092 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2093 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2094 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2095 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2096 }; 2097 map1 { 2098 trip = <&cpu1_alert1>; 2099 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2100 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2101 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2102 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2103 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2104 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2105 }; 2106 }; 2107 }; 2108 2109 cpu2-thermal { 2110 polling-delay-passive = <250>; 2111 polling-delay = <1000>; 2112 2113 thermal-sensors = <&tsens0 3>; 2114 2115 trips { 2116 cpu2_alert0: trip-point0 { 2117 temperature = <90000>; 2118 hysteresis = <2000>; 2119 type = "passive"; 2120 }; 2121 2122 cpu2_alert1: trip-point1 { 2123 temperature = <95000>; 2124 hysteresis = <2000>; 2125 type = "passive"; 2126 }; 2127 2128 cpu2_crit: cpu_crit { 2129 temperature = <110000>; 2130 hysteresis = <1000>; 2131 type = "critical"; 2132 }; 2133 }; 2134 2135 cooling-maps { 2136 map0 { 2137 trip = <&cpu2_alert0>; 2138 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2139 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2140 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2141 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2142 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2143 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2144 }; 2145 map1 { 2146 trip = <&cpu2_alert1>; 2147 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2148 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2149 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2150 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2151 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2152 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2153 }; 2154 }; 2155 }; 2156 2157 cpu3-thermal { 2158 polling-delay-passive = <250>; 2159 polling-delay = <1000>; 2160 2161 thermal-sensors = <&tsens0 4>; 2162 2163 trips { 2164 cpu3_alert0: trip-point0 { 2165 temperature = <90000>; 2166 hysteresis = <2000>; 2167 type = "passive"; 2168 }; 2169 2170 cpu3_alert1: trip-point1 { 2171 temperature = <95000>; 2172 hysteresis = <2000>; 2173 type = "passive"; 2174 }; 2175 2176 cpu3_crit: cpu_crit { 2177 temperature = <110000>; 2178 hysteresis = <1000>; 2179 type = "critical"; 2180 }; 2181 }; 2182 2183 cooling-maps { 2184 map0 { 2185 trip = <&cpu3_alert0>; 2186 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2187 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2188 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2189 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2190 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2191 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2192 }; 2193 map1 { 2194 trip = <&cpu3_alert1>; 2195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2196 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2197 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2199 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2200 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2201 }; 2202 }; 2203 }; 2204 2205 cpu4-thermal { 2206 polling-delay-passive = <250>; 2207 polling-delay = <1000>; 2208 2209 thermal-sensors = <&tsens0 5>; 2210 2211 trips { 2212 cpu4_alert0: trip-point0 { 2213 temperature = <90000>; 2214 hysteresis = <2000>; 2215 type = "passive"; 2216 }; 2217 2218 cpu4_alert1: trip-point1 { 2219 temperature = <95000>; 2220 hysteresis = <2000>; 2221 type = "passive"; 2222 }; 2223 2224 cpu4_crit: cpu_crit { 2225 temperature = <110000>; 2226 hysteresis = <1000>; 2227 type = "critical"; 2228 }; 2229 }; 2230 2231 cooling-maps { 2232 map0 { 2233 trip = <&cpu4_alert0>; 2234 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2235 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2236 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2237 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2238 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2240 }; 2241 map1 { 2242 trip = <&cpu4_alert1>; 2243 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2244 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2245 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2246 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2247 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2249 }; 2250 }; 2251 }; 2252 2253 cpu5-thermal { 2254 polling-delay-passive = <250>; 2255 polling-delay = <1000>; 2256 2257 thermal-sensors = <&tsens0 6>; 2258 2259 trips { 2260 cpu5_alert0: trip-point0 { 2261 temperature = <90000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 2266 cpu5_alert1: trip-point1 { 2267 temperature = <95000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 cpu5_crit: cpu_crit { 2273 temperature = <110000>; 2274 hysteresis = <1000>; 2275 type = "critical"; 2276 }; 2277 }; 2278 2279 cooling-maps { 2280 map0 { 2281 trip = <&cpu5_alert0>; 2282 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2283 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2284 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2285 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2286 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2287 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2288 }; 2289 map1 { 2290 trip = <&cpu5_alert1>; 2291 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2292 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2293 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2294 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2295 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2296 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2297 }; 2298 }; 2299 }; 2300 2301 cpu6-thermal { 2302 polling-delay-passive = <250>; 2303 polling-delay = <1000>; 2304 2305 thermal-sensors = <&tsens0 9>; 2306 2307 trips { 2308 cpu6_alert0: trip-point0 { 2309 temperature = <90000>; 2310 hysteresis = <2000>; 2311 type = "passive"; 2312 }; 2313 2314 cpu6_alert1: trip-point1 { 2315 temperature = <95000>; 2316 hysteresis = <2000>; 2317 type = "passive"; 2318 }; 2319 2320 cpu6_crit: cpu_crit { 2321 temperature = <110000>; 2322 hysteresis = <1000>; 2323 type = "critical"; 2324 }; 2325 }; 2326 2327 cooling-maps { 2328 map0 { 2329 trip = <&cpu6_alert0>; 2330 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2331 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2332 }; 2333 map1 { 2334 trip = <&cpu6_alert1>; 2335 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2337 }; 2338 }; 2339 }; 2340 2341 cpu7-thermal { 2342 polling-delay-passive = <250>; 2343 polling-delay = <1000>; 2344 2345 thermal-sensors = <&tsens0 10>; 2346 2347 trips { 2348 cpu7_alert0: trip-point0 { 2349 temperature = <90000>; 2350 hysteresis = <2000>; 2351 type = "passive"; 2352 }; 2353 2354 cpu7_alert1: trip-point1 { 2355 temperature = <95000>; 2356 hysteresis = <2000>; 2357 type = "passive"; 2358 }; 2359 2360 cpu7_crit: cpu_crit { 2361 temperature = <110000>; 2362 hysteresis = <1000>; 2363 type = "critical"; 2364 }; 2365 }; 2366 2367 cooling-maps { 2368 map0 { 2369 trip = <&cpu7_alert0>; 2370 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2371 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2372 }; 2373 map1 { 2374 trip = <&cpu7_alert1>; 2375 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2376 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2377 }; 2378 }; 2379 }; 2380 2381 cpu8-thermal { 2382 polling-delay-passive = <250>; 2383 polling-delay = <1000>; 2384 2385 thermal-sensors = <&tsens0 11>; 2386 2387 trips { 2388 cpu8_alert0: trip-point0 { 2389 temperature = <90000>; 2390 hysteresis = <2000>; 2391 type = "passive"; 2392 }; 2393 2394 cpu8_alert1: trip-point1 { 2395 temperature = <95000>; 2396 hysteresis = <2000>; 2397 type = "passive"; 2398 }; 2399 2400 cpu8_crit: cpu_crit { 2401 temperature = <110000>; 2402 hysteresis = <1000>; 2403 type = "critical"; 2404 }; 2405 }; 2406 2407 cooling-maps { 2408 map0 { 2409 trip = <&cpu8_alert0>; 2410 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2411 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2412 }; 2413 map1 { 2414 trip = <&cpu8_alert1>; 2415 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2416 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2417 }; 2418 }; 2419 }; 2420 2421 cpu9-thermal { 2422 polling-delay-passive = <250>; 2423 polling-delay = <1000>; 2424 2425 thermal-sensors = <&tsens0 12>; 2426 2427 trips { 2428 cpu9_alert0: trip-point0 { 2429 temperature = <90000>; 2430 hysteresis = <2000>; 2431 type = "passive"; 2432 }; 2433 2434 cpu9_alert1: trip-point1 { 2435 temperature = <95000>; 2436 hysteresis = <2000>; 2437 type = "passive"; 2438 }; 2439 2440 cpu9_crit: cpu_crit { 2441 temperature = <110000>; 2442 hysteresis = <1000>; 2443 type = "critical"; 2444 }; 2445 }; 2446 2447 cooling-maps { 2448 map0 { 2449 trip = <&cpu9_alert0>; 2450 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2451 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2452 }; 2453 map1 { 2454 trip = <&cpu9_alert1>; 2455 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2456 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2457 }; 2458 }; 2459 }; 2460 2461 aoss0-thermal { 2462 polling-delay-passive = <250>; 2463 polling-delay = <1000>; 2464 2465 thermal-sensors = <&tsens0 0>; 2466 2467 trips { 2468 aoss0_alert0: trip-point0 { 2469 temperature = <90000>; 2470 hysteresis = <2000>; 2471 type = "hot"; 2472 }; 2473 2474 aoss0_crit: aoss0_crit { 2475 temperature = <110000>; 2476 hysteresis = <2000>; 2477 type = "critical"; 2478 }; 2479 }; 2480 }; 2481 2482 cpuss0-thermal { 2483 polling-delay-passive = <250>; 2484 polling-delay = <1000>; 2485 2486 thermal-sensors = <&tsens0 7>; 2487 2488 trips { 2489 cpuss0_alert0: trip-point0 { 2490 temperature = <90000>; 2491 hysteresis = <2000>; 2492 type = "hot"; 2493 }; 2494 cpuss0_crit: cluster0_crit { 2495 temperature = <110000>; 2496 hysteresis = <2000>; 2497 type = "critical"; 2498 }; 2499 }; 2500 }; 2501 2502 cpuss1-thermal { 2503 polling-delay-passive = <250>; 2504 polling-delay = <1000>; 2505 2506 thermal-sensors = <&tsens0 8>; 2507 2508 trips { 2509 cpuss1_alert0: trip-point0 { 2510 temperature = <90000>; 2511 hysteresis = <2000>; 2512 type = "hot"; 2513 }; 2514 cpuss1_crit: cluster0_crit { 2515 temperature = <110000>; 2516 hysteresis = <2000>; 2517 type = "critical"; 2518 }; 2519 }; 2520 }; 2521 2522 gpuss0-thermal { 2523 polling-delay-passive = <250>; 2524 polling-delay = <1000>; 2525 2526 thermal-sensors = <&tsens0 13>; 2527 2528 trips { 2529 gpuss0_alert0: trip-point0 { 2530 temperature = <90000>; 2531 hysteresis = <2000>; 2532 type = "hot"; 2533 }; 2534 2535 gpuss0_crit: gpuss0_crit { 2536 temperature = <110000>; 2537 hysteresis = <2000>; 2538 type = "critical"; 2539 }; 2540 }; 2541 }; 2542 2543 gpuss1-thermal { 2544 polling-delay-passive = <250>; 2545 polling-delay = <1000>; 2546 2547 thermal-sensors = <&tsens0 14>; 2548 2549 trips { 2550 gpuss1_alert0: trip-point0 { 2551 temperature = <90000>; 2552 hysteresis = <2000>; 2553 type = "hot"; 2554 }; 2555 2556 gpuss1_crit: gpuss1_crit { 2557 temperature = <110000>; 2558 hysteresis = <2000>; 2559 type = "critical"; 2560 }; 2561 }; 2562 }; 2563 2564 aoss1-thermal { 2565 polling-delay-passive = <250>; 2566 polling-delay = <1000>; 2567 2568 thermal-sensors = <&tsens1 0>; 2569 2570 trips { 2571 aoss1_alert0: trip-point0 { 2572 temperature = <90000>; 2573 hysteresis = <2000>; 2574 type = "hot"; 2575 }; 2576 2577 aoss1_crit: aoss1_crit { 2578 temperature = <110000>; 2579 hysteresis = <2000>; 2580 type = "critical"; 2581 }; 2582 }; 2583 }; 2584 2585 cwlan-thermal { 2586 polling-delay-passive = <250>; 2587 polling-delay = <1000>; 2588 2589 thermal-sensors = <&tsens1 1>; 2590 2591 trips { 2592 cwlan_alert0: trip-point0 { 2593 temperature = <90000>; 2594 hysteresis = <2000>; 2595 type = "hot"; 2596 }; 2597 2598 cwlan_crit: cwlan_crit { 2599 temperature = <110000>; 2600 hysteresis = <2000>; 2601 type = "critical"; 2602 }; 2603 }; 2604 }; 2605 2606 audio-thermal { 2607 polling-delay-passive = <250>; 2608 polling-delay = <1000>; 2609 2610 thermal-sensors = <&tsens1 2>; 2611 2612 trips { 2613 audio_alert0: trip-point0 { 2614 temperature = <90000>; 2615 hysteresis = <2000>; 2616 type = "hot"; 2617 }; 2618 2619 audio_crit: audio_crit { 2620 temperature = <110000>; 2621 hysteresis = <2000>; 2622 type = "critical"; 2623 }; 2624 }; 2625 }; 2626 2627 ddr-thermal { 2628 polling-delay-passive = <250>; 2629 polling-delay = <1000>; 2630 2631 thermal-sensors = <&tsens1 3>; 2632 2633 trips { 2634 ddr_alert0: trip-point0 { 2635 temperature = <90000>; 2636 hysteresis = <2000>; 2637 type = "hot"; 2638 }; 2639 2640 ddr_crit: ddr_crit { 2641 temperature = <110000>; 2642 hysteresis = <2000>; 2643 type = "critical"; 2644 }; 2645 }; 2646 }; 2647 2648 q6-hvx-thermal { 2649 polling-delay-passive = <250>; 2650 polling-delay = <1000>; 2651 2652 thermal-sensors = <&tsens1 4>; 2653 2654 trips { 2655 q6_hvx_alert0: trip-point0 { 2656 temperature = <90000>; 2657 hysteresis = <2000>; 2658 type = "hot"; 2659 }; 2660 2661 q6_hvx_crit: q6_hvx_crit { 2662 temperature = <110000>; 2663 hysteresis = <2000>; 2664 type = "critical"; 2665 }; 2666 }; 2667 }; 2668 2669 camera-thermal { 2670 polling-delay-passive = <250>; 2671 polling-delay = <1000>; 2672 2673 thermal-sensors = <&tsens1 5>; 2674 2675 trips { 2676 camera_alert0: trip-point0 { 2677 temperature = <90000>; 2678 hysteresis = <2000>; 2679 type = "hot"; 2680 }; 2681 2682 camera_crit: camera_crit { 2683 temperature = <110000>; 2684 hysteresis = <2000>; 2685 type = "critical"; 2686 }; 2687 }; 2688 }; 2689 2690 mdm-core-thermal { 2691 polling-delay-passive = <250>; 2692 polling-delay = <1000>; 2693 2694 thermal-sensors = <&tsens1 6>; 2695 2696 trips { 2697 mdm_alert0: trip-point0 { 2698 temperature = <90000>; 2699 hysteresis = <2000>; 2700 type = "hot"; 2701 }; 2702 2703 mdm_crit: mdm_crit { 2704 temperature = <110000>; 2705 hysteresis = <2000>; 2706 type = "critical"; 2707 }; 2708 }; 2709 }; 2710 2711 mdm-dsp-thermal { 2712 polling-delay-passive = <250>; 2713 polling-delay = <1000>; 2714 2715 thermal-sensors = <&tsens1 7>; 2716 2717 trips { 2718 mdm_dsp_alert0: trip-point0 { 2719 temperature = <90000>; 2720 hysteresis = <2000>; 2721 type = "hot"; 2722 }; 2723 2724 mdm_dsp_crit: mdm_dsp_crit { 2725 temperature = <110000>; 2726 hysteresis = <2000>; 2727 type = "critical"; 2728 }; 2729 }; 2730 }; 2731 2732 npu-thermal { 2733 polling-delay-passive = <250>; 2734 polling-delay = <1000>; 2735 2736 thermal-sensors = <&tsens1 8>; 2737 2738 trips { 2739 npu_alert0: trip-point0 { 2740 temperature = <90000>; 2741 hysteresis = <2000>; 2742 type = "hot"; 2743 }; 2744 2745 npu_crit: npu_crit { 2746 temperature = <110000>; 2747 hysteresis = <2000>; 2748 type = "critical"; 2749 }; 2750 }; 2751 }; 2752 2753 video-thermal { 2754 polling-delay-passive = <250>; 2755 polling-delay = <1000>; 2756 2757 thermal-sensors = <&tsens1 9>; 2758 2759 trips { 2760 video_alert0: trip-point0 { 2761 temperature = <90000>; 2762 hysteresis = <2000>; 2763 type = "hot"; 2764 }; 2765 2766 video_crit: video_crit { 2767 temperature = <110000>; 2768 hysteresis = <2000>; 2769 type = "critical"; 2770 }; 2771 }; 2772 }; 2773 }; 2774 2775 timer { 2776 compatible = "arm,armv8-timer"; 2777 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2778 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2779 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2780 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2781 }; 2782}; 2783