1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2016 ARM Ltd.
3// based on the Allwinner H3 dtsi:
4//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6#include <dt-bindings/clock/sun50i-a64-ccu.h>
7#include <dt-bindings/clock/sun8i-de2.h>
8#include <dt-bindings/clock/sun8i-r-ccu.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/sun50i-a64-ccu.h>
11#include <dt-bindings/reset/sun8i-de2.h>
12#include <dt-bindings/reset/sun8i-r-ccu.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	chosen {
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges;
24
25		simplefb_lcd: framebuffer-lcd {
26			compatible = "allwinner,simple-framebuffer",
27				     "simple-framebuffer";
28			allwinner,pipeline = "mixer0-lcd0";
29			clocks = <&ccu CLK_TCON0>,
30				 <&display_clocks CLK_MIXER0>;
31			status = "disabled";
32		};
33
34		simplefb_hdmi: framebuffer-hdmi {
35			compatible = "allwinner,simple-framebuffer",
36				     "simple-framebuffer";
37			allwinner,pipeline = "mixer1-lcd1-hdmi";
38			clocks = <&display_clocks CLK_MIXER1>,
39				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40			status = "disabled";
41		};
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		cpu0: cpu@0 {
49			compatible = "arm,cortex-a53";
50			device_type = "cpu";
51			reg = <0>;
52			enable-method = "psci";
53			next-level-cache = <&L2>;
54			clocks = <&ccu 21>;
55			clock-names = "cpu";
56			#cooling-cells = <2>;
57		};
58
59		cpu1: cpu@1 {
60			compatible = "arm,cortex-a53";
61			device_type = "cpu";
62			reg = <1>;
63			enable-method = "psci";
64			next-level-cache = <&L2>;
65			clocks = <&ccu 21>;
66			clock-names = "cpu";
67			#cooling-cells = <2>;
68		};
69
70		cpu2: cpu@2 {
71			compatible = "arm,cortex-a53";
72			device_type = "cpu";
73			reg = <2>;
74			enable-method = "psci";
75			next-level-cache = <&L2>;
76			clocks = <&ccu 21>;
77			clock-names = "cpu";
78			#cooling-cells = <2>;
79		};
80
81		cpu3: cpu@3 {
82			compatible = "arm,cortex-a53";
83			device_type = "cpu";
84			reg = <3>;
85			enable-method = "psci";
86			next-level-cache = <&L2>;
87			clocks = <&ccu 21>;
88			clock-names = "cpu";
89			#cooling-cells = <2>;
90		};
91
92		L2: l2-cache {
93			compatible = "cache";
94			cache-level = <2>;
95		};
96	};
97
98	de: display-engine {
99		compatible = "allwinner,sun50i-a64-display-engine";
100		allwinner,pipelines = <&mixer0>,
101				      <&mixer1>;
102		status = "disabled";
103	};
104
105	osc24M: osc24M_clk {
106		#clock-cells = <0>;
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "osc24M";
110	};
111
112	osc32k: osc32k_clk {
113		#clock-cells = <0>;
114		compatible = "fixed-clock";
115		clock-frequency = <32768>;
116		clock-output-names = "ext-osc32k";
117	};
118
119	pmu {
120		compatible = "arm,cortex-a53-pmu";
121		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126	};
127
128	psci {
129		compatible = "arm,psci-0.2";
130		method = "smc";
131	};
132
133	sound: sound {
134		compatible = "simple-audio-card";
135		simple-audio-card,name = "sun50i-a64-audio";
136		simple-audio-card,format = "i2s";
137		simple-audio-card,frame-master = <&cpudai>;
138		simple-audio-card,bitclock-master = <&cpudai>;
139		simple-audio-card,mclk-fs = <128>;
140		simple-audio-card,aux-devs = <&codec_analog>;
141		simple-audio-card,routing =
142				"Left DAC", "AIF1 Slot 0 Left",
143				"Right DAC", "AIF1 Slot 0 Right",
144				"AIF1 Slot 0 Left ADC", "Left ADC",
145				"AIF1 Slot 0 Right ADC", "Right ADC";
146		status = "disabled";
147
148		cpudai: simple-audio-card,cpu {
149			sound-dai = <&dai>;
150		};
151
152		link_codec: simple-audio-card,codec {
153			sound-dai = <&codec>;
154		};
155	};
156
157	sound_spdif {
158		compatible = "simple-audio-card";
159		simple-audio-card,name = "On-board SPDIF";
160
161		simple-audio-card,cpu {
162			sound-dai = <&spdif>;
163		};
164
165		simple-audio-card,codec {
166			sound-dai = <&spdif_out>;
167		};
168	};
169
170	spdif_out: spdif-out {
171		#sound-dai-cells = <0>;
172		compatible = "linux,spdif-dit";
173	};
174
175	timer {
176		compatible = "arm,armv8-timer";
177		allwinner,erratum-unknown1;
178		interrupts = <GIC_PPI 13
179			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
180			     <GIC_PPI 14
181			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
182			     <GIC_PPI 11
183			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
184			     <GIC_PPI 10
185			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
186	};
187
188	thermal-zones {
189		cpu_thermal: cpu0-thermal {
190			/* milliseconds */
191			polling-delay-passive = <0>;
192			polling-delay = <0>;
193			thermal-sensors = <&ths 0>;
194
195			cooling-maps {
196				map0 {
197					trip = <&cpu_alert0>;
198					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
199							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202				};
203				map1 {
204					trip = <&cpu_alert1>;
205					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
209				};
210			};
211
212			trips {
213				cpu_alert0: cpu_alert0 {
214					/* milliCelsius */
215					temperature = <75000>;
216					hysteresis = <2000>;
217					type = "passive";
218				};
219
220				cpu_alert1: cpu_alert1 {
221					/* milliCelsius */
222					temperature = <90000>;
223					hysteresis = <2000>;
224					type = "hot";
225				};
226
227				cpu_crit: cpu_crit {
228					/* milliCelsius */
229					temperature = <110000>;
230					hysteresis = <2000>;
231					type = "critical";
232				};
233			};
234		};
235
236		gpu0_thermal: gpu0-thermal {
237			/* milliseconds */
238			polling-delay-passive = <0>;
239			polling-delay = <0>;
240			thermal-sensors = <&ths 1>;
241		};
242
243		gpu1_thermal: gpu1-thermal {
244			/* milliseconds */
245			polling-delay-passive = <0>;
246			polling-delay = <0>;
247			thermal-sensors = <&ths 2>;
248		};
249	};
250
251	soc {
252		compatible = "simple-bus";
253		#address-cells = <1>;
254		#size-cells = <1>;
255		ranges;
256
257		bus@1000000 {
258			compatible = "allwinner,sun50i-a64-de2";
259			reg = <0x1000000 0x400000>;
260			allwinner,sram = <&de2_sram 1>;
261			#address-cells = <1>;
262			#size-cells = <1>;
263			ranges = <0 0x1000000 0x400000>;
264
265			display_clocks: clock@0 {
266				compatible = "allwinner,sun50i-a64-de2-clk";
267				reg = <0x0 0x10000>;
268				clocks = <&ccu CLK_BUS_DE>,
269					 <&ccu CLK_DE>;
270				clock-names = "bus",
271					      "mod";
272				resets = <&ccu RST_BUS_DE>;
273				#clock-cells = <1>;
274				#reset-cells = <1>;
275			};
276
277			rotate: rotate@20000 {
278				compatible = "allwinner,sun50i-a64-de2-rotate",
279					     "allwinner,sun8i-a83t-de2-rotate";
280				reg = <0x20000 0x10000>;
281				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
282				clocks = <&display_clocks CLK_BUS_ROT>,
283					 <&display_clocks CLK_ROT>;
284				clock-names = "bus",
285					      "mod";
286				resets = <&display_clocks RST_ROT>;
287			};
288
289			mixer0: mixer@100000 {
290				compatible = "allwinner,sun50i-a64-de2-mixer-0";
291				reg = <0x100000 0x100000>;
292				clocks = <&display_clocks CLK_BUS_MIXER0>,
293					 <&display_clocks CLK_MIXER0>;
294				clock-names = "bus",
295					      "mod";
296				resets = <&display_clocks RST_MIXER0>;
297
298				ports {
299					#address-cells = <1>;
300					#size-cells = <0>;
301
302					mixer0_out: port@1 {
303						#address-cells = <1>;
304						#size-cells = <0>;
305						reg = <1>;
306
307						mixer0_out_tcon0: endpoint@0 {
308							reg = <0>;
309							remote-endpoint = <&tcon0_in_mixer0>;
310						};
311
312						mixer0_out_tcon1: endpoint@1 {
313							reg = <1>;
314							remote-endpoint = <&tcon1_in_mixer0>;
315						};
316					};
317				};
318			};
319
320			mixer1: mixer@200000 {
321				compatible = "allwinner,sun50i-a64-de2-mixer-1";
322				reg = <0x200000 0x100000>;
323				clocks = <&display_clocks CLK_BUS_MIXER1>,
324					 <&display_clocks CLK_MIXER1>;
325				clock-names = "bus",
326					      "mod";
327				resets = <&display_clocks RST_MIXER1>;
328
329				ports {
330					#address-cells = <1>;
331					#size-cells = <0>;
332
333					mixer1_out: port@1 {
334						#address-cells = <1>;
335						#size-cells = <0>;
336						reg = <1>;
337
338						mixer1_out_tcon0: endpoint@0 {
339							reg = <0>;
340							remote-endpoint = <&tcon0_in_mixer1>;
341						};
342
343						mixer1_out_tcon1: endpoint@1 {
344							reg = <1>;
345							remote-endpoint = <&tcon1_in_mixer1>;
346						};
347					};
348				};
349			};
350		};
351
352		syscon: syscon@1c00000 {
353			compatible = "allwinner,sun50i-a64-system-control";
354			reg = <0x01c00000 0x1000>;
355			#address-cells = <1>;
356			#size-cells = <1>;
357			ranges;
358
359			sram_c: sram@18000 {
360				compatible = "mmio-sram";
361				reg = <0x00018000 0x28000>;
362				#address-cells = <1>;
363				#size-cells = <1>;
364				ranges = <0 0x00018000 0x28000>;
365
366				de2_sram: sram-section@0 {
367					compatible = "allwinner,sun50i-a64-sram-c";
368					reg = <0x0000 0x28000>;
369				};
370			};
371
372			sram_c1: sram@1d00000 {
373				compatible = "mmio-sram";
374				reg = <0x01d00000 0x40000>;
375				#address-cells = <1>;
376				#size-cells = <1>;
377				ranges = <0 0x01d00000 0x40000>;
378
379				ve_sram: sram-section@0 {
380					compatible = "allwinner,sun50i-a64-sram-c1",
381						     "allwinner,sun4i-a10-sram-c1";
382					reg = <0x000000 0x40000>;
383				};
384			};
385		};
386
387		dma: dma-controller@1c02000 {
388			compatible = "allwinner,sun50i-a64-dma";
389			reg = <0x01c02000 0x1000>;
390			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
391			clocks = <&ccu CLK_BUS_DMA>;
392			dma-channels = <8>;
393			dma-requests = <27>;
394			resets = <&ccu RST_BUS_DMA>;
395			#dma-cells = <1>;
396		};
397
398		tcon0: lcd-controller@1c0c000 {
399			compatible = "allwinner,sun50i-a64-tcon-lcd",
400				     "allwinner,sun8i-a83t-tcon-lcd";
401			reg = <0x01c0c000 0x1000>;
402			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
403			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
404			clock-names = "ahb", "tcon-ch0";
405			clock-output-names = "tcon-pixel-clock";
406			#clock-cells = <0>;
407			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
408			reset-names = "lcd", "lvds";
409
410			ports {
411				#address-cells = <1>;
412				#size-cells = <0>;
413
414				tcon0_in: port@0 {
415					#address-cells = <1>;
416					#size-cells = <0>;
417					reg = <0>;
418
419					tcon0_in_mixer0: endpoint@0 {
420						reg = <0>;
421						remote-endpoint = <&mixer0_out_tcon0>;
422					};
423
424					tcon0_in_mixer1: endpoint@1 {
425						reg = <1>;
426						remote-endpoint = <&mixer1_out_tcon0>;
427					};
428				};
429
430				tcon0_out: port@1 {
431					#address-cells = <1>;
432					#size-cells = <0>;
433					reg = <1>;
434
435					tcon0_out_dsi: endpoint@1 {
436						reg = <1>;
437						remote-endpoint = <&dsi_in_tcon0>;
438						allwinner,tcon-channel = <1>;
439					};
440				};
441			};
442		};
443
444		tcon1: lcd-controller@1c0d000 {
445			compatible = "allwinner,sun50i-a64-tcon-tv",
446				     "allwinner,sun8i-a83t-tcon-tv";
447			reg = <0x01c0d000 0x1000>;
448			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
449			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
450			clock-names = "ahb", "tcon-ch1";
451			resets = <&ccu RST_BUS_TCON1>;
452			reset-names = "lcd";
453
454			ports {
455				#address-cells = <1>;
456				#size-cells = <0>;
457
458				tcon1_in: port@0 {
459					#address-cells = <1>;
460					#size-cells = <0>;
461					reg = <0>;
462
463					tcon1_in_mixer0: endpoint@0 {
464						reg = <0>;
465						remote-endpoint = <&mixer0_out_tcon1>;
466					};
467
468					tcon1_in_mixer1: endpoint@1 {
469						reg = <1>;
470						remote-endpoint = <&mixer1_out_tcon1>;
471					};
472				};
473
474				tcon1_out: port@1 {
475					#address-cells = <1>;
476					#size-cells = <0>;
477					reg = <1>;
478
479					tcon1_out_hdmi: endpoint@1 {
480						reg = <1>;
481						remote-endpoint = <&hdmi_in_tcon1>;
482					};
483				};
484			};
485		};
486
487		video-codec@1c0e000 {
488			compatible = "allwinner,sun50i-a64-video-engine";
489			reg = <0x01c0e000 0x1000>;
490			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
491				 <&ccu CLK_DRAM_VE>;
492			clock-names = "ahb", "mod", "ram";
493			resets = <&ccu RST_BUS_VE>;
494			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
495			allwinner,sram = <&ve_sram 1>;
496		};
497
498		mmc0: mmc@1c0f000 {
499			compatible = "allwinner,sun50i-a64-mmc";
500			reg = <0x01c0f000 0x1000>;
501			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
502			clock-names = "ahb", "mmc";
503			resets = <&ccu RST_BUS_MMC0>;
504			reset-names = "ahb";
505			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
506			max-frequency = <150000000>;
507			status = "disabled";
508			#address-cells = <1>;
509			#size-cells = <0>;
510		};
511
512		mmc1: mmc@1c10000 {
513			compatible = "allwinner,sun50i-a64-mmc";
514			reg = <0x01c10000 0x1000>;
515			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
516			clock-names = "ahb", "mmc";
517			resets = <&ccu RST_BUS_MMC1>;
518			reset-names = "ahb";
519			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
520			max-frequency = <150000000>;
521			status = "disabled";
522			#address-cells = <1>;
523			#size-cells = <0>;
524		};
525
526		mmc2: mmc@1c11000 {
527			compatible = "allwinner,sun50i-a64-emmc";
528			reg = <0x01c11000 0x1000>;
529			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
530			clock-names = "ahb", "mmc";
531			resets = <&ccu RST_BUS_MMC2>;
532			reset-names = "ahb";
533			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
534			max-frequency = <200000000>;
535			status = "disabled";
536			#address-cells = <1>;
537			#size-cells = <0>;
538		};
539
540		sid: eeprom@1c14000 {
541			compatible = "allwinner,sun50i-a64-sid";
542			reg = <0x1c14000 0x400>;
543			#address-cells = <1>;
544			#size-cells = <1>;
545
546			ths_calibration: thermal-sensor-calibration@34 {
547				reg = <0x34 0x8>;
548			};
549		};
550
551		crypto: crypto@1c15000 {
552			compatible = "allwinner,sun50i-a64-crypto";
553			reg = <0x01c15000 0x1000>;
554			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
555			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
556			clock-names = "bus", "mod";
557			resets = <&ccu RST_BUS_CE>;
558		};
559
560		usb_otg: usb@1c19000 {
561			compatible = "allwinner,sun8i-a33-musb";
562			reg = <0x01c19000 0x0400>;
563			clocks = <&ccu CLK_BUS_OTG>;
564			resets = <&ccu RST_BUS_OTG>;
565			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
566			interrupt-names = "mc";
567			phys = <&usbphy 0>;
568			phy-names = "usb";
569			extcon = <&usbphy 0>;
570			dr_mode = "otg";
571			status = "disabled";
572		};
573
574		usbphy: phy@1c19400 {
575			compatible = "allwinner,sun50i-a64-usb-phy";
576			reg = <0x01c19400 0x14>,
577			      <0x01c1a800 0x4>,
578			      <0x01c1b800 0x4>;
579			reg-names = "phy_ctrl",
580				    "pmu0",
581				    "pmu1";
582			clocks = <&ccu CLK_USB_PHY0>,
583				 <&ccu CLK_USB_PHY1>;
584			clock-names = "usb0_phy",
585				      "usb1_phy";
586			resets = <&ccu RST_USB_PHY0>,
587				 <&ccu RST_USB_PHY1>;
588			reset-names = "usb0_reset",
589				      "usb1_reset";
590			status = "disabled";
591			#phy-cells = <1>;
592		};
593
594		ehci0: usb@1c1a000 {
595			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
596			reg = <0x01c1a000 0x100>;
597			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
598			clocks = <&ccu CLK_BUS_OHCI0>,
599				 <&ccu CLK_BUS_EHCI0>,
600				 <&ccu CLK_USB_OHCI0>;
601			resets = <&ccu RST_BUS_OHCI0>,
602				 <&ccu RST_BUS_EHCI0>;
603			status = "disabled";
604		};
605
606		ohci0: usb@1c1a400 {
607			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
608			reg = <0x01c1a400 0x100>;
609			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
610			clocks = <&ccu CLK_BUS_OHCI0>,
611				 <&ccu CLK_USB_OHCI0>;
612			resets = <&ccu RST_BUS_OHCI0>;
613			status = "disabled";
614		};
615
616		ehci1: usb@1c1b000 {
617			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
618			reg = <0x01c1b000 0x100>;
619			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
620			clocks = <&ccu CLK_BUS_OHCI1>,
621				 <&ccu CLK_BUS_EHCI1>,
622				 <&ccu CLK_USB_OHCI1>;
623			resets = <&ccu RST_BUS_OHCI1>,
624				 <&ccu RST_BUS_EHCI1>;
625			phys = <&usbphy 1>;
626			phy-names = "usb";
627			status = "disabled";
628		};
629
630		ohci1: usb@1c1b400 {
631			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
632			reg = <0x01c1b400 0x100>;
633			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
634			clocks = <&ccu CLK_BUS_OHCI1>,
635				 <&ccu CLK_USB_OHCI1>;
636			resets = <&ccu RST_BUS_OHCI1>;
637			phys = <&usbphy 1>;
638			phy-names = "usb";
639			status = "disabled";
640		};
641
642		ccu: clock@1c20000 {
643			compatible = "allwinner,sun50i-a64-ccu";
644			reg = <0x01c20000 0x400>;
645			clocks = <&osc24M>, <&rtc 0>;
646			clock-names = "hosc", "losc";
647			#clock-cells = <1>;
648			#reset-cells = <1>;
649		};
650
651		pio: pinctrl@1c20800 {
652			compatible = "allwinner,sun50i-a64-pinctrl";
653			reg = <0x01c20800 0x400>;
654			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
655				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
656				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
657			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
658			clock-names = "apb", "hosc", "losc";
659			gpio-controller;
660			#gpio-cells = <3>;
661			interrupt-controller;
662			#interrupt-cells = <3>;
663
664			csi_pins: csi-pins {
665				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
666				       "PE7", "PE8", "PE9", "PE10", "PE11";
667				function = "csi";
668			};
669
670			/omit-if-no-ref/
671			csi_mclk_pin: csi-mclk-pin {
672				pins = "PE1";
673				function = "csi";
674			};
675
676			i2c0_pins: i2c0-pins {
677				pins = "PH0", "PH1";
678				function = "i2c0";
679			};
680
681			i2c1_pins: i2c1-pins {
682				pins = "PH2", "PH3";
683				function = "i2c1";
684			};
685
686			i2c2_pins: i2c2-pins {
687				pins = "PE14", "PE15";
688				function = "i2c2";
689			};
690
691			/omit-if-no-ref/
692			lcd_rgb666_pins: lcd-rgb666-pins {
693				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
694				       "PD5", "PD6", "PD7", "PD8", "PD9",
695				       "PD10", "PD11", "PD12", "PD13",
696				       "PD14", "PD15", "PD16", "PD17",
697				       "PD18", "PD19", "PD20", "PD21";
698				function = "lcd0";
699			};
700
701			mmc0_pins: mmc0-pins {
702				pins = "PF0", "PF1", "PF2", "PF3",
703				       "PF4", "PF5";
704				function = "mmc0";
705				drive-strength = <30>;
706				bias-pull-up;
707			};
708
709			mmc1_pins: mmc1-pins {
710				pins = "PG0", "PG1", "PG2", "PG3",
711				       "PG4", "PG5";
712				function = "mmc1";
713				drive-strength = <30>;
714				bias-pull-up;
715			};
716
717			mmc2_pins: mmc2-pins {
718				pins = "PC5", "PC6", "PC8", "PC9",
719				       "PC10","PC11", "PC12", "PC13",
720				       "PC14", "PC15", "PC16";
721				function = "mmc2";
722				drive-strength = <30>;
723				bias-pull-up;
724			};
725
726			mmc2_ds_pin: mmc2-ds-pin {
727				pins = "PC1";
728				function = "mmc2";
729				drive-strength = <30>;
730				bias-pull-up;
731			};
732
733			pwm_pin: pwm-pin {
734				pins = "PD22";
735				function = "pwm";
736			};
737
738			rmii_pins: rmii-pins {
739				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
740				       "PD18", "PD19", "PD20", "PD22", "PD23";
741				function = "emac";
742				drive-strength = <40>;
743			};
744
745			rgmii_pins: rgmii-pins {
746				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
747				       "PD13", "PD15", "PD16", "PD17", "PD18",
748				       "PD19", "PD20", "PD21", "PD22", "PD23";
749				function = "emac";
750				drive-strength = <40>;
751			};
752
753			spdif_tx_pin: spdif-tx-pin {
754				pins = "PH8";
755				function = "spdif";
756			};
757
758			spi0_pins: spi0-pins {
759				pins = "PC0", "PC1", "PC2", "PC3";
760				function = "spi0";
761			};
762
763			spi1_pins: spi1-pins {
764				pins = "PD0", "PD1", "PD2", "PD3";
765				function = "spi1";
766			};
767
768			uart0_pb_pins: uart0-pb-pins {
769				pins = "PB8", "PB9";
770				function = "uart0";
771			};
772
773			uart1_pins: uart1-pins {
774				pins = "PG6", "PG7";
775				function = "uart1";
776			};
777
778			uart1_rts_cts_pins: uart1-rts-cts-pins {
779				pins = "PG8", "PG9";
780				function = "uart1";
781			};
782
783			uart2_pins: uart2-pins {
784				pins = "PB0", "PB1";
785				function = "uart2";
786			};
787
788			uart3_pins: uart3-pins {
789				pins = "PD0", "PD1";
790				function = "uart3";
791			};
792
793			uart4_pins: uart4-pins {
794				pins = "PD2", "PD3";
795				function = "uart4";
796			};
797
798			uart4_rts_cts_pins: uart4-rts-cts-pins {
799				pins = "PD4", "PD5";
800				function = "uart4";
801			};
802		};
803
804		spdif: spdif@1c21000 {
805			#sound-dai-cells = <0>;
806			compatible = "allwinner,sun50i-a64-spdif",
807				     "allwinner,sun8i-h3-spdif";
808			reg = <0x01c21000 0x400>;
809			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
811			resets = <&ccu RST_BUS_SPDIF>;
812			clock-names = "apb", "spdif";
813			dmas = <&dma 2>;
814			dma-names = "tx";
815			pinctrl-names = "default";
816			pinctrl-0 = <&spdif_tx_pin>;
817			status = "disabled";
818		};
819
820		lradc: lradc@1c21800 {
821			compatible = "allwinner,sun50i-a64-lradc",
822				     "allwinner,sun8i-a83t-r-lradc";
823			reg = <0x01c21800 0x400>;
824			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
825			status = "disabled";
826		};
827
828		i2s0: i2s@1c22000 {
829			#sound-dai-cells = <0>;
830			compatible = "allwinner,sun50i-a64-i2s",
831				     "allwinner,sun8i-h3-i2s";
832			reg = <0x01c22000 0x400>;
833			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
834			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
835			clock-names = "apb", "mod";
836			resets = <&ccu RST_BUS_I2S0>;
837			dma-names = "rx", "tx";
838			dmas = <&dma 3>, <&dma 3>;
839			status = "disabled";
840		};
841
842		i2s1: i2s@1c22400 {
843			#sound-dai-cells = <0>;
844			compatible = "allwinner,sun50i-a64-i2s",
845				     "allwinner,sun8i-h3-i2s";
846			reg = <0x01c22400 0x400>;
847			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
848			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
849			clock-names = "apb", "mod";
850			resets = <&ccu RST_BUS_I2S1>;
851			dma-names = "rx", "tx";
852			dmas = <&dma 4>, <&dma 4>;
853			status = "disabled";
854		};
855
856		dai: dai@1c22c00 {
857			#sound-dai-cells = <0>;
858			compatible = "allwinner,sun50i-a64-codec-i2s";
859			reg = <0x01c22c00 0x200>;
860			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
861			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
862			clock-names = "apb", "mod";
863			resets = <&ccu RST_BUS_CODEC>;
864			dmas = <&dma 15>, <&dma 15>;
865			dma-names = "rx", "tx";
866			status = "disabled";
867		};
868
869		codec: codec@1c22e00 {
870			#sound-dai-cells = <0>;
871			compatible = "allwinner,sun8i-a33-codec";
872			reg = <0x01c22e00 0x600>;
873			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
874			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
875			clock-names = "bus", "mod";
876			status = "disabled";
877		};
878
879		ths: thermal-sensor@1c25000 {
880			compatible = "allwinner,sun50i-a64-ths";
881			reg = <0x01c25000 0x100>;
882			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
883			clock-names = "bus", "mod";
884			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885			resets = <&ccu RST_BUS_THS>;
886			nvmem-cells = <&ths_calibration>;
887			nvmem-cell-names = "calibration";
888			#thermal-sensor-cells = <1>;
889		};
890
891		uart0: serial@1c28000 {
892			compatible = "snps,dw-apb-uart";
893			reg = <0x01c28000 0x400>;
894			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
895			reg-shift = <2>;
896			reg-io-width = <4>;
897			clocks = <&ccu CLK_BUS_UART0>;
898			resets = <&ccu RST_BUS_UART0>;
899			status = "disabled";
900		};
901
902		uart1: serial@1c28400 {
903			compatible = "snps,dw-apb-uart";
904			reg = <0x01c28400 0x400>;
905			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
906			reg-shift = <2>;
907			reg-io-width = <4>;
908			clocks = <&ccu CLK_BUS_UART1>;
909			resets = <&ccu RST_BUS_UART1>;
910			status = "disabled";
911		};
912
913		uart2: serial@1c28800 {
914			compatible = "snps,dw-apb-uart";
915			reg = <0x01c28800 0x400>;
916			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
917			reg-shift = <2>;
918			reg-io-width = <4>;
919			clocks = <&ccu CLK_BUS_UART2>;
920			resets = <&ccu RST_BUS_UART2>;
921			status = "disabled";
922		};
923
924		uart3: serial@1c28c00 {
925			compatible = "snps,dw-apb-uart";
926			reg = <0x01c28c00 0x400>;
927			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
928			reg-shift = <2>;
929			reg-io-width = <4>;
930			clocks = <&ccu CLK_BUS_UART3>;
931			resets = <&ccu RST_BUS_UART3>;
932			status = "disabled";
933		};
934
935		uart4: serial@1c29000 {
936			compatible = "snps,dw-apb-uart";
937			reg = <0x01c29000 0x400>;
938			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
939			reg-shift = <2>;
940			reg-io-width = <4>;
941			clocks = <&ccu CLK_BUS_UART4>;
942			resets = <&ccu RST_BUS_UART4>;
943			status = "disabled";
944		};
945
946		i2c0: i2c@1c2ac00 {
947			compatible = "allwinner,sun6i-a31-i2c";
948			reg = <0x01c2ac00 0x400>;
949			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
950			clocks = <&ccu CLK_BUS_I2C0>;
951			resets = <&ccu RST_BUS_I2C0>;
952			pinctrl-names = "default";
953			pinctrl-0 = <&i2c0_pins>;
954			status = "disabled";
955			#address-cells = <1>;
956			#size-cells = <0>;
957		};
958
959		i2c1: i2c@1c2b000 {
960			compatible = "allwinner,sun6i-a31-i2c";
961			reg = <0x01c2b000 0x400>;
962			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
963			clocks = <&ccu CLK_BUS_I2C1>;
964			resets = <&ccu RST_BUS_I2C1>;
965			pinctrl-names = "default";
966			pinctrl-0 = <&i2c1_pins>;
967			status = "disabled";
968			#address-cells = <1>;
969			#size-cells = <0>;
970		};
971
972		i2c2: i2c@1c2b400 {
973			compatible = "allwinner,sun6i-a31-i2c";
974			reg = <0x01c2b400 0x400>;
975			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
976			clocks = <&ccu CLK_BUS_I2C2>;
977			resets = <&ccu RST_BUS_I2C2>;
978			pinctrl-names = "default";
979			pinctrl-0 = <&i2c2_pins>;
980			status = "disabled";
981			#address-cells = <1>;
982			#size-cells = <0>;
983		};
984
985		spi0: spi@1c68000 {
986			compatible = "allwinner,sun8i-h3-spi";
987			reg = <0x01c68000 0x1000>;
988			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
989			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
990			clock-names = "ahb", "mod";
991			dmas = <&dma 23>, <&dma 23>;
992			dma-names = "rx", "tx";
993			pinctrl-names = "default";
994			pinctrl-0 = <&spi0_pins>;
995			resets = <&ccu RST_BUS_SPI0>;
996			status = "disabled";
997			num-cs = <1>;
998			#address-cells = <1>;
999			#size-cells = <0>;
1000		};
1001
1002		spi1: spi@1c69000 {
1003			compatible = "allwinner,sun8i-h3-spi";
1004			reg = <0x01c69000 0x1000>;
1005			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1006			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1007			clock-names = "ahb", "mod";
1008			dmas = <&dma 24>, <&dma 24>;
1009			dma-names = "rx", "tx";
1010			pinctrl-names = "default";
1011			pinctrl-0 = <&spi1_pins>;
1012			resets = <&ccu RST_BUS_SPI1>;
1013			status = "disabled";
1014			num-cs = <1>;
1015			#address-cells = <1>;
1016			#size-cells = <0>;
1017		};
1018
1019		emac: ethernet@1c30000 {
1020			compatible = "allwinner,sun50i-a64-emac";
1021			syscon = <&syscon>;
1022			reg = <0x01c30000 0x10000>;
1023			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1024			interrupt-names = "macirq";
1025			resets = <&ccu RST_BUS_EMAC>;
1026			reset-names = "stmmaceth";
1027			clocks = <&ccu CLK_BUS_EMAC>;
1028			clock-names = "stmmaceth";
1029			status = "disabled";
1030
1031			mdio: mdio {
1032				compatible = "snps,dwmac-mdio";
1033				#address-cells = <1>;
1034				#size-cells = <0>;
1035			};
1036		};
1037
1038		mali: gpu@1c40000 {
1039			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1040			reg = <0x01c40000 0x10000>;
1041			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1042				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1043				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1044				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1045				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1046				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1047				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1048			interrupt-names = "gp",
1049					  "gpmmu",
1050					  "pp0",
1051					  "ppmmu0",
1052					  "pp1",
1053					  "ppmmu1",
1054					  "pmu";
1055			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1056			clock-names = "bus", "core";
1057			resets = <&ccu RST_BUS_GPU>;
1058		};
1059
1060		gic: interrupt-controller@1c81000 {
1061			compatible = "arm,gic-400";
1062			reg = <0x01c81000 0x1000>,
1063			      <0x01c82000 0x2000>,
1064			      <0x01c84000 0x2000>,
1065			      <0x01c86000 0x2000>;
1066			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1067			interrupt-controller;
1068			#interrupt-cells = <3>;
1069		};
1070
1071		pwm: pwm@1c21400 {
1072			compatible = "allwinner,sun50i-a64-pwm",
1073				     "allwinner,sun5i-a13-pwm";
1074			reg = <0x01c21400 0x400>;
1075			clocks = <&osc24M>;
1076			pinctrl-names = "default";
1077			pinctrl-0 = <&pwm_pin>;
1078			#pwm-cells = <3>;
1079			status = "disabled";
1080		};
1081
1082		mbus: dram-controller@1c62000 {
1083			compatible = "allwinner,sun50i-a64-mbus";
1084			reg = <0x01c62000 0x1000>;
1085			clocks = <&ccu 112>;
1086			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1087			#interconnect-cells = <1>;
1088		};
1089
1090		csi: csi@1cb0000 {
1091			compatible = "allwinner,sun50i-a64-csi";
1092			reg = <0x01cb0000 0x1000>;
1093			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1094			clocks = <&ccu CLK_BUS_CSI>,
1095				 <&ccu CLK_CSI_SCLK>,
1096				 <&ccu CLK_DRAM_CSI>;
1097			clock-names = "bus", "mod", "ram";
1098			resets = <&ccu RST_BUS_CSI>;
1099			pinctrl-names = "default";
1100			pinctrl-0 = <&csi_pins>;
1101			status = "disabled";
1102		};
1103
1104		dsi: dsi@1ca0000 {
1105			compatible = "allwinner,sun50i-a64-mipi-dsi";
1106			reg = <0x01ca0000 0x1000>;
1107			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1108			clocks = <&ccu CLK_BUS_MIPI_DSI>;
1109			resets = <&ccu RST_BUS_MIPI_DSI>;
1110			phys = <&dphy>;
1111			phy-names = "dphy";
1112			status = "disabled";
1113			#address-cells = <1>;
1114			#size-cells = <0>;
1115
1116			port {
1117				dsi_in_tcon0: endpoint {
1118					remote-endpoint = <&tcon0_out_dsi>;
1119				};
1120			};
1121		};
1122
1123		dphy: d-phy@1ca1000 {
1124			compatible = "allwinner,sun50i-a64-mipi-dphy",
1125				     "allwinner,sun6i-a31-mipi-dphy";
1126			reg = <0x01ca1000 0x1000>;
1127			clocks = <&ccu CLK_BUS_MIPI_DSI>,
1128				 <&ccu CLK_DSI_DPHY>;
1129			clock-names = "bus", "mod";
1130			resets = <&ccu RST_BUS_MIPI_DSI>;
1131			status = "disabled";
1132			#phy-cells = <0>;
1133		};
1134
1135		deinterlace: deinterlace@1e00000 {
1136			compatible = "allwinner,sun50i-a64-deinterlace",
1137				     "allwinner,sun8i-h3-deinterlace";
1138			reg = <0x01e00000 0x20000>;
1139			clocks = <&ccu CLK_BUS_DEINTERLACE>,
1140				 <&ccu CLK_DEINTERLACE>,
1141				 <&ccu CLK_DRAM_DEINTERLACE>;
1142			clock-names = "bus", "mod", "ram";
1143			resets = <&ccu RST_BUS_DEINTERLACE>;
1144			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1145			interconnects = <&mbus 9>;
1146			interconnect-names = "dma-mem";
1147		};
1148
1149		hdmi: hdmi@1ee0000 {
1150			compatible = "allwinner,sun50i-a64-dw-hdmi",
1151				     "allwinner,sun8i-a83t-dw-hdmi";
1152			reg = <0x01ee0000 0x10000>;
1153			reg-io-width = <1>;
1154			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1155			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1156				 <&ccu CLK_HDMI>;
1157			clock-names = "iahb", "isfr", "tmds";
1158			resets = <&ccu RST_BUS_HDMI1>;
1159			reset-names = "ctrl";
1160			phys = <&hdmi_phy>;
1161			phy-names = "phy";
1162			status = "disabled";
1163
1164			ports {
1165				#address-cells = <1>;
1166				#size-cells = <0>;
1167
1168				hdmi_in: port@0 {
1169					reg = <0>;
1170
1171					hdmi_in_tcon1: endpoint {
1172						remote-endpoint = <&tcon1_out_hdmi>;
1173					};
1174				};
1175
1176				hdmi_out: port@1 {
1177					reg = <1>;
1178				};
1179			};
1180		};
1181
1182		hdmi_phy: hdmi-phy@1ef0000 {
1183			compatible = "allwinner,sun50i-a64-hdmi-phy";
1184			reg = <0x01ef0000 0x10000>;
1185			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1186				 <&ccu CLK_PLL_VIDEO0>;
1187			clock-names = "bus", "mod", "pll-0";
1188			resets = <&ccu RST_BUS_HDMI0>;
1189			reset-names = "phy";
1190			#phy-cells = <0>;
1191		};
1192
1193		rtc: rtc@1f00000 {
1194			compatible = "allwinner,sun50i-a64-rtc",
1195				     "allwinner,sun8i-h3-rtc";
1196			reg = <0x01f00000 0x400>;
1197			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1198				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1199			clock-output-names = "osc32k", "osc32k-out", "iosc";
1200			clocks = <&osc32k>;
1201			#clock-cells = <1>;
1202		};
1203
1204		r_intc: interrupt-controller@1f00c00 {
1205			compatible = "allwinner,sun50i-a64-r-intc",
1206				     "allwinner,sun6i-a31-r-intc";
1207			interrupt-controller;
1208			#interrupt-cells = <2>;
1209			reg = <0x01f00c00 0x400>;
1210			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1211		};
1212
1213		r_ccu: clock@1f01400 {
1214			compatible = "allwinner,sun50i-a64-r-ccu";
1215			reg = <0x01f01400 0x100>;
1216			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1217				 <&ccu CLK_PLL_PERIPH0>;
1218			clock-names = "hosc", "losc", "iosc", "pll-periph";
1219			#clock-cells = <1>;
1220			#reset-cells = <1>;
1221		};
1222
1223		codec_analog: codec-analog@1f015c0 {
1224			compatible = "allwinner,sun50i-a64-codec-analog";
1225			reg = <0x01f015c0 0x4>;
1226			status = "disabled";
1227		};
1228
1229		r_i2c: i2c@1f02400 {
1230			compatible = "allwinner,sun50i-a64-i2c",
1231				     "allwinner,sun6i-a31-i2c";
1232			reg = <0x01f02400 0x400>;
1233			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1234			clocks = <&r_ccu CLK_APB0_I2C>;
1235			resets = <&r_ccu RST_APB0_I2C>;
1236			status = "disabled";
1237			#address-cells = <1>;
1238			#size-cells = <0>;
1239		};
1240
1241		r_ir: ir@1f02000 {
1242			compatible = "allwinner,sun50i-a64-ir",
1243				     "allwinner,sun6i-a31-ir";
1244			reg = <0x01f02000 0x400>;
1245			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1246			clock-names = "apb", "ir";
1247			resets = <&r_ccu RST_APB0_IR>;
1248			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1249			pinctrl-names = "default";
1250			pinctrl-0 = <&r_ir_rx_pin>;
1251			status = "disabled";
1252		};
1253
1254		r_pwm: pwm@1f03800 {
1255			compatible = "allwinner,sun50i-a64-pwm",
1256				     "allwinner,sun5i-a13-pwm";
1257			reg = <0x01f03800 0x400>;
1258			clocks = <&osc24M>;
1259			pinctrl-names = "default";
1260			pinctrl-0 = <&r_pwm_pin>;
1261			#pwm-cells = <3>;
1262			status = "disabled";
1263		};
1264
1265		r_pio: pinctrl@1f02c00 {
1266			compatible = "allwinner,sun50i-a64-r-pinctrl";
1267			reg = <0x01f02c00 0x400>;
1268			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1269			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1270			clock-names = "apb", "hosc", "losc";
1271			gpio-controller;
1272			#gpio-cells = <3>;
1273			interrupt-controller;
1274			#interrupt-cells = <3>;
1275
1276			r_i2c_pl89_pins: r-i2c-pl89-pins {
1277				pins = "PL8", "PL9";
1278				function = "s_i2c";
1279			};
1280
1281			r_ir_rx_pin: r-ir-rx-pin {
1282				pins = "PL11";
1283				function = "s_cir_rx";
1284			};
1285
1286			r_pwm_pin: r-pwm-pin {
1287				pins = "PL10";
1288				function = "s_pwm";
1289			};
1290
1291			r_rsb_pins: r-rsb-pins {
1292				pins = "PL0", "PL1";
1293				function = "s_rsb";
1294			};
1295		};
1296
1297		r_rsb: rsb@1f03400 {
1298			compatible = "allwinner,sun8i-a23-rsb";
1299			reg = <0x01f03400 0x400>;
1300			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1301			clocks = <&r_ccu 6>;
1302			clock-frequency = <3000000>;
1303			resets = <&r_ccu 2>;
1304			pinctrl-names = "default";
1305			pinctrl-0 = <&r_rsb_pins>;
1306			status = "disabled";
1307			#address-cells = <1>;
1308			#size-cells = <0>;
1309		};
1310
1311		wdt0: watchdog@1c20ca0 {
1312			compatible = "allwinner,sun50i-a64-wdt",
1313				     "allwinner,sun6i-a31-wdt";
1314			reg = <0x01c20ca0 0x20>;
1315			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1316			clocks = <&osc24M>;
1317		};
1318	};
1319};
1320