1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 15 /* 16 * While not explicitly listed in the TLFS, Hyper-V always runs with a page size 17 * of 4096. These definitions are used when communicating with Hyper-V using 18 * guest physical pages and guest physical page addresses, since the guest page 19 * size may not be 4096 on all architectures. 20 */ 21 #define HV_HYP_PAGE_SHIFT 12 22 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 23 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 24 25 /* 26 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 27 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 28 */ 29 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 30 #define HYPERV_CPUID_INTERFACE 0x40000001 31 #define HYPERV_CPUID_VERSION 0x40000002 32 #define HYPERV_CPUID_FEATURES 0x40000003 33 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 34 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 35 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 36 37 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 38 #define HYPERV_CPUID_MIN 0x40000005 39 #define HYPERV_CPUID_MAX 0x4000ffff 40 41 /* 42 * Feature identification. EAX indicates which features are available 43 * to the partition based upon the current partition privileges. 44 * These are HYPERV_CPUID_FEATURES.EAX bits. 45 */ 46 47 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 48 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0) 49 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 50 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 51 /* 52 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 53 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 54 */ 55 #define HV_X64_MSR_SYNIC_AVAILABLE BIT(2) 56 /* 57 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 58 * HV_X64_MSR_STIMER3_COUNT) available 59 */ 60 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 61 /* 62 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 63 * are available 64 */ 65 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4) 66 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 67 #define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5) 68 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 69 #define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6) 70 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 71 #define HV_X64_MSR_RESET_AVAILABLE BIT(7) 72 /* 73 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 74 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 75 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 76 */ 77 #define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8) 78 /* Partition reference TSC MSR is available */ 79 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 80 /* Partition Guest IDLE MSR is available */ 81 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10) 82 /* 83 * There is a single feature flag that signifies if the partition has access 84 * to MSRs with local APIC and TSC frequencies. 85 */ 86 #define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11) 87 /* AccessReenlightenmentControls privilege */ 88 #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) 89 90 /* 91 * Feature identification: indicates which flags were specified at partition 92 * creation. The format is the same as the partition creation flag structure 93 * defined in section Partition Creation Flags. 94 * These are HYPERV_CPUID_FEATURES.EBX bits. 95 */ 96 #define HV_X64_CREATE_PARTITIONS BIT(0) 97 #define HV_X64_ACCESS_PARTITION_ID BIT(1) 98 #define HV_X64_ACCESS_MEMORY_POOL BIT(2) 99 #define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3) 100 #define HV_X64_POST_MESSAGES BIT(4) 101 #define HV_X64_SIGNAL_EVENTS BIT(5) 102 #define HV_X64_CREATE_PORT BIT(6) 103 #define HV_X64_CONNECT_PORT BIT(7) 104 #define HV_X64_ACCESS_STATS BIT(8) 105 #define HV_X64_DEBUGGING BIT(11) 106 #define HV_X64_CPU_POWER_MANAGEMENT BIT(12) 107 108 /* 109 * Feature identification. EDX indicates which miscellaneous features 110 * are available to the partition. 111 * These are HYPERV_CPUID_FEATURES.EDX bits. 112 */ 113 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 114 #define HV_X64_MWAIT_AVAILABLE BIT(0) 115 /* Guest debugging support is available */ 116 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 117 /* Performance Monitor support is available*/ 118 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 119 /* Support for physical CPU dynamic partitioning events is available*/ 120 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 121 /* 122 * Support for passing hypercall input parameter block via XMM 123 * registers is available 124 */ 125 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) 126 /* Support for a virtual guest idle state is available */ 127 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 128 /* Frequency MSRs available */ 129 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 130 /* Crash MSR available */ 131 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 132 /* stimer Direct Mode is available */ 133 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 134 135 /* 136 * Implementation recommendations. Indicates which behaviors the hypervisor 137 * recommends the OS implement for optimal performance. 138 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 139 */ 140 /* 141 * Recommend using hypercall for address space switches rather 142 * than MOV to CR3 instruction 143 */ 144 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 145 /* Recommend using hypercall for local TLB flushes rather 146 * than INVLPG or MOV to CR3 instructions */ 147 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 148 /* 149 * Recommend using hypercall for remote TLB flushes rather 150 * than inter-processor interrupts 151 */ 152 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 153 /* 154 * Recommend using MSRs for accessing APIC registers 155 * EOI, ICR and TPR rather than their memory-mapped counterparts 156 */ 157 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 158 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 159 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 160 /* 161 * Recommend using relaxed timing for this partition. If used, 162 * the VM should disable any watchdog timeouts that rely on the 163 * timely delivery of external interrupts 164 */ 165 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 166 167 /* 168 * Recommend not using Auto End-Of-Interrupt feature 169 */ 170 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 171 172 /* 173 * Recommend using cluster IPI hypercalls. 174 */ 175 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 176 177 /* Recommend using the newer ExProcessorMasks interface */ 178 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 179 180 /* Recommend using enlightened VMCS */ 181 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 182 183 /* 184 * Virtual processor will never share a physical core with another virtual 185 * processor, except for virtual processors that are reported as sibling SMT 186 * threads. 187 */ 188 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 189 190 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 191 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 192 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 193 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 194 195 /* Hyper-V specific model specific registers (MSRs) */ 196 197 /* MSR used to identify the guest OS. */ 198 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 199 200 /* MSR used to setup pages used to communicate with the hypervisor. */ 201 #define HV_X64_MSR_HYPERCALL 0x40000001 202 203 /* MSR used to provide vcpu index */ 204 #define HV_X64_MSR_VP_INDEX 0x40000002 205 206 /* MSR used to reset the guest OS. */ 207 #define HV_X64_MSR_RESET 0x40000003 208 209 /* MSR used to provide vcpu runtime in 100ns units */ 210 #define HV_X64_MSR_VP_RUNTIME 0x40000010 211 212 /* MSR used to read the per-partition time reference counter */ 213 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 214 215 /* A partition's reference time stamp counter (TSC) page */ 216 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 217 218 /* MSR used to retrieve the TSC frequency */ 219 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 220 221 /* MSR used to retrieve the local APIC timer frequency */ 222 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 223 224 /* Define the virtual APIC registers */ 225 #define HV_X64_MSR_EOI 0x40000070 226 #define HV_X64_MSR_ICR 0x40000071 227 #define HV_X64_MSR_TPR 0x40000072 228 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 229 230 /* Define synthetic interrupt controller model specific registers. */ 231 #define HV_X64_MSR_SCONTROL 0x40000080 232 #define HV_X64_MSR_SVERSION 0x40000081 233 #define HV_X64_MSR_SIEFP 0x40000082 234 #define HV_X64_MSR_SIMP 0x40000083 235 #define HV_X64_MSR_EOM 0x40000084 236 #define HV_X64_MSR_SINT0 0x40000090 237 #define HV_X64_MSR_SINT1 0x40000091 238 #define HV_X64_MSR_SINT2 0x40000092 239 #define HV_X64_MSR_SINT3 0x40000093 240 #define HV_X64_MSR_SINT4 0x40000094 241 #define HV_X64_MSR_SINT5 0x40000095 242 #define HV_X64_MSR_SINT6 0x40000096 243 #define HV_X64_MSR_SINT7 0x40000097 244 #define HV_X64_MSR_SINT8 0x40000098 245 #define HV_X64_MSR_SINT9 0x40000099 246 #define HV_X64_MSR_SINT10 0x4000009A 247 #define HV_X64_MSR_SINT11 0x4000009B 248 #define HV_X64_MSR_SINT12 0x4000009C 249 #define HV_X64_MSR_SINT13 0x4000009D 250 #define HV_X64_MSR_SINT14 0x4000009E 251 #define HV_X64_MSR_SINT15 0x4000009F 252 253 /* 254 * Synthetic Timer MSRs. Four timers per vcpu. 255 */ 256 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 257 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 258 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 259 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 260 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 261 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 262 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 263 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 264 265 /* Hyper-V guest idle MSR */ 266 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 267 268 /* Hyper-V guest crash notification MSR's */ 269 #define HV_X64_MSR_CRASH_P0 0x40000100 270 #define HV_X64_MSR_CRASH_P1 0x40000101 271 #define HV_X64_MSR_CRASH_P2 0x40000102 272 #define HV_X64_MSR_CRASH_P3 0x40000103 273 #define HV_X64_MSR_CRASH_P4 0x40000104 274 #define HV_X64_MSR_CRASH_CTL 0x40000105 275 276 /* TSC emulation after migration */ 277 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 278 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 279 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 280 281 /* 282 * Declare the MSR used to setup pages used to communicate with the hypervisor. 283 */ 284 union hv_x64_msr_hypercall_contents { 285 u64 as_uint64; 286 struct { 287 u64 enable:1; 288 u64 reserved:11; 289 u64 guest_physical_address:52; 290 } __packed; 291 }; 292 293 /* 294 * TSC page layout. 295 */ 296 struct ms_hyperv_tsc_page { 297 volatile u32 tsc_sequence; 298 u32 reserved1; 299 volatile u64 tsc_scale; 300 volatile s64 tsc_offset; 301 u64 reserved2[509]; 302 } __packed; 303 304 /* 305 * The guest OS needs to register the guest ID with the hypervisor. 306 * The guest ID is a 64 bit entity and the structure of this ID is 307 * specified in the Hyper-V specification: 308 * 309 * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx 310 * 311 * While the current guideline does not specify how Linux guest ID(s) 312 * need to be generated, our plan is to publish the guidelines for 313 * Linux and other guest operating systems that currently are hosted 314 * on Hyper-V. The implementation here conforms to this yet 315 * unpublished guidelines. 316 * 317 * 318 * Bit(s) 319 * 63 - Indicates if the OS is Open Source or not; 1 is Open Source 320 * 62:56 - Os Type; Linux is 0x100 321 * 55:48 - Distro specific identification 322 * 47:16 - Linux kernel version number 323 * 15:0 - Distro specific identification 324 * 325 * 326 */ 327 328 #define HV_LINUX_VENDOR_ID 0x8100 329 330 struct hv_reenlightenment_control { 331 __u64 vector:8; 332 __u64 reserved1:8; 333 __u64 enabled:1; 334 __u64 reserved2:15; 335 __u64 target_vp:32; 336 } __packed; 337 338 struct hv_tsc_emulation_control { 339 __u64 enabled:1; 340 __u64 reserved:63; 341 } __packed; 342 343 struct hv_tsc_emulation_status { 344 __u64 inprogress:1; 345 __u64 reserved:63; 346 } __packed; 347 348 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 349 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 350 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 351 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 352 353 /* 354 * Crash notification (HV_X64_MSR_CRASH_CTL) flags. 355 */ 356 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 357 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 358 #define HV_X64_MSR_CRASH_PARAMS \ 359 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 360 361 #define HV_IPI_LOW_VECTOR 0x10 362 #define HV_IPI_HIGH_VECTOR 0xff 363 364 /* Declare the various hypercall operations. */ 365 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 366 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 367 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 368 #define HVCALL_SEND_IPI 0x000b 369 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 370 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 371 #define HVCALL_SEND_IPI_EX 0x0015 372 #define HVCALL_POST_MESSAGE 0x005c 373 #define HVCALL_SIGNAL_EVENT 0x005d 374 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 375 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 376 377 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 378 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 379 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 380 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 381 382 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 383 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 384 385 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 386 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 387 388 #define HV_PROCESSOR_POWER_STATE_C0 0 389 #define HV_PROCESSOR_POWER_STATE_C1 1 390 #define HV_PROCESSOR_POWER_STATE_C2 2 391 #define HV_PROCESSOR_POWER_STATE_C3 3 392 393 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 394 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 395 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 396 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 397 398 enum HV_GENERIC_SET_FORMAT { 399 HV_GENERIC_SET_SPARSE_4K, 400 HV_GENERIC_SET_ALL, 401 }; 402 403 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 404 #define HV_HYPERCALL_FAST_BIT BIT(16) 405 #define HV_HYPERCALL_VARHEAD_OFFSET 17 406 #define HV_HYPERCALL_REP_COMP_OFFSET 32 407 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 408 #define HV_HYPERCALL_REP_START_OFFSET 48 409 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 410 411 /* hypercall status code */ 412 #define HV_STATUS_SUCCESS 0 413 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 414 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 415 #define HV_STATUS_INVALID_ALIGNMENT 4 416 #define HV_STATUS_INVALID_PARAMETER 5 417 #define HV_STATUS_INSUFFICIENT_MEMORY 11 418 #define HV_STATUS_INVALID_PORT_ID 17 419 #define HV_STATUS_INVALID_CONNECTION_ID 18 420 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 421 422 /* 423 * The Hyper-V TimeRefCount register and the TSC 424 * page provide a guest VM clock with 100ns tick rate 425 */ 426 #define HV_CLOCK_HZ (NSEC_PER_SEC/100) 427 428 typedef struct _HV_REFERENCE_TSC_PAGE { 429 __u32 tsc_sequence; 430 __u32 res1; 431 __u64 tsc_scale; 432 __s64 tsc_offset; 433 } __packed HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 434 435 /* Define the number of synthetic interrupt sources. */ 436 #define HV_SYNIC_SINT_COUNT (16) 437 /* Define the expected SynIC version. */ 438 #define HV_SYNIC_VERSION_1 (0x1) 439 /* Valid SynIC vectors are 16-255. */ 440 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 441 442 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 443 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 444 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 445 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 446 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 447 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 448 449 #define HV_SYNIC_STIMER_COUNT (4) 450 451 /* Define synthetic interrupt controller message constants. */ 452 #define HV_MESSAGE_SIZE (256) 453 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 454 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 455 456 /* Define hypervisor message types. */ 457 enum hv_message_type { 458 HVMSG_NONE = 0x00000000, 459 460 /* Memory access messages. */ 461 HVMSG_UNMAPPED_GPA = 0x80000000, 462 HVMSG_GPA_INTERCEPT = 0x80000001, 463 464 /* Timer notification messages. */ 465 HVMSG_TIMER_EXPIRED = 0x80000010, 466 467 /* Error messages. */ 468 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 469 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 470 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 471 472 /* Trace buffer complete messages. */ 473 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 474 475 /* Platform-specific processor intercept messages. */ 476 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 477 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 478 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 479 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 480 HVMSG_X64_APIC_EOI = 0x80010004, 481 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 482 }; 483 484 /* Define synthetic interrupt controller message flags. */ 485 union hv_message_flags { 486 __u8 asu8; 487 struct { 488 __u8 msg_pending:1; 489 __u8 reserved:7; 490 } __packed; 491 }; 492 493 /* Define port identifier type. */ 494 union hv_port_id { 495 __u32 asu32; 496 struct { 497 __u32 id:24; 498 __u32 reserved:8; 499 } __packed u; 500 }; 501 502 /* Define synthetic interrupt controller message header. */ 503 struct hv_message_header { 504 __u32 message_type; 505 __u8 payload_size; 506 union hv_message_flags message_flags; 507 __u8 reserved[2]; 508 union { 509 __u64 sender; 510 union hv_port_id port; 511 }; 512 } __packed; 513 514 /* Define synthetic interrupt controller message format. */ 515 struct hv_message { 516 struct hv_message_header header; 517 union { 518 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 519 } u; 520 } __packed; 521 522 /* Define the synthetic interrupt message page layout. */ 523 struct hv_message_page { 524 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 525 } __packed; 526 527 /* Define timer message payload structure. */ 528 struct hv_timer_message_payload { 529 __u32 timer_index; 530 __u32 reserved; 531 __u64 expiration_time; /* When the timer expired */ 532 __u64 delivery_time; /* When the message was delivered */ 533 } __packed; 534 535 struct hv_nested_enlightenments_control { 536 struct { 537 __u32 directhypercall:1; 538 __u32 reserved:31; 539 } features; 540 struct { 541 __u32 reserved; 542 } hypercallControls; 543 } __packed; 544 545 /* Define virtual processor assist page structure. */ 546 struct hv_vp_assist_page { 547 __u32 apic_assist; 548 __u32 reserved1; 549 __u64 vtl_control[3]; 550 struct hv_nested_enlightenments_control nested_control; 551 __u8 enlighten_vmentry; 552 __u8 reserved2[7]; 553 __u64 current_nested_vmcs; 554 } __packed; 555 556 struct hv_enlightened_vmcs { 557 u32 revision_id; 558 u32 abort; 559 560 u16 host_es_selector; 561 u16 host_cs_selector; 562 u16 host_ss_selector; 563 u16 host_ds_selector; 564 u16 host_fs_selector; 565 u16 host_gs_selector; 566 u16 host_tr_selector; 567 568 u16 padding16_1; 569 570 u64 host_ia32_pat; 571 u64 host_ia32_efer; 572 573 u64 host_cr0; 574 u64 host_cr3; 575 u64 host_cr4; 576 577 u64 host_ia32_sysenter_esp; 578 u64 host_ia32_sysenter_eip; 579 u64 host_rip; 580 u32 host_ia32_sysenter_cs; 581 582 u32 pin_based_vm_exec_control; 583 u32 vm_exit_controls; 584 u32 secondary_vm_exec_control; 585 586 u64 io_bitmap_a; 587 u64 io_bitmap_b; 588 u64 msr_bitmap; 589 590 u16 guest_es_selector; 591 u16 guest_cs_selector; 592 u16 guest_ss_selector; 593 u16 guest_ds_selector; 594 u16 guest_fs_selector; 595 u16 guest_gs_selector; 596 u16 guest_ldtr_selector; 597 u16 guest_tr_selector; 598 599 u32 guest_es_limit; 600 u32 guest_cs_limit; 601 u32 guest_ss_limit; 602 u32 guest_ds_limit; 603 u32 guest_fs_limit; 604 u32 guest_gs_limit; 605 u32 guest_ldtr_limit; 606 u32 guest_tr_limit; 607 u32 guest_gdtr_limit; 608 u32 guest_idtr_limit; 609 610 u32 guest_es_ar_bytes; 611 u32 guest_cs_ar_bytes; 612 u32 guest_ss_ar_bytes; 613 u32 guest_ds_ar_bytes; 614 u32 guest_fs_ar_bytes; 615 u32 guest_gs_ar_bytes; 616 u32 guest_ldtr_ar_bytes; 617 u32 guest_tr_ar_bytes; 618 619 u64 guest_es_base; 620 u64 guest_cs_base; 621 u64 guest_ss_base; 622 u64 guest_ds_base; 623 u64 guest_fs_base; 624 u64 guest_gs_base; 625 u64 guest_ldtr_base; 626 u64 guest_tr_base; 627 u64 guest_gdtr_base; 628 u64 guest_idtr_base; 629 630 u64 padding64_1[3]; 631 632 u64 vm_exit_msr_store_addr; 633 u64 vm_exit_msr_load_addr; 634 u64 vm_entry_msr_load_addr; 635 636 u64 cr3_target_value0; 637 u64 cr3_target_value1; 638 u64 cr3_target_value2; 639 u64 cr3_target_value3; 640 641 u32 page_fault_error_code_mask; 642 u32 page_fault_error_code_match; 643 644 u32 cr3_target_count; 645 u32 vm_exit_msr_store_count; 646 u32 vm_exit_msr_load_count; 647 u32 vm_entry_msr_load_count; 648 649 u64 tsc_offset; 650 u64 virtual_apic_page_addr; 651 u64 vmcs_link_pointer; 652 653 u64 guest_ia32_debugctl; 654 u64 guest_ia32_pat; 655 u64 guest_ia32_efer; 656 657 u64 guest_pdptr0; 658 u64 guest_pdptr1; 659 u64 guest_pdptr2; 660 u64 guest_pdptr3; 661 662 u64 guest_pending_dbg_exceptions; 663 u64 guest_sysenter_esp; 664 u64 guest_sysenter_eip; 665 666 u32 guest_activity_state; 667 u32 guest_sysenter_cs; 668 669 u64 cr0_guest_host_mask; 670 u64 cr4_guest_host_mask; 671 u64 cr0_read_shadow; 672 u64 cr4_read_shadow; 673 u64 guest_cr0; 674 u64 guest_cr3; 675 u64 guest_cr4; 676 u64 guest_dr7; 677 678 u64 host_fs_base; 679 u64 host_gs_base; 680 u64 host_tr_base; 681 u64 host_gdtr_base; 682 u64 host_idtr_base; 683 u64 host_rsp; 684 685 u64 ept_pointer; 686 687 u16 virtual_processor_id; 688 u16 padding16_2[3]; 689 690 u64 padding64_2[5]; 691 u64 guest_physical_address; 692 693 u32 vm_instruction_error; 694 u32 vm_exit_reason; 695 u32 vm_exit_intr_info; 696 u32 vm_exit_intr_error_code; 697 u32 idt_vectoring_info_field; 698 u32 idt_vectoring_error_code; 699 u32 vm_exit_instruction_len; 700 u32 vmx_instruction_info; 701 702 u64 exit_qualification; 703 u64 exit_io_instruction_ecx; 704 u64 exit_io_instruction_esi; 705 u64 exit_io_instruction_edi; 706 u64 exit_io_instruction_eip; 707 708 u64 guest_linear_address; 709 u64 guest_rsp; 710 u64 guest_rflags; 711 712 u32 guest_interruptibility_info; 713 u32 cpu_based_vm_exec_control; 714 u32 exception_bitmap; 715 u32 vm_entry_controls; 716 u32 vm_entry_intr_info_field; 717 u32 vm_entry_exception_error_code; 718 u32 vm_entry_instruction_len; 719 u32 tpr_threshold; 720 721 u64 guest_rip; 722 723 u32 hv_clean_fields; 724 u32 hv_padding_32; 725 u32 hv_synthetic_controls; 726 struct { 727 u32 nested_flush_hypercall:1; 728 u32 msr_bitmap:1; 729 u32 reserved:30; 730 } __packed hv_enlightenments_control; 731 u32 hv_vp_id; 732 733 u64 hv_vm_id; 734 u64 partition_assist_page; 735 u64 padding64_4[4]; 736 u64 guest_bndcfgs; 737 u64 padding64_5[7]; 738 u64 xss_exit_bitmap; 739 u64 padding64_6[7]; 740 } __packed; 741 742 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 743 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 744 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 745 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 746 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 747 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 748 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 749 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 750 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 751 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 752 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 753 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 754 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 755 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 756 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 757 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 758 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 759 760 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 761 762 /* Define synthetic interrupt controller flag constants. */ 763 #define HV_EVENT_FLAGS_COUNT (256 * 8) 764 #define HV_EVENT_FLAGS_LONG_COUNT (256 / sizeof(unsigned long)) 765 766 /* 767 * Synthetic timer configuration. 768 */ 769 union hv_stimer_config { 770 u64 as_uint64; 771 struct { 772 u64 enable:1; 773 u64 periodic:1; 774 u64 lazy:1; 775 u64 auto_enable:1; 776 u64 apic_vector:8; 777 u64 direct_mode:1; 778 u64 reserved_z0:3; 779 u64 sintx:4; 780 u64 reserved_z1:44; 781 } __packed; 782 }; 783 784 785 /* Define the synthetic interrupt controller event flags format. */ 786 union hv_synic_event_flags { 787 unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT]; 788 }; 789 790 /* Define SynIC control register. */ 791 union hv_synic_scontrol { 792 u64 as_uint64; 793 struct { 794 u64 enable:1; 795 u64 reserved:63; 796 } __packed; 797 }; 798 799 /* Define synthetic interrupt source. */ 800 union hv_synic_sint { 801 u64 as_uint64; 802 struct { 803 u64 vector:8; 804 u64 reserved1:8; 805 u64 masked:1; 806 u64 auto_eoi:1; 807 u64 reserved2:46; 808 } __packed; 809 }; 810 811 /* Define the format of the SIMP register */ 812 union hv_synic_simp { 813 u64 as_uint64; 814 struct { 815 u64 simp_enabled:1; 816 u64 preserved:11; 817 u64 base_simp_gpa:52; 818 } __packed; 819 }; 820 821 /* Define the format of the SIEFP register */ 822 union hv_synic_siefp { 823 u64 as_uint64; 824 struct { 825 u64 siefp_enabled:1; 826 u64 preserved:11; 827 u64 base_siefp_gpa:52; 828 } __packed; 829 }; 830 831 struct hv_vpset { 832 u64 format; 833 u64 valid_bank_mask; 834 u64 bank_contents[]; 835 } __packed; 836 837 /* HvCallSendSyntheticClusterIpi hypercall */ 838 struct hv_send_ipi { 839 u32 vector; 840 u32 reserved; 841 u64 cpu_mask; 842 } __packed; 843 844 /* HvCallSendSyntheticClusterIpiEx hypercall */ 845 struct hv_send_ipi_ex { 846 u32 vector; 847 u32 reserved; 848 struct hv_vpset vp_set; 849 } __packed; 850 851 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 852 struct hv_guest_mapping_flush { 853 u64 address_space; 854 u64 flags; 855 } __packed; 856 857 /* 858 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 859 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 860 */ 861 #define HV_MAX_FLUSH_PAGES (2048) 862 863 /* HvFlushGuestPhysicalAddressList hypercall */ 864 union hv_gpa_page_range { 865 u64 address_space; 866 struct { 867 u64 additional_pages:11; 868 u64 largepage:1; 869 u64 basepfn:52; 870 } page; 871 }; 872 873 /* 874 * All input flush parameters should be in single page. The max flush 875 * count is equal with how many entries of union hv_gpa_page_range can 876 * be populated into the input parameter page. 877 */ 878 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 879 sizeof(union hv_gpa_page_range)) 880 881 struct hv_guest_mapping_flush_list { 882 u64 address_space; 883 u64 flags; 884 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 885 }; 886 887 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */ 888 struct hv_tlb_flush { 889 u64 address_space; 890 u64 flags; 891 u64 processor_mask; 892 u64 gva_list[]; 893 } __packed; 894 895 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 896 struct hv_tlb_flush_ex { 897 u64 address_space; 898 u64 flags; 899 struct hv_vpset hv_vp_set; 900 u64 gva_list[]; 901 } __packed; 902 903 struct hv_partition_assist_pg { 904 u32 tlb_lock_count; 905 }; 906 #endif 907