1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/spi-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: SPI Controller Generic Binding 8 9maintainers: 10 - Mark Brown <broonie@kernel.org> 11 12description: | 13 SPI busses can be described with a node for the SPI controller device 14 and a set of child nodes for each SPI slave on the bus. The system SPI 15 controller may be described for use in SPI master mode or in SPI slave mode, 16 but not for both at the same time. 17 18properties: 19 $nodename: 20 pattern: "^spi(@.*|-[0-9a-f])*$" 21 22 "#address-cells": 23 const: 1 24 25 "#size-cells": 26 const: 0 27 28 cs-gpios: 29 description: | 30 GPIOs used as chip selects. 31 If that property is used, the number of chip selects will be 32 increased automatically with max(cs-gpios, hardware chip selects). 33 34 So if, for example, the controller has 4 CS lines, and the 35 cs-gpios looks like this 36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; 37 38 Then it should be configured so that num_chipselect = 4, with 39 the following mapping 40 cs0 : &gpio1 0 0 41 cs1 : native 42 cs2 : &gpio1 1 0 43 cs3 : &gpio1 2 0 44 45 num-cs: 46 $ref: /schemas/types.yaml#/definitions/uint32 47 description: 48 Total number of chip selects. 49 50 spi-slave: 51 $ref: /schemas/types.yaml#/definitions/flag 52 description: 53 The SPI controller acts as a slave, instead of a master. 54 55patternProperties: 56 "^slave$": 57 type: object 58 59 properties: 60 compatible: 61 description: 62 Compatible of the SPI device. 63 64 required: 65 - compatible 66 67 "^.*@[0-9a-f]+$": 68 type: object 69 70 properties: 71 compatible: 72 description: 73 Compatible of the SPI device. 74 75 reg: 76 minimum: 0 77 maximum: 256 78 description: 79 Chip select used by the device. 80 81 spi-3wire: 82 $ref: /schemas/types.yaml#/definitions/flag 83 description: 84 The device requires 3-wire mode. 85 86 spi-cpha: 87 $ref: /schemas/types.yaml#/definitions/flag 88 description: 89 The device requires shifted clock phase (CPHA) mode. 90 91 spi-cpol: 92 $ref: /schemas/types.yaml#/definitions/flag 93 description: 94 The device requires inverse clock polarity (CPOL) mode. 95 96 spi-cs-high: 97 $ref: /schemas/types.yaml#/definitions/flag 98 description: 99 The device requires the chip select active high. 100 101 spi-lsb-first: 102 $ref: /schemas/types.yaml#/definitions/flag 103 description: 104 The device requires the LSB first mode. 105 106 spi-max-frequency: 107 $ref: /schemas/types.yaml#/definitions/uint32 108 description: 109 Maximum SPI clocking speed of the device in Hz. 110 111 spi-rx-bus-width: 112 allOf: 113 - $ref: /schemas/types.yaml#/definitions/uint32 114 - enum: [ 1, 2, 4, 8 ] 115 - default: 1 116 description: 117 Bus width to the SPI bus used for MISO. 118 119 spi-rx-delay-us: 120 description: 121 Delay, in microseconds, after a read transfer. 122 123 spi-tx-bus-width: 124 allOf: 125 - $ref: /schemas/types.yaml#/definitions/uint32 126 - enum: [ 1, 2, 4, 8 ] 127 - default: 1 128 description: 129 Bus width to the SPI bus used for MOSI. 130 131 spi-tx-delay-us: 132 description: 133 Delay, in microseconds, after a write transfer. 134 135 required: 136 - compatible 137 - reg 138 139examples: 140 - | 141 spi@f00 { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 145 reg = <0xf00 0x20>; 146 interrupts = <2 13 0 2 14 0>; 147 interrupt-parent = <&mpc5200_pic>; 148 149 ethernet-switch@0 { 150 compatible = "micrel,ks8995m"; 151 spi-max-frequency = <1000000>; 152 reg = <0>; 153 }; 154 155 codec@1 { 156 compatible = "ti,tlv320aic26"; 157 spi-max-frequency = <100000>; 158 reg = <1>; 159 }; 160 }; 161