1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * LTC2632 Digital to analog convertors spi driver 4 * 5 * Copyright 2017 Maxime Roussin-Bélanger 6 * expanded by Silvan Murer <silvan.murer@gmail.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/spi/spi.h> 11 #include <linux/module.h> 12 #include <linux/iio/iio.h> 13 #include <linux/regulator/consumer.h> 14 15 #define LTC2632_CMD_WRITE_INPUT_N 0x0 16 #define LTC2632_CMD_UPDATE_DAC_N 0x1 17 #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2 18 #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_N 0x3 19 #define LTC2632_CMD_POWERDOWN_DAC_N 0x4 20 #define LTC2632_CMD_POWERDOWN_CHIP 0x5 21 #define LTC2632_CMD_INTERNAL_REFER 0x6 22 #define LTC2632_CMD_EXTERNAL_REFER 0x7 23 24 /** 25 * struct ltc2632_chip_info - chip specific information 26 * @channels: channel spec for the DAC 27 * @vref_mv: internal reference voltage 28 */ 29 struct ltc2632_chip_info { 30 const struct iio_chan_spec *channels; 31 const size_t num_channels; 32 const int vref_mv; 33 }; 34 35 /** 36 * struct ltc2632_state - driver instance specific data 37 * @spi_dev: pointer to the spi_device struct 38 * @powerdown_cache_mask used to show current channel powerdown state 39 * @vref_mv used reference voltage (internal or external) 40 * @vref_reg regulator for the reference voltage 41 */ 42 struct ltc2632_state { 43 struct spi_device *spi_dev; 44 unsigned int powerdown_cache_mask; 45 int vref_mv; 46 struct regulator *vref_reg; 47 }; 48 49 enum ltc2632_supported_device_ids { 50 ID_LTC2632L12, 51 ID_LTC2632L10, 52 ID_LTC2632L8, 53 ID_LTC2632H12, 54 ID_LTC2632H10, 55 ID_LTC2632H8, 56 ID_LTC2636L12, 57 ID_LTC2636L10, 58 ID_LTC2636L8, 59 ID_LTC2636H12, 60 ID_LTC2636H10, 61 ID_LTC2636H8, 62 }; 63 64 static int ltc2632_spi_write(struct spi_device *spi, 65 u8 cmd, u8 addr, u16 val, u8 shift) 66 { 67 u32 data; 68 u8 msg[3]; 69 70 /* 71 * The input shift register is 24 bits wide. 72 * The next four are the command bits, C3 to C0, 73 * followed by the 4-bit DAC address, A3 to A0, and then the 74 * 12-, 10-, 8-bit data-word. The data-word comprises the 12-, 75 * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits. 76 */ 77 data = (cmd << 20) | (addr << 16) | (val << shift); 78 msg[0] = data >> 16; 79 msg[1] = data >> 8; 80 msg[2] = data; 81 82 return spi_write(spi, msg, sizeof(msg)); 83 } 84 85 static int ltc2632_read_raw(struct iio_dev *indio_dev, 86 struct iio_chan_spec const *chan, 87 int *val, 88 int *val2, 89 long m) 90 { 91 const struct ltc2632_state *st = iio_priv(indio_dev); 92 93 switch (m) { 94 case IIO_CHAN_INFO_SCALE: 95 *val = st->vref_mv; 96 *val2 = chan->scan_type.realbits; 97 return IIO_VAL_FRACTIONAL_LOG2; 98 } 99 return -EINVAL; 100 } 101 102 static int ltc2632_write_raw(struct iio_dev *indio_dev, 103 struct iio_chan_spec const *chan, 104 int val, 105 int val2, 106 long mask) 107 { 108 struct ltc2632_state *st = iio_priv(indio_dev); 109 110 switch (mask) { 111 case IIO_CHAN_INFO_RAW: 112 if (val >= (1 << chan->scan_type.realbits) || val < 0) 113 return -EINVAL; 114 115 return ltc2632_spi_write(st->spi_dev, 116 LTC2632_CMD_WRITE_INPUT_N_UPDATE_N, 117 chan->address, val, 118 chan->scan_type.shift); 119 default: 120 return -EINVAL; 121 } 122 } 123 124 static ssize_t ltc2632_read_dac_powerdown(struct iio_dev *indio_dev, 125 uintptr_t private, 126 const struct iio_chan_spec *chan, 127 char *buf) 128 { 129 struct ltc2632_state *st = iio_priv(indio_dev); 130 131 return sprintf(buf, "%d\n", 132 !!(st->powerdown_cache_mask & (1 << chan->channel))); 133 } 134 135 static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev, 136 uintptr_t private, 137 const struct iio_chan_spec *chan, 138 const char *buf, 139 size_t len) 140 { 141 bool pwr_down; 142 int ret; 143 struct ltc2632_state *st = iio_priv(indio_dev); 144 145 ret = strtobool(buf, &pwr_down); 146 if (ret) 147 return ret; 148 149 if (pwr_down) 150 st->powerdown_cache_mask |= (1 << chan->channel); 151 else 152 st->powerdown_cache_mask &= ~(1 << chan->channel); 153 154 ret = ltc2632_spi_write(st->spi_dev, 155 LTC2632_CMD_POWERDOWN_DAC_N, 156 chan->channel, 0, 0); 157 158 return ret ? ret : len; 159 } 160 161 static const struct iio_info ltc2632_info = { 162 .write_raw = ltc2632_write_raw, 163 .read_raw = ltc2632_read_raw, 164 }; 165 166 static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = { 167 { 168 .name = "powerdown", 169 .read = ltc2632_read_dac_powerdown, 170 .write = ltc2632_write_dac_powerdown, 171 .shared = IIO_SEPARATE, 172 }, 173 { }, 174 }; 175 176 #define LTC2632_CHANNEL(_chan, _bits) { \ 177 .type = IIO_VOLTAGE, \ 178 .indexed = 1, \ 179 .output = 1, \ 180 .channel = (_chan), \ 181 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 182 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 183 .address = (_chan), \ 184 .scan_type = { \ 185 .realbits = (_bits), \ 186 .shift = 16 - (_bits), \ 187 }, \ 188 .ext_info = ltc2632_ext_info, \ 189 } 190 191 #define DECLARE_LTC2632_CHANNELS(_name, _bits) \ 192 const struct iio_chan_spec _name ## _channels[] = { \ 193 LTC2632_CHANNEL(0, _bits), \ 194 LTC2632_CHANNEL(1, _bits), \ 195 LTC2632_CHANNEL(2, _bits), \ 196 LTC2632_CHANNEL(3, _bits), \ 197 LTC2632_CHANNEL(4, _bits), \ 198 LTC2632_CHANNEL(5, _bits), \ 199 LTC2632_CHANNEL(6, _bits), \ 200 LTC2632_CHANNEL(7, _bits), \ 201 } 202 203 static DECLARE_LTC2632_CHANNELS(ltc2632x12, 12); 204 static DECLARE_LTC2632_CHANNELS(ltc2632x10, 10); 205 static DECLARE_LTC2632_CHANNELS(ltc2632x8, 8); 206 207 static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = { 208 [ID_LTC2632L12] = { 209 .channels = ltc2632x12_channels, 210 .num_channels = 2, 211 .vref_mv = 2500, 212 }, 213 [ID_LTC2632L10] = { 214 .channels = ltc2632x10_channels, 215 .num_channels = 2, 216 .vref_mv = 2500, 217 }, 218 [ID_LTC2632L8] = { 219 .channels = ltc2632x8_channels, 220 .num_channels = 2, 221 .vref_mv = 2500, 222 }, 223 [ID_LTC2632H12] = { 224 .channels = ltc2632x12_channels, 225 .num_channels = 2, 226 .vref_mv = 4096, 227 }, 228 [ID_LTC2632H10] = { 229 .channels = ltc2632x10_channels, 230 .num_channels = 2, 231 .vref_mv = 4096, 232 }, 233 [ID_LTC2632H8] = { 234 .channels = ltc2632x8_channels, 235 .num_channels = 2, 236 .vref_mv = 4096, 237 }, 238 [ID_LTC2636L12] = { 239 .channels = ltc2632x12_channels, 240 .num_channels = 8, 241 .vref_mv = 2500, 242 }, 243 [ID_LTC2636L10] = { 244 .channels = ltc2632x10_channels, 245 .num_channels = 8, 246 .vref_mv = 2500, 247 }, 248 [ID_LTC2636L8] = { 249 .channels = ltc2632x8_channels, 250 .num_channels = 8, 251 .vref_mv = 2500, 252 }, 253 [ID_LTC2636H12] = { 254 .channels = ltc2632x12_channels, 255 .num_channels = 8, 256 .vref_mv = 4096, 257 }, 258 [ID_LTC2636H10] = { 259 .channels = ltc2632x10_channels, 260 .num_channels = 8, 261 .vref_mv = 4096, 262 }, 263 [ID_LTC2636H8] = { 264 .channels = ltc2632x8_channels, 265 .num_channels = 8, 266 .vref_mv = 4096, 267 }, 268 }; 269 270 static int ltc2632_probe(struct spi_device *spi) 271 { 272 struct ltc2632_state *st; 273 struct iio_dev *indio_dev; 274 struct ltc2632_chip_info *chip_info; 275 int ret; 276 277 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 278 if (!indio_dev) 279 return -ENOMEM; 280 281 st = iio_priv(indio_dev); 282 283 spi_set_drvdata(spi, indio_dev); 284 st->spi_dev = spi; 285 286 chip_info = (struct ltc2632_chip_info *) 287 spi_get_device_id(spi)->driver_data; 288 289 st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref"); 290 if (PTR_ERR(st->vref_reg) == -ENODEV) { 291 /* use internal reference voltage */ 292 st->vref_reg = NULL; 293 st->vref_mv = chip_info->vref_mv; 294 295 ret = ltc2632_spi_write(spi, LTC2632_CMD_INTERNAL_REFER, 296 0, 0, 0); 297 if (ret) { 298 dev_err(&spi->dev, 299 "Set internal reference command failed, %d\n", 300 ret); 301 return ret; 302 } 303 } else if (IS_ERR(st->vref_reg)) { 304 dev_err(&spi->dev, 305 "Error getting voltage reference regulator\n"); 306 return PTR_ERR(st->vref_reg); 307 } else { 308 /* use external reference voltage */ 309 ret = regulator_enable(st->vref_reg); 310 if (ret) { 311 dev_err(&spi->dev, 312 "enable reference regulator failed, %d\n", 313 ret); 314 return ret; 315 } 316 st->vref_mv = regulator_get_voltage(st->vref_reg) / 1000; 317 318 ret = ltc2632_spi_write(spi, LTC2632_CMD_EXTERNAL_REFER, 319 0, 0, 0); 320 if (ret) { 321 dev_err(&spi->dev, 322 "Set external reference command failed, %d\n", 323 ret); 324 return ret; 325 } 326 } 327 328 indio_dev->dev.parent = &spi->dev; 329 indio_dev->name = dev_of_node(&spi->dev) ? dev_of_node(&spi->dev)->name 330 : spi_get_device_id(spi)->name; 331 indio_dev->info = <c2632_info; 332 indio_dev->modes = INDIO_DIRECT_MODE; 333 indio_dev->channels = chip_info->channels; 334 indio_dev->num_channels = chip_info->num_channels; 335 336 return iio_device_register(indio_dev); 337 } 338 339 static int ltc2632_remove(struct spi_device *spi) 340 { 341 struct iio_dev *indio_dev = spi_get_drvdata(spi); 342 struct ltc2632_state *st = iio_priv(indio_dev); 343 344 iio_device_unregister(indio_dev); 345 346 if (st->vref_reg) 347 regulator_disable(st->vref_reg); 348 349 return 0; 350 } 351 352 static const struct spi_device_id ltc2632_id[] = { 353 { "ltc2632-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L12] }, 354 { "ltc2632-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L10] }, 355 { "ltc2632-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L8] }, 356 { "ltc2632-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H12] }, 357 { "ltc2632-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H10] }, 358 { "ltc2632-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H8] }, 359 { "ltc2636-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L12] }, 360 { "ltc2636-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L10] }, 361 { "ltc2636-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L8] }, 362 { "ltc2636-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636H12] }, 363 { "ltc2636-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636H10] }, 364 { "ltc2636-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636H8] }, 365 {} 366 }; 367 MODULE_DEVICE_TABLE(spi, ltc2632_id); 368 369 static const struct of_device_id ltc2632_of_match[] = { 370 { 371 .compatible = "lltc,ltc2632-l12", 372 .data = <c2632_chip_info_tbl[ID_LTC2632L12] 373 }, { 374 .compatible = "lltc,ltc2632-l10", 375 .data = <c2632_chip_info_tbl[ID_LTC2632L10] 376 }, { 377 .compatible = "lltc,ltc2632-l8", 378 .data = <c2632_chip_info_tbl[ID_LTC2632L8] 379 }, { 380 .compatible = "lltc,ltc2632-h12", 381 .data = <c2632_chip_info_tbl[ID_LTC2632H12] 382 }, { 383 .compatible = "lltc,ltc2632-h10", 384 .data = <c2632_chip_info_tbl[ID_LTC2632H10] 385 }, { 386 .compatible = "lltc,ltc2632-h8", 387 .data = <c2632_chip_info_tbl[ID_LTC2632H8] 388 }, { 389 .compatible = "lltc,ltc2636-l12", 390 .data = <c2632_chip_info_tbl[ID_LTC2636L12] 391 }, { 392 .compatible = "lltc,ltc2636-l10", 393 .data = <c2632_chip_info_tbl[ID_LTC2636L10] 394 }, { 395 .compatible = "lltc,ltc2636-l8", 396 .data = <c2632_chip_info_tbl[ID_LTC2636L8] 397 }, { 398 .compatible = "lltc,ltc2636-h12", 399 .data = <c2632_chip_info_tbl[ID_LTC2636H12] 400 }, { 401 .compatible = "lltc,ltc2636-h10", 402 .data = <c2632_chip_info_tbl[ID_LTC2636H10] 403 }, { 404 .compatible = "lltc,ltc2636-h8", 405 .data = <c2632_chip_info_tbl[ID_LTC2636H8] 406 }, 407 {} 408 }; 409 MODULE_DEVICE_TABLE(of, ltc2632_of_match); 410 411 static struct spi_driver ltc2632_driver = { 412 .driver = { 413 .name = "ltc2632", 414 .of_match_table = of_match_ptr(ltc2632_of_match), 415 }, 416 .probe = ltc2632_probe, 417 .remove = ltc2632_remove, 418 .id_table = ltc2632_id, 419 }; 420 module_spi_driver(ltc2632_driver); 421 422 MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>"); 423 MODULE_DESCRIPTION("LTC2632 DAC SPI driver"); 424 MODULE_LICENSE("GPL v2"); 425