1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 53 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 54 55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 56 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 58 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 59 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 60 61 static const char hcd_name[] = "xhci_hcd"; 62 63 static struct hc_driver __read_mostly xhci_pci_hc_driver; 64 65 static int xhci_pci_setup(struct usb_hcd *hcd); 66 67 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 68 .reset = xhci_pci_setup, 69 }; 70 71 /* called after powerup, by probe or system-pm "wakeup" */ 72 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 73 { 74 /* 75 * TODO: Implement finding debug ports later. 76 * TODO: see if there are any quirks that need to be added to handle 77 * new extended capabilities. 78 */ 79 80 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 81 if (!pci_set_mwi(pdev)) 82 xhci_dbg(xhci, "MWI active\n"); 83 84 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 85 return 0; 86 } 87 88 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 89 { 90 struct pci_dev *pdev = to_pci_dev(dev); 91 92 /* Look for vendor-specific quirks */ 93 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 94 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 95 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 96 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 97 pdev->revision == 0x0) { 98 xhci->quirks |= XHCI_RESET_EP_QUIRK; 99 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 100 "QUIRK: Fresco Logic xHC needs configure" 101 " endpoint cmd after reset endpoint"); 102 } 103 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 104 pdev->revision == 0x4) { 105 xhci->quirks |= XHCI_SLOW_SUSPEND; 106 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 107 "QUIRK: Fresco Logic xHC revision %u" 108 "must be suspended extra slowly", 109 pdev->revision); 110 } 111 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 112 xhci->quirks |= XHCI_BROKEN_STREAMS; 113 /* Fresco Logic confirms: all revisions of this chip do not 114 * support MSI, even though some of them claim to in their PCI 115 * capabilities. 116 */ 117 xhci->quirks |= XHCI_BROKEN_MSI; 118 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 119 "QUIRK: Fresco Logic revision %u " 120 "has broken MSI implementation", 121 pdev->revision); 122 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 123 } 124 125 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 126 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 127 xhci->quirks |= XHCI_BROKEN_STREAMS; 128 129 if (pdev->vendor == PCI_VENDOR_ID_NEC) 130 xhci->quirks |= XHCI_NEC_HOST; 131 132 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 133 xhci->quirks |= XHCI_AMD_0x96_HOST; 134 135 /* AMD PLL quirk */ 136 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 137 xhci->quirks |= XHCI_AMD_PLL_FIX; 138 139 if (pdev->vendor == PCI_VENDOR_ID_AMD && 140 (pdev->device == 0x145c || 141 pdev->device == 0x15e0 || 142 pdev->device == 0x15e1 || 143 pdev->device == 0x43bb)) 144 xhci->quirks |= XHCI_SUSPEND_DELAY; 145 146 if (pdev->vendor == PCI_VENDOR_ID_AMD && 147 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 148 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 149 150 if (pdev->vendor == PCI_VENDOR_ID_AMD) 151 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 152 153 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 154 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 155 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 156 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 157 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 158 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 159 160 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 161 xhci->quirks |= XHCI_LPM_SUPPORT; 162 xhci->quirks |= XHCI_INTEL_HOST; 163 xhci->quirks |= XHCI_AVOID_BEI; 164 } 165 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 166 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 167 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 168 xhci->limit_active_eps = 64; 169 xhci->quirks |= XHCI_SW_BW_CHECKING; 170 /* 171 * PPT desktop boards DH77EB and DH77DF will power back on after 172 * a few seconds of being shutdown. The fix for this is to 173 * switch the ports from xHCI to EHCI on shutdown. We can't use 174 * DMI information to find those particular boards (since each 175 * vendor will change the board name), so we have to key off all 176 * PPT chipsets. 177 */ 178 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 179 } 180 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 181 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 182 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 183 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 184 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 185 } 186 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 187 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 188 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 189 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 190 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 191 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 192 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 193 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 194 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 195 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 196 } 197 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 198 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 199 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 200 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 201 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 202 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 203 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 204 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 205 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 206 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 207 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 208 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 209 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 210 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 211 xhci->quirks |= XHCI_MISSING_CAS; 212 213 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 214 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 215 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 216 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 217 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 218 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 219 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 220 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 221 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 222 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI)) 223 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 224 225 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 226 pdev->device == PCI_DEVICE_ID_EJ168) { 227 xhci->quirks |= XHCI_RESET_ON_RESUME; 228 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 229 xhci->quirks |= XHCI_BROKEN_STREAMS; 230 } 231 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 232 pdev->device == 0x0014) { 233 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 234 xhci->quirks |= XHCI_ZERO_64B_REGS; 235 } 236 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 237 pdev->device == 0x0015) { 238 xhci->quirks |= XHCI_RESET_ON_RESUME; 239 xhci->quirks |= XHCI_ZERO_64B_REGS; 240 } 241 if (pdev->vendor == PCI_VENDOR_ID_VIA) 242 xhci->quirks |= XHCI_RESET_ON_RESUME; 243 244 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 245 if (pdev->vendor == PCI_VENDOR_ID_VIA && 246 pdev->device == 0x3432) 247 xhci->quirks |= XHCI_BROKEN_STREAMS; 248 249 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 250 xhci->quirks |= XHCI_LPM_SUPPORT; 251 252 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 253 pdev->device == 0x1042) 254 xhci->quirks |= XHCI_BROKEN_STREAMS; 255 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 256 pdev->device == 0x1142) 257 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 258 259 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 260 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 261 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 262 263 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 264 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 265 266 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 267 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 268 pdev->device == 0x9026) 269 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 270 271 if (xhci->quirks & XHCI_RESET_ON_RESUME) 272 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 273 "QUIRK: Resetting on resume"); 274 } 275 276 #ifdef CONFIG_ACPI 277 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 278 { 279 static const guid_t intel_dsm_guid = 280 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 281 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 282 union acpi_object *obj; 283 284 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 285 NULL); 286 ACPI_FREE(obj); 287 } 288 #else 289 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 290 #endif /* CONFIG_ACPI */ 291 292 /* called during probe() after chip reset completes */ 293 static int xhci_pci_setup(struct usb_hcd *hcd) 294 { 295 struct xhci_hcd *xhci; 296 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 297 int retval; 298 299 xhci = hcd_to_xhci(hcd); 300 if (!xhci->sbrn) 301 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 302 303 /* imod_interval is the interrupt moderation value in nanoseconds. */ 304 xhci->imod_interval = 40000; 305 306 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 307 if (retval) 308 return retval; 309 310 if (!usb_hcd_is_primary_hcd(hcd)) 311 return 0; 312 313 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 314 xhci_pme_acpi_rtd3_enable(pdev); 315 316 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 317 318 /* Find any debug ports */ 319 return xhci_pci_reinit(xhci, pdev); 320 } 321 322 /* 323 * We need to register our own PCI probe function (instead of the USB core's 324 * function) in order to create a second roothub under xHCI. 325 */ 326 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 327 { 328 int retval; 329 struct xhci_hcd *xhci; 330 struct hc_driver *driver; 331 struct usb_hcd *hcd; 332 333 driver = (struct hc_driver *)id->driver_data; 334 335 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 336 pm_runtime_get_noresume(&dev->dev); 337 338 /* Register the USB 2.0 roothub. 339 * FIXME: USB core must know to register the USB 2.0 roothub first. 340 * This is sort of silly, because we could just set the HCD driver flags 341 * to say USB 2.0, but I'm not sure what the implications would be in 342 * the other parts of the HCD code. 343 */ 344 retval = usb_hcd_pci_probe(dev, id); 345 346 if (retval) 347 goto put_runtime_pm; 348 349 /* USB 2.0 roothub is stored in the PCI device now. */ 350 hcd = dev_get_drvdata(&dev->dev); 351 xhci = hcd_to_xhci(hcd); 352 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 353 pci_name(dev), hcd); 354 if (!xhci->shared_hcd) { 355 retval = -ENOMEM; 356 goto dealloc_usb2_hcd; 357 } 358 359 retval = xhci_ext_cap_init(xhci); 360 if (retval) 361 goto put_usb3_hcd; 362 363 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 364 IRQF_SHARED); 365 if (retval) 366 goto put_usb3_hcd; 367 /* Roothub already marked as USB 3.0 speed */ 368 369 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 370 HCC_MAX_PSA(xhci->hcc_params) >= 4) 371 xhci->shared_hcd->can_do_streams = 1; 372 373 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 374 pm_runtime_put_noidle(&dev->dev); 375 376 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 377 pm_runtime_allow(&dev->dev); 378 379 return 0; 380 381 put_usb3_hcd: 382 usb_put_hcd(xhci->shared_hcd); 383 dealloc_usb2_hcd: 384 usb_hcd_pci_remove(dev); 385 put_runtime_pm: 386 pm_runtime_put_noidle(&dev->dev); 387 return retval; 388 } 389 390 static void xhci_pci_remove(struct pci_dev *dev) 391 { 392 struct xhci_hcd *xhci; 393 394 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 395 xhci->xhc_state |= XHCI_STATE_REMOVING; 396 397 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 398 pm_runtime_forbid(&dev->dev); 399 400 if (xhci->shared_hcd) { 401 usb_remove_hcd(xhci->shared_hcd); 402 usb_put_hcd(xhci->shared_hcd); 403 xhci->shared_hcd = NULL; 404 } 405 406 /* Workaround for spurious wakeups at shutdown with HSW */ 407 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 408 pci_set_power_state(dev, PCI_D3hot); 409 410 usb_hcd_pci_remove(dev); 411 } 412 413 #ifdef CONFIG_PM 414 /* 415 * In some Intel xHCI controllers, in order to get D3 working, 416 * through a vendor specific SSIC CONFIG register at offset 0x883c, 417 * SSIC PORT need to be marked as "unused" before putting xHCI 418 * into D3. After D3 exit, the SSIC port need to be marked as "used". 419 * Without this change, xHCI might not enter D3 state. 420 */ 421 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 422 { 423 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 424 u32 val; 425 void __iomem *reg; 426 int i; 427 428 for (i = 0; i < SSIC_PORT_NUM; i++) { 429 reg = (void __iomem *) xhci->cap_regs + 430 SSIC_PORT_CFG2 + 431 i * SSIC_PORT_CFG2_OFFSET; 432 433 /* Notify SSIC that SSIC profile programming is not done. */ 434 val = readl(reg) & ~PROG_DONE; 435 writel(val, reg); 436 437 /* Mark SSIC port as unused(suspend) or used(resume) */ 438 val = readl(reg); 439 if (suspend) 440 val |= SSIC_PORT_UNUSED; 441 else 442 val &= ~SSIC_PORT_UNUSED; 443 writel(val, reg); 444 445 /* Notify SSIC that SSIC profile programming is done */ 446 val = readl(reg) | PROG_DONE; 447 writel(val, reg); 448 readl(reg); 449 } 450 } 451 452 /* 453 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 454 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 455 */ 456 static void xhci_pme_quirk(struct usb_hcd *hcd) 457 { 458 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 459 void __iomem *reg; 460 u32 val; 461 462 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 463 val = readl(reg); 464 writel(val | BIT(28), reg); 465 readl(reg); 466 } 467 468 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 469 { 470 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 471 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 472 int ret; 473 474 /* 475 * Systems with the TI redriver that loses port status change events 476 * need to have the registers polled during D3, so avoid D3cold. 477 */ 478 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 479 pci_d3cold_disable(pdev); 480 481 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 482 xhci_pme_quirk(hcd); 483 484 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 485 xhci_ssic_port_unused_quirk(hcd, true); 486 487 ret = xhci_suspend(xhci, do_wakeup); 488 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 489 xhci_ssic_port_unused_quirk(hcd, false); 490 491 return ret; 492 } 493 494 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 495 { 496 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 497 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 498 int retval = 0; 499 500 /* The BIOS on systems with the Intel Panther Point chipset may or may 501 * not support xHCI natively. That means that during system resume, it 502 * may switch the ports back to EHCI so that users can use their 503 * keyboard to select a kernel from GRUB after resume from hibernate. 504 * 505 * The BIOS is supposed to remember whether the OS had xHCI ports 506 * enabled before resume, and switch the ports back to xHCI when the 507 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 508 * writers. 509 * 510 * Unconditionally switch the ports back to xHCI after a system resume. 511 * It should not matter whether the EHCI or xHCI controller is 512 * resumed first. It's enough to do the switchover in xHCI because 513 * USB core won't notice anything as the hub driver doesn't start 514 * running again until after all the devices (including both EHCI and 515 * xHCI host controllers) have been resumed. 516 */ 517 518 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 519 usb_enable_intel_xhci_ports(pdev); 520 521 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 522 xhci_ssic_port_unused_quirk(hcd, false); 523 524 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 525 xhci_pme_quirk(hcd); 526 527 retval = xhci_resume(xhci, hibernated); 528 return retval; 529 } 530 531 static void xhci_pci_shutdown(struct usb_hcd *hcd) 532 { 533 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 534 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 535 536 xhci_shutdown(hcd); 537 538 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 539 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 540 pci_set_power_state(pdev, PCI_D3hot); 541 } 542 #endif /* CONFIG_PM */ 543 544 /*-------------------------------------------------------------------------*/ 545 546 /* PCI driver selection metadata; PCI hotplugging uses this */ 547 static const struct pci_device_id pci_ids[] = { { 548 /* handle any USB 3.0 xHCI controller */ 549 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 550 .driver_data = (unsigned long) &xhci_pci_hc_driver, 551 }, 552 { /* end: all zeroes */ } 553 }; 554 MODULE_DEVICE_TABLE(pci, pci_ids); 555 556 /* pci driver glue; this is a "new style" PCI driver module */ 557 static struct pci_driver xhci_pci_driver = { 558 .name = hcd_name, 559 .id_table = pci_ids, 560 561 .probe = xhci_pci_probe, 562 .remove = xhci_pci_remove, 563 /* suspend and resume implemented later */ 564 565 .shutdown = usb_hcd_pci_shutdown, 566 #ifdef CONFIG_PM 567 .driver = { 568 .pm = &usb_hcd_pci_pm_ops 569 }, 570 #endif 571 }; 572 573 static int __init xhci_pci_init(void) 574 { 575 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 576 #ifdef CONFIG_PM 577 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 578 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 579 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 580 #endif 581 return pci_register_driver(&xhci_pci_driver); 582 } 583 module_init(xhci_pci_init); 584 585 static void __exit xhci_pci_exit(void) 586 { 587 pci_unregister_driver(&xhci_pci_driver); 588 } 589 module_exit(xhci_pci_exit); 590 591 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 592 MODULE_LICENSE("GPL"); 593