1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SAMSUNG EXYNOS7 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 */ 8 9#include <dt-bindings/clock/exynos7-clk.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_bus0; 21 pinctrl2 = &pinctrl_nfc; 22 pinctrl3 = &pinctrl_touch; 23 pinctrl4 = &pinctrl_ff; 24 pinctrl5 = &pinctrl_ese; 25 pinctrl6 = &pinctrl_fsys0; 26 pinctrl7 = &pinctrl_fsys1; 27 pinctrl8 = &pinctrl_bus1; 28 tmuctrl0 = &tmuctrl_0; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 33 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 38 <&cpu_atlas2>, <&cpu_atlas3>; 39 }; 40 41 fin_pll: clock { 42 /* XXTI */ 43 compatible = "fixed-clock"; 44 clock-output-names = "fin_pll"; 45 #clock-cells = <0>; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu_atlas0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a57"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 }; 58 59 cpu_atlas1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a57"; 62 reg = <0x1>; 63 enable-method = "psci"; 64 }; 65 66 cpu_atlas2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a57"; 69 reg = <0x2>; 70 enable-method = "psci"; 71 }; 72 73 cpu_atlas3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a57"; 76 reg = <0x3>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 gpu: gpu@14ac0000 { 82 compatible = "samsung,exynos5433-mali", "arm,mali-t760"; 83 reg = <0x14ac0000 0x5000>; 84 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 87 interrupt-names = "job", "mmu", "gpu"; 88 status = "disabled"; 89 /* TODO: operating points for DVFS, cooling device */ 90 }; 91 92 psci { 93 compatible = "arm,psci-0.2"; 94 method = "smc"; 95 }; 96 97 soc: soc { 98 compatible = "simple-bus"; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges; 102 103 chipid@10000000 { 104 compatible = "samsung,exynos4210-chipid"; 105 reg = <0x10000000 0x100>; 106 }; 107 108 gic: interrupt-controller@11001000 { 109 compatible = "arm,gic-400"; 110 #interrupt-cells = <3>; 111 #address-cells = <0>; 112 interrupt-controller; 113 reg = <0x11001000 0x1000>, 114 <0x11002000 0x1000>, 115 <0x11004000 0x2000>, 116 <0x11006000 0x2000>; 117 }; 118 119 amba { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges; 124 125 pdma0: pdma@10e10000 { 126 compatible = "arm,pl330", "arm,primecell"; 127 reg = <0x10E10000 0x1000>; 128 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&clock_fsys0 ACLK_PDMA0>; 130 clock-names = "apb_pclk"; 131 #dma-cells = <1>; 132 #dma-channels = <8>; 133 #dma-requests = <32>; 134 }; 135 136 pdma1: pdma@10eb0000 { 137 compatible = "arm,pl330", "arm,primecell"; 138 reg = <0x10EB0000 0x1000>; 139 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&clock_fsys0 ACLK_PDMA1>; 141 clock-names = "apb_pclk"; 142 #dma-cells = <1>; 143 #dma-channels = <8>; 144 #dma-requests = <32>; 145 }; 146 }; 147 148 clock_topc: clock-controller@10570000 { 149 compatible = "samsung,exynos7-clock-topc"; 150 reg = <0x10570000 0x10000>; 151 #clock-cells = <1>; 152 }; 153 154 clock_top0: clock-controller@105d0000 { 155 compatible = "samsung,exynos7-clock-top0"; 156 reg = <0x105d0000 0xb000>; 157 #clock-cells = <1>; 158 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 159 <&clock_topc DOUT_SCLK_BUS1_PLL>, 160 <&clock_topc DOUT_SCLK_CC_PLL>, 161 <&clock_topc DOUT_SCLK_MFC_PLL>; 162 clock-names = "fin_pll", "dout_sclk_bus0_pll", 163 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 164 "dout_sclk_mfc_pll"; 165 }; 166 167 clock_top1: clock-controller@105e0000 { 168 compatible = "samsung,exynos7-clock-top1"; 169 reg = <0x105e0000 0xb000>; 170 #clock-cells = <1>; 171 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 172 <&clock_topc DOUT_SCLK_BUS1_PLL>, 173 <&clock_topc DOUT_SCLK_CC_PLL>, 174 <&clock_topc DOUT_SCLK_MFC_PLL>; 175 clock-names = "fin_pll", "dout_sclk_bus0_pll", 176 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 177 "dout_sclk_mfc_pll"; 178 }; 179 180 clock_ccore: clock-controller@105b0000 { 181 compatible = "samsung,exynos7-clock-ccore"; 182 reg = <0x105b0000 0xd00>; 183 #clock-cells = <1>; 184 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 185 clock-names = "fin_pll", "dout_aclk_ccore_133"; 186 }; 187 188 clock_peric0: clock-controller@13610000 { 189 compatible = "samsung,exynos7-clock-peric0"; 190 reg = <0x13610000 0xd00>; 191 #clock-cells = <1>; 192 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 193 <&clock_top0 CLK_SCLK_UART0>; 194 clock-names = "fin_pll", "dout_aclk_peric0_66", 195 "sclk_uart0"; 196 }; 197 198 clock_peric1: clock-controller@14c80000 { 199 compatible = "samsung,exynos7-clock-peric1"; 200 reg = <0x14c80000 0xd00>; 201 #clock-cells = <1>; 202 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 203 <&clock_top0 CLK_SCLK_UART1>, 204 <&clock_top0 CLK_SCLK_UART2>, 205 <&clock_top0 CLK_SCLK_UART3>; 206 clock-names = "fin_pll", "dout_aclk_peric1_66", 207 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 208 }; 209 210 clock_peris: clock-controller@10040000 { 211 compatible = "samsung,exynos7-clock-peris"; 212 reg = <0x10040000 0xd00>; 213 #clock-cells = <1>; 214 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 215 clock-names = "fin_pll", "dout_aclk_peris_66"; 216 }; 217 218 clock_fsys0: clock-controller@10e90000 { 219 compatible = "samsung,exynos7-clock-fsys0"; 220 reg = <0x10e90000 0xd00>; 221 #clock-cells = <1>; 222 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 223 <&clock_top1 DOUT_SCLK_MMC2>; 224 clock-names = "fin_pll", "dout_aclk_fsys0_200", 225 "dout_sclk_mmc2"; 226 }; 227 228 clock_fsys1: clock-controller@156e0000 { 229 compatible = "samsung,exynos7-clock-fsys1"; 230 reg = <0x156e0000 0xd00>; 231 #clock-cells = <1>; 232 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 233 <&clock_top1 DOUT_SCLK_MMC0>, 234 <&clock_top1 DOUT_SCLK_MMC1>; 235 clock-names = "fin_pll", "dout_aclk_fsys1_200", 236 "dout_sclk_mmc0", "dout_sclk_mmc1"; 237 }; 238 239 serial_0: serial@13630000 { 240 compatible = "samsung,exynos4210-uart"; 241 reg = <0x13630000 0x100>; 242 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&clock_peric0 PCLK_UART0>, 244 <&clock_peric0 SCLK_UART0>; 245 clock-names = "uart", "clk_uart_baud0"; 246 status = "disabled"; 247 }; 248 249 serial_1: serial@14c20000 { 250 compatible = "samsung,exynos4210-uart"; 251 reg = <0x14c20000 0x100>; 252 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&clock_peric1 PCLK_UART1>, 254 <&clock_peric1 SCLK_UART1>; 255 clock-names = "uart", "clk_uart_baud0"; 256 status = "disabled"; 257 }; 258 259 serial_2: serial@14c30000 { 260 compatible = "samsung,exynos4210-uart"; 261 reg = <0x14c30000 0x100>; 262 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clock_peric1 PCLK_UART2>, 264 <&clock_peric1 SCLK_UART2>; 265 clock-names = "uart", "clk_uart_baud0"; 266 status = "disabled"; 267 }; 268 269 serial_3: serial@14c40000 { 270 compatible = "samsung,exynos4210-uart"; 271 reg = <0x14c40000 0x100>; 272 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clock_peric1 PCLK_UART3>, 274 <&clock_peric1 SCLK_UART3>; 275 clock-names = "uart", "clk_uart_baud0"; 276 status = "disabled"; 277 }; 278 279 pinctrl_alive: pinctrl@10580000 { 280 compatible = "samsung,exynos7-pinctrl"; 281 reg = <0x10580000 0x1000>; 282 283 wakeup-interrupt-controller { 284 compatible = "samsung,exynos7-wakeup-eint"; 285 interrupt-parent = <&gic>; 286 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 287 }; 288 }; 289 290 pinctrl_bus0: pinctrl@13470000 { 291 compatible = "samsung,exynos7-pinctrl"; 292 reg = <0x13470000 0x1000>; 293 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 pinctrl_nfc: pinctrl@14cd0000 { 297 compatible = "samsung,exynos7-pinctrl"; 298 reg = <0x14cd0000 0x1000>; 299 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 300 }; 301 302 pinctrl_touch: pinctrl@14ce0000 { 303 compatible = "samsung,exynos7-pinctrl"; 304 reg = <0x14ce0000 0x1000>; 305 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 306 }; 307 308 pinctrl_ff: pinctrl@14c90000 { 309 compatible = "samsung,exynos7-pinctrl"; 310 reg = <0x14c90000 0x1000>; 311 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 312 }; 313 314 pinctrl_ese: pinctrl@14ca0000 { 315 compatible = "samsung,exynos7-pinctrl"; 316 reg = <0x14ca0000 0x1000>; 317 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 318 }; 319 320 pinctrl_fsys0: pinctrl@10e60000 { 321 compatible = "samsung,exynos7-pinctrl"; 322 reg = <0x10e60000 0x1000>; 323 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 324 }; 325 326 pinctrl_fsys1: pinctrl@15690000 { 327 compatible = "samsung,exynos7-pinctrl"; 328 reg = <0x15690000 0x1000>; 329 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 330 }; 331 332 pinctrl_bus1: pinctrl@14870000 { 333 compatible = "samsung,exynos7-pinctrl"; 334 reg = <0x14870000 0x1000>; 335 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 336 }; 337 338 hsi2c_0: hsi2c@13640000 { 339 compatible = "samsung,exynos7-hsi2c"; 340 reg = <0x13640000 0x1000>; 341 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&hs_i2c0_bus>; 346 clocks = <&clock_peric0 PCLK_HSI2C0>; 347 clock-names = "hsi2c"; 348 status = "disabled"; 349 }; 350 351 hsi2c_1: hsi2c@13650000 { 352 compatible = "samsung,exynos7-hsi2c"; 353 reg = <0x13650000 0x1000>; 354 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&hs_i2c1_bus>; 359 clocks = <&clock_peric0 PCLK_HSI2C1>; 360 clock-names = "hsi2c"; 361 status = "disabled"; 362 }; 363 364 hsi2c_2: hsi2c@14e60000 { 365 compatible = "samsung,exynos7-hsi2c"; 366 reg = <0x14e60000 0x1000>; 367 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&hs_i2c2_bus>; 372 clocks = <&clock_peric1 PCLK_HSI2C2>; 373 clock-names = "hsi2c"; 374 status = "disabled"; 375 }; 376 377 hsi2c_3: hsi2c@14e70000 { 378 compatible = "samsung,exynos7-hsi2c"; 379 reg = <0x14e70000 0x1000>; 380 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&hs_i2c3_bus>; 385 clocks = <&clock_peric1 PCLK_HSI2C3>; 386 clock-names = "hsi2c"; 387 status = "disabled"; 388 }; 389 390 hsi2c_4: hsi2c@13660000 { 391 compatible = "samsung,exynos7-hsi2c"; 392 reg = <0x13660000 0x1000>; 393 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&hs_i2c4_bus>; 398 clocks = <&clock_peric0 PCLK_HSI2C4>; 399 clock-names = "hsi2c"; 400 status = "disabled"; 401 }; 402 403 hsi2c_5: hsi2c@13670000 { 404 compatible = "samsung,exynos7-hsi2c"; 405 reg = <0x13670000 0x1000>; 406 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&hs_i2c5_bus>; 411 clocks = <&clock_peric0 PCLK_HSI2C5>; 412 clock-names = "hsi2c"; 413 status = "disabled"; 414 }; 415 416 hsi2c_6: hsi2c@14e00000 { 417 compatible = "samsung,exynos7-hsi2c"; 418 reg = <0x14e00000 0x1000>; 419 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&hs_i2c6_bus>; 424 clocks = <&clock_peric1 PCLK_HSI2C6>; 425 clock-names = "hsi2c"; 426 status = "disabled"; 427 }; 428 429 hsi2c_7: hsi2c@13e10000 { 430 compatible = "samsung,exynos7-hsi2c"; 431 reg = <0x13e10000 0x1000>; 432 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&hs_i2c7_bus>; 437 clocks = <&clock_peric1 PCLK_HSI2C7>; 438 clock-names = "hsi2c"; 439 status = "disabled"; 440 }; 441 442 hsi2c_8: hsi2c@14e20000 { 443 compatible = "samsung,exynos7-hsi2c"; 444 reg = <0x14e20000 0x1000>; 445 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&hs_i2c8_bus>; 450 clocks = <&clock_peric1 PCLK_HSI2C8>; 451 clock-names = "hsi2c"; 452 status = "disabled"; 453 }; 454 455 hsi2c_9: hsi2c@13680000 { 456 compatible = "samsung,exynos7-hsi2c"; 457 reg = <0x13680000 0x1000>; 458 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&hs_i2c9_bus>; 463 clocks = <&clock_peric0 PCLK_HSI2C9>; 464 clock-names = "hsi2c"; 465 status = "disabled"; 466 }; 467 468 hsi2c_10: hsi2c@13690000 { 469 compatible = "samsung,exynos7-hsi2c"; 470 reg = <0x13690000 0x1000>; 471 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&hs_i2c10_bus>; 476 clocks = <&clock_peric0 PCLK_HSI2C10>; 477 clock-names = "hsi2c"; 478 status = "disabled"; 479 }; 480 481 hsi2c_11: hsi2c@136a0000 { 482 compatible = "samsung,exynos7-hsi2c"; 483 reg = <0x136a0000 0x1000>; 484 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&hs_i2c11_bus>; 489 clocks = <&clock_peric0 PCLK_HSI2C11>; 490 clock-names = "hsi2c"; 491 status = "disabled"; 492 }; 493 494 pmu_system_controller: system-controller@105c0000 { 495 compatible = "samsung,exynos7-pmu", "syscon"; 496 reg = <0x105c0000 0x5000>; 497 498 reboot: syscon-reboot { 499 compatible = "syscon-reboot"; 500 regmap = <&pmu_system_controller>; 501 offset = <0x0400>; 502 mask = <0x1>; 503 }; 504 }; 505 506 rtc: rtc@10590000 { 507 compatible = "samsung,s3c6410-rtc"; 508 reg = <0x10590000 0x100>; 509 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clock_ccore PCLK_RTC>; 512 clock-names = "rtc"; 513 status = "disabled"; 514 }; 515 516 watchdog: watchdog@101d0000 { 517 compatible = "samsung,exynos7-wdt"; 518 reg = <0x101d0000 0x100>; 519 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clock_peris PCLK_WDT>; 521 clock-names = "watchdog"; 522 samsung,syscon-phandle = <&pmu_system_controller>; 523 status = "disabled"; 524 }; 525 526 mmc_0: mmc@15740000 { 527 compatible = "samsung,exynos7-dw-mshc-smu"; 528 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <0x15740000 0x2000>; 532 clocks = <&clock_fsys1 ACLK_MMC0>, 533 <&clock_top1 CLK_SCLK_MMC0>; 534 clock-names = "biu", "ciu"; 535 fifo-depth = <0x40>; 536 status = "disabled"; 537 }; 538 539 mmc_1: mmc@15750000 { 540 compatible = "samsung,exynos7-dw-mshc"; 541 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <0x15750000 0x2000>; 545 clocks = <&clock_fsys1 ACLK_MMC1>, 546 <&clock_top1 CLK_SCLK_MMC1>; 547 clock-names = "biu", "ciu"; 548 fifo-depth = <0x40>; 549 status = "disabled"; 550 }; 551 552 mmc_2: mmc@15560000 { 553 compatible = "samsung,exynos7-dw-mshc-smu"; 554 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 reg = <0x15560000 0x2000>; 558 clocks = <&clock_fsys0 ACLK_MMC2>, 559 <&clock_top1 CLK_SCLK_MMC2>; 560 clock-names = "biu", "ciu"; 561 fifo-depth = <0x40>; 562 status = "disabled"; 563 }; 564 565 adc: adc@13620000 { 566 compatible = "samsung,exynos7-adc"; 567 reg = <0x13620000 0x100>; 568 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clock_peric0 PCLK_ADCIF>; 570 clock-names = "adc"; 571 #io-channel-cells = <1>; 572 io-channel-ranges; 573 status = "disabled"; 574 }; 575 576 pwm: pwm@136c0000 { 577 compatible = "samsung,exynos4210-pwm"; 578 reg = <0x136c0000 0x100>; 579 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 580 #pwm-cells = <3>; 581 clocks = <&clock_peric0 PCLK_PWM>; 582 clock-names = "timers"; 583 }; 584 585 tmuctrl_0: tmu@10060000 { 586 compatible = "samsung,exynos7-tmu"; 587 reg = <0x10060000 0x200>; 588 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clock_peris PCLK_TMU>, 590 <&clock_peris SCLK_TMU>; 591 clock-names = "tmu_apbif", "tmu_sclk"; 592 #thermal-sensor-cells = <0>; 593 }; 594 595 thermal-zones { 596 atlas_thermal: cluster0-thermal { 597 polling-delay-passive = <0>; /* milliseconds */ 598 polling-delay = <0>; /* milliseconds */ 599 thermal-sensors = <&tmuctrl_0>; 600 #include "exynos7-trip-points.dtsi" 601 }; 602 }; 603 604 usbdrd_phy: phy@15500000 { 605 compatible = "samsung,exynos7-usbdrd-phy"; 606 reg = <0x15500000 0x100>; 607 clocks = <&clock_fsys0 ACLK_USBDRD300>, 608 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 609 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 610 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 611 <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 612 clock-names = "phy", "ref", "phy_pipe", 613 "phy_utmi", "itp"; 614 samsung,pmu-syscon = <&pmu_system_controller>; 615 #phy-cells = <1>; 616 }; 617 618 usbdrd3 { 619 compatible = "samsung,exynos7-dwusb3"; 620 clocks = <&clock_fsys0 ACLK_USBDRD300>, 621 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 622 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 623 clock-names = "usbdrd30", "usbdrd30_susp_clk", 624 "usbdrd30_axius_clk"; 625 #address-cells = <1>; 626 #size-cells = <1>; 627 ranges; 628 629 dwc3@15400000 { 630 compatible = "snps,dwc3"; 631 reg = <0x15400000 0x10000>; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 634 phy-names = "usb2-phy", "usb3-phy"; 635 }; 636 }; 637 }; 638 639 timer { 640 compatible = "arm,armv8-timer"; 641 interrupts = <GIC_PPI 13 642 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 643 <GIC_PPI 14 644 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 645 <GIC_PPI 11 646 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 647 <GIC_PPI 10 648 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 649 }; 650}; 651 652#include "exynos7-pinctrl.dtsi" 653