1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Tiger Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2019 - 2020, Intel Corporation 6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-intel.h" 17 18 #define TGL_PAD_OWN 0x020 19 #define TGL_PADCFGLOCK 0x080 20 #define TGL_HOSTSW_OWN 0x0b0 21 #define TGL_GPI_IS 0x100 22 #define TGL_GPI_IE 0x120 23 24 #define TGL_GPP(r, s, e, g) \ 25 { \ 26 .reg_num = (r), \ 27 .base = (s), \ 28 .size = ((e) - (s) + 1), \ 29 .gpio_base = (g), \ 30 } 31 32 #define TGL_COMMUNITY(b, s, e, g) \ 33 { \ 34 .barno = (b), \ 35 .padown_offset = TGL_PAD_OWN, \ 36 .padcfglock_offset = TGL_PADCFGLOCK, \ 37 .hostown_offset = TGL_HOSTSW_OWN, \ 38 .is_offset = TGL_GPI_IS, \ 39 .ie_offset = TGL_GPI_IE, \ 40 .pin_base = (s), \ 41 .npins = ((e) - (s) + 1), \ 42 .gpps = (g), \ 43 .ngpps = ARRAY_SIZE(g), \ 44 } 45 46 /* Tiger Lake-LP */ 47 static const struct pinctrl_pin_desc tgllp_pins[] = { 48 /* GPP_B */ 49 PINCTRL_PIN(0, "CORE_VID_0"), 50 PINCTRL_PIN(1, "CORE_VID_1"), 51 PINCTRL_PIN(2, "VRALERTB"), 52 PINCTRL_PIN(3, "CPU_GP_2"), 53 PINCTRL_PIN(4, "CPU_GP_3"), 54 PINCTRL_PIN(5, "ISH_I2C0_SDA"), 55 PINCTRL_PIN(6, "ISH_I2C0_SCL"), 56 PINCTRL_PIN(7, "ISH_I2C1_SDA"), 57 PINCTRL_PIN(8, "ISH_I2C1_SCL"), 58 PINCTRL_PIN(9, "I2C5_SDA"), 59 PINCTRL_PIN(10, "I2C5_SCL"), 60 PINCTRL_PIN(11, "PMCALERTB"), 61 PINCTRL_PIN(12, "SLP_S0B"), 62 PINCTRL_PIN(13, "PLTRSTB"), 63 PINCTRL_PIN(14, "SPKR"), 64 PINCTRL_PIN(15, "GSPI0_CS0B"), 65 PINCTRL_PIN(16, "GSPI0_CLK"), 66 PINCTRL_PIN(17, "GSPI0_MISO"), 67 PINCTRL_PIN(18, "GSPI0_MOSI"), 68 PINCTRL_PIN(19, "GSPI1_CS0B"), 69 PINCTRL_PIN(20, "GSPI1_CLK"), 70 PINCTRL_PIN(21, "GSPI1_MISO"), 71 PINCTRL_PIN(22, "GSPI1_MOSI"), 72 PINCTRL_PIN(23, "SML1ALERTB"), 73 PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), 74 PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), 75 /* GPP_T */ 76 PINCTRL_PIN(26, "I2C6_SDA"), 77 PINCTRL_PIN(27, "I2C6_SCL"), 78 PINCTRL_PIN(28, "I2C7_SDA"), 79 PINCTRL_PIN(29, "I2C7_SCL"), 80 PINCTRL_PIN(30, "UART4_RXD"), 81 PINCTRL_PIN(31, "UART4_TXD"), 82 PINCTRL_PIN(32, "UART4_RTSB"), 83 PINCTRL_PIN(33, "UART4_CTSB"), 84 PINCTRL_PIN(34, "UART5_RXD"), 85 PINCTRL_PIN(35, "UART5_TXD"), 86 PINCTRL_PIN(36, "UART5_RTSB"), 87 PINCTRL_PIN(37, "UART5_CTSB"), 88 PINCTRL_PIN(38, "UART6_RXD"), 89 PINCTRL_PIN(39, "UART6_TXD"), 90 PINCTRL_PIN(40, "UART6_RTSB"), 91 PINCTRL_PIN(41, "UART6_CTSB"), 92 /* GPP_A */ 93 PINCTRL_PIN(42, "ESPI_IO_0"), 94 PINCTRL_PIN(43, "ESPI_IO_1"), 95 PINCTRL_PIN(44, "ESPI_IO_2"), 96 PINCTRL_PIN(45, "ESPI_IO_3"), 97 PINCTRL_PIN(46, "ESPI_CSB"), 98 PINCTRL_PIN(47, "ESPI_CLK"), 99 PINCTRL_PIN(48, "ESPI_RESETB"), 100 PINCTRL_PIN(49, "I2S2_SCLK"), 101 PINCTRL_PIN(50, "I2S2_SFRM"), 102 PINCTRL_PIN(51, "I2S2_TXD"), 103 PINCTRL_PIN(52, "I2S2_RXD"), 104 PINCTRL_PIN(53, "PMC_I2C_SDA"), 105 PINCTRL_PIN(54, "SATAXPCIE_1"), 106 PINCTRL_PIN(55, "PMC_I2C_SCL"), 107 PINCTRL_PIN(56, "USB2_OCB_1"), 108 PINCTRL_PIN(57, "USB2_OCB_2"), 109 PINCTRL_PIN(58, "USB2_OCB_3"), 110 PINCTRL_PIN(59, "DDSP_HPD_C"), 111 PINCTRL_PIN(60, "DDSP_HPD_B"), 112 PINCTRL_PIN(61, "DDSP_HPD_1"), 113 PINCTRL_PIN(62, "DDSP_HPD_2"), 114 PINCTRL_PIN(63, "GPPC_A_21"), 115 PINCTRL_PIN(64, "GPPC_A_22"), 116 PINCTRL_PIN(65, "I2S1_SCLK"), 117 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), 118 /* GPP_S */ 119 PINCTRL_PIN(67, "SNDW0_CLK"), 120 PINCTRL_PIN(68, "SNDW0_DATA"), 121 PINCTRL_PIN(69, "SNDW1_CLK"), 122 PINCTRL_PIN(70, "SNDW1_DATA"), 123 PINCTRL_PIN(71, "SNDW2_CLK"), 124 PINCTRL_PIN(72, "SNDW2_DATA"), 125 PINCTRL_PIN(73, "SNDW3_CLK"), 126 PINCTRL_PIN(74, "SNDW3_DATA"), 127 /* GPP_H */ 128 PINCTRL_PIN(75, "GPPC_H_0"), 129 PINCTRL_PIN(76, "GPPC_H_1"), 130 PINCTRL_PIN(77, "GPPC_H_2"), 131 PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"), 132 PINCTRL_PIN(79, "I2C2_SDA"), 133 PINCTRL_PIN(80, "I2C2_SCL"), 134 PINCTRL_PIN(81, "I2C3_SDA"), 135 PINCTRL_PIN(82, "I2C3_SCL"), 136 PINCTRL_PIN(83, "I2C4_SDA"), 137 PINCTRL_PIN(84, "I2C4_SCL"), 138 PINCTRL_PIN(85, "SRCCLKREQB_4"), 139 PINCTRL_PIN(86, "SRCCLKREQB_5"), 140 PINCTRL_PIN(87, "M2_SKT2_CFG_0"), 141 PINCTRL_PIN(88, "M2_SKT2_CFG_1"), 142 PINCTRL_PIN(89, "M2_SKT2_CFG_2"), 143 PINCTRL_PIN(90, "M2_SKT2_CFG_3"), 144 PINCTRL_PIN(91, "DDPB_CTRLCLK"), 145 PINCTRL_PIN(92, "DDPB_CTRLDATA"), 146 PINCTRL_PIN(93, "CPU_C10_GATEB"), 147 PINCTRL_PIN(94, "TIME_SYNC_0"), 148 PINCTRL_PIN(95, "IMGCLKOUT_1"), 149 PINCTRL_PIN(96, "IMGCLKOUT_2"), 150 PINCTRL_PIN(97, "IMGCLKOUT_3"), 151 PINCTRL_PIN(98, "IMGCLKOUT_4"), 152 /* GPP_D */ 153 PINCTRL_PIN(99, "ISH_GP_0"), 154 PINCTRL_PIN(100, "ISH_GP_1"), 155 PINCTRL_PIN(101, "ISH_GP_2"), 156 PINCTRL_PIN(102, "ISH_GP_3"), 157 PINCTRL_PIN(103, "IMGCLKOUT_0"), 158 PINCTRL_PIN(104, "SRCCLKREQB_0"), 159 PINCTRL_PIN(105, "SRCCLKREQB_1"), 160 PINCTRL_PIN(106, "SRCCLKREQB_2"), 161 PINCTRL_PIN(107, "SRCCLKREQB_3"), 162 PINCTRL_PIN(108, "ISH_SPI_CSB"), 163 PINCTRL_PIN(109, "ISH_SPI_CLK"), 164 PINCTRL_PIN(110, "ISH_SPI_MISO"), 165 PINCTRL_PIN(111, "ISH_SPI_MOSI"), 166 PINCTRL_PIN(112, "ISH_UART0_RXD"), 167 PINCTRL_PIN(113, "ISH_UART0_TXD"), 168 PINCTRL_PIN(114, "ISH_UART0_RTSB"), 169 PINCTRL_PIN(115, "ISH_UART0_CTSB"), 170 PINCTRL_PIN(116, "ISH_GP_4"), 171 PINCTRL_PIN(117, "ISH_GP_5"), 172 PINCTRL_PIN(118, "I2S_MCLK1_OUT"), 173 PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"), 174 /* GPP_U */ 175 PINCTRL_PIN(120, "UART3_RXD"), 176 PINCTRL_PIN(121, "UART3_TXD"), 177 PINCTRL_PIN(122, "UART3_RTSB"), 178 PINCTRL_PIN(123, "UART3_CTSB"), 179 PINCTRL_PIN(124, "GSPI3_CS0B"), 180 PINCTRL_PIN(125, "GSPI3_CLK"), 181 PINCTRL_PIN(126, "GSPI3_MISO"), 182 PINCTRL_PIN(127, "GSPI3_MOSI"), 183 PINCTRL_PIN(128, "GSPI4_CS0B"), 184 PINCTRL_PIN(129, "GSPI4_CLK"), 185 PINCTRL_PIN(130, "GSPI4_MISO"), 186 PINCTRL_PIN(131, "GSPI4_MOSI"), 187 PINCTRL_PIN(132, "GSPI5_CS0B"), 188 PINCTRL_PIN(133, "GSPI5_CLK"), 189 PINCTRL_PIN(134, "GSPI5_MISO"), 190 PINCTRL_PIN(135, "GSPI5_MOSI"), 191 PINCTRL_PIN(136, "GSPI6_CS0B"), 192 PINCTRL_PIN(137, "GSPI6_CLK"), 193 PINCTRL_PIN(138, "GSPI6_MISO"), 194 PINCTRL_PIN(139, "GSPI6_MOSI"), 195 PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"), 196 PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"), 197 PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"), 198 PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"), 199 /* vGPIO */ 200 PINCTRL_PIN(144, "CNV_BTEN"), 201 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), 202 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), 203 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), 204 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), 205 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), 206 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), 207 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), 208 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), 209 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), 210 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), 211 PINCTRL_PIN(155, "vUART0_TXD"), 212 PINCTRL_PIN(156, "vUART0_RXD"), 213 PINCTRL_PIN(157, "vUART0_CTS_B"), 214 PINCTRL_PIN(158, "vUART0_RTS_B"), 215 PINCTRL_PIN(159, "vISH_UART0_TXD"), 216 PINCTRL_PIN(160, "vISH_UART0_RXD"), 217 PINCTRL_PIN(161, "vISH_UART0_CTS_B"), 218 PINCTRL_PIN(162, "vISH_UART0_RTS_B"), 219 PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"), 220 PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"), 221 PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"), 222 PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"), 223 PINCTRL_PIN(167, "vI2S2_SCLK"), 224 PINCTRL_PIN(168, "vI2S2_SFRM"), 225 PINCTRL_PIN(169, "vI2S2_TXD"), 226 PINCTRL_PIN(170, "vI2S2_RXD"), 227 /* GPP_C */ 228 PINCTRL_PIN(171, "SMBCLK"), 229 PINCTRL_PIN(172, "SMBDATA"), 230 PINCTRL_PIN(173, "SMBALERTB"), 231 PINCTRL_PIN(174, "SML0CLK"), 232 PINCTRL_PIN(175, "SML0DATA"), 233 PINCTRL_PIN(176, "SML0ALERTB"), 234 PINCTRL_PIN(177, "SML1CLK"), 235 PINCTRL_PIN(178, "SML1DATA"), 236 PINCTRL_PIN(179, "UART0_RXD"), 237 PINCTRL_PIN(180, "UART0_TXD"), 238 PINCTRL_PIN(181, "UART0_RTSB"), 239 PINCTRL_PIN(182, "UART0_CTSB"), 240 PINCTRL_PIN(183, "UART1_RXD"), 241 PINCTRL_PIN(184, "UART1_TXD"), 242 PINCTRL_PIN(185, "UART1_RTSB"), 243 PINCTRL_PIN(186, "UART1_CTSB"), 244 PINCTRL_PIN(187, "I2C0_SDA"), 245 PINCTRL_PIN(188, "I2C0_SCL"), 246 PINCTRL_PIN(189, "I2C1_SDA"), 247 PINCTRL_PIN(190, "I2C1_SCL"), 248 PINCTRL_PIN(191, "UART2_RXD"), 249 PINCTRL_PIN(192, "UART2_TXD"), 250 PINCTRL_PIN(193, "UART2_RTSB"), 251 PINCTRL_PIN(194, "UART2_CTSB"), 252 /* GPP_F */ 253 PINCTRL_PIN(195, "CNV_BRI_DT"), 254 PINCTRL_PIN(196, "CNV_BRI_RSP"), 255 PINCTRL_PIN(197, "CNV_RGI_DT"), 256 PINCTRL_PIN(198, "CNV_RGI_RSP"), 257 PINCTRL_PIN(199, "CNV_RF_RESET_B"), 258 PINCTRL_PIN(200, "GPPC_F_5"), 259 PINCTRL_PIN(201, "CNV_PA_BLANKING"), 260 PINCTRL_PIN(202, "GPPC_F_7"), 261 PINCTRL_PIN(203, "I2S_MCLK2_INOUT"), 262 PINCTRL_PIN(204, "BOOTMPC"), 263 PINCTRL_PIN(205, "GPPC_F_10"), 264 PINCTRL_PIN(206, "GPPC_F_11"), 265 PINCTRL_PIN(207, "GSXDOUT"), 266 PINCTRL_PIN(208, "GSXSLOAD"), 267 PINCTRL_PIN(209, "GSXDIN"), 268 PINCTRL_PIN(210, "GSXSRESETB"), 269 PINCTRL_PIN(211, "GSXCLK"), 270 PINCTRL_PIN(212, "GMII_MDC"), 271 PINCTRL_PIN(213, "GMII_MDIO"), 272 PINCTRL_PIN(214, "SRCCLKREQB_6"), 273 PINCTRL_PIN(215, "EXT_PWR_GATEB"), 274 PINCTRL_PIN(216, "EXT_PWR_GATE2B"), 275 PINCTRL_PIN(217, "VNN_CTRL"), 276 PINCTRL_PIN(218, "V1P05_CTRL"), 277 PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"), 278 /* HVCMOS */ 279 PINCTRL_PIN(220, "L_BKLTEN"), 280 PINCTRL_PIN(221, "L_BKLTCTL"), 281 PINCTRL_PIN(222, "L_VDDEN"), 282 PINCTRL_PIN(223, "SYS_PWROK"), 283 PINCTRL_PIN(224, "SYS_RESETB"), 284 PINCTRL_PIN(225, "MLK_RSTB"), 285 /* GPP_E */ 286 PINCTRL_PIN(226, "SATAXPCIE_0"), 287 PINCTRL_PIN(227, "SPI1_IO_2"), 288 PINCTRL_PIN(228, "SPI1_IO_3"), 289 PINCTRL_PIN(229, "CPU_GP_0"), 290 PINCTRL_PIN(230, "SATA_DEVSLP_0"), 291 PINCTRL_PIN(231, "SATA_DEVSLP_1"), 292 PINCTRL_PIN(232, "GPPC_E_6"), 293 PINCTRL_PIN(233, "CPU_GP_1"), 294 PINCTRL_PIN(234, "SPI1_CS1B"), 295 PINCTRL_PIN(235, "USB2_OCB_0"), 296 PINCTRL_PIN(236, "SPI1_CSB"), 297 PINCTRL_PIN(237, "SPI1_CLK"), 298 PINCTRL_PIN(238, "SPI1_MISO_IO_1"), 299 PINCTRL_PIN(239, "SPI1_MOSI_IO_0"), 300 PINCTRL_PIN(240, "DDSP_HPD_A"), 301 PINCTRL_PIN(241, "ISH_GP_6"), 302 PINCTRL_PIN(242, "ISH_GP_7"), 303 PINCTRL_PIN(243, "GPPC_E_17"), 304 PINCTRL_PIN(244, "DDP1_CTRLCLK"), 305 PINCTRL_PIN(245, "DDP1_CTRLDATA"), 306 PINCTRL_PIN(246, "DDP2_CTRLCLK"), 307 PINCTRL_PIN(247, "DDP2_CTRLDATA"), 308 PINCTRL_PIN(248, "DDPA_CTRLCLK"), 309 PINCTRL_PIN(249, "DDPA_CTRLDATA"), 310 PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"), 311 /* JTAG */ 312 PINCTRL_PIN(251, "JTAG_TDO"), 313 PINCTRL_PIN(252, "JTAGX"), 314 PINCTRL_PIN(253, "PRDYB"), 315 PINCTRL_PIN(254, "PREQB"), 316 PINCTRL_PIN(255, "CPU_TRSTB"), 317 PINCTRL_PIN(256, "JTAG_TDI"), 318 PINCTRL_PIN(257, "JTAG_TMS"), 319 PINCTRL_PIN(258, "JTAG_TCK"), 320 PINCTRL_PIN(259, "DBG_PMODE"), 321 /* GPP_R */ 322 PINCTRL_PIN(260, "HDA_BCLK"), 323 PINCTRL_PIN(261, "HDA_SYNC"), 324 PINCTRL_PIN(262, "HDA_SDO"), 325 PINCTRL_PIN(263, "HDA_SDI_0"), 326 PINCTRL_PIN(264, "HDA_RSTB"), 327 PINCTRL_PIN(265, "HDA_SDI_1"), 328 PINCTRL_PIN(266, "GPP_R_6"), 329 PINCTRL_PIN(267, "GPP_R_7"), 330 /* SPI */ 331 PINCTRL_PIN(268, "SPI0_IO_2"), 332 PINCTRL_PIN(269, "SPI0_IO_3"), 333 PINCTRL_PIN(270, "SPI0_MOSI_IO_0"), 334 PINCTRL_PIN(271, "SPI0_MISO_IO_1"), 335 PINCTRL_PIN(272, "SPI0_TPM_CSB"), 336 PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"), 337 PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"), 338 PINCTRL_PIN(275, "SPI0_CLK"), 339 PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), 340 }; 341 342 static const struct intel_padgroup tgllp_community0_gpps[] = { 343 TGL_GPP(0, 0, 25, 0), /* GPP_B */ 344 TGL_GPP(1, 26, 41, 32), /* GPP_T */ 345 TGL_GPP(2, 42, 66, 64), /* GPP_A */ 346 }; 347 348 static const struct intel_padgroup tgllp_community1_gpps[] = { 349 TGL_GPP(0, 67, 74, 96), /* GPP_S */ 350 TGL_GPP(1, 75, 98, 128), /* GPP_H */ 351 TGL_GPP(2, 99, 119, 160), /* GPP_D */ 352 TGL_GPP(3, 120, 143, 192), /* GPP_U */ 353 TGL_GPP(4, 144, 170, 224), /* vGPIO */ 354 }; 355 356 static const struct intel_padgroup tgllp_community4_gpps[] = { 357 TGL_GPP(0, 171, 194, 256), /* GPP_C */ 358 TGL_GPP(1, 195, 219, 288), /* GPP_F */ 359 TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 360 TGL_GPP(3, 226, 250, 320), /* GPP_E */ 361 TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 362 }; 363 364 static const struct intel_padgroup tgllp_community5_gpps[] = { 365 TGL_GPP(0, 260, 267, 352), /* GPP_R */ 366 TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ 367 }; 368 369 static const struct intel_community tgllp_communities[] = { 370 TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps), 371 TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps), 372 TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps), 373 TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps), 374 }; 375 376 static const struct intel_pinctrl_soc_data tgllp_soc_data = { 377 .pins = tgllp_pins, 378 .npins = ARRAY_SIZE(tgllp_pins), 379 .communities = tgllp_communities, 380 .ncommunities = ARRAY_SIZE(tgllp_communities), 381 }; 382 383 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { 384 { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, 385 { } 386 }; 387 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); 388 389 static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops); 390 391 static struct platform_driver tgl_pinctrl_driver = { 392 .probe = intel_pinctrl_probe_by_hid, 393 .driver = { 394 .name = "tigerlake-pinctrl", 395 .acpi_match_table = tgl_pinctrl_acpi_match, 396 .pm = &tgl_pinctrl_pm_ops, 397 }, 398 }; 399 400 module_platform_driver(tgl_pinctrl_driver); 401 402 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 403 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 404 MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); 405 MODULE_LICENSE("GPL v2"); 406