1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 clock-latency-ns = <244144>; /* 8 32k periods */ 30 #cooling-cells = <2>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 reg = <1>; 37 enable-method = "psci"; 38 clocks = <&ccu CLK_CPUX>; 39 clock-latency-ns = <244144>; /* 8 32k periods */ 40 #cooling-cells = <2>; 41 }; 42 43 cpu2: cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <2>; 47 enable-method = "psci"; 48 clocks = <&ccu CLK_CPUX>; 49 clock-latency-ns = <244144>; /* 8 32k periods */ 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 reg = <3>; 57 enable-method = "psci"; 58 clocks = <&ccu CLK_CPUX>; 59 clock-latency-ns = <244144>; /* 8 32k periods */ 60 #cooling-cells = <2>; 61 }; 62 }; 63 64 de: display-engine { 65 compatible = "allwinner,sun50i-h6-display-engine"; 66 allwinner,pipelines = <&mixer0>; 67 status = "disabled"; 68 }; 69 70 osc24M: osc24M_clk { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "osc24M"; 75 }; 76 77 pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-0.2"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges; 108 109 bus@1000000 { 110 compatible = "allwinner,sun50i-h6-de3", 111 "allwinner,sun50i-a64-de2"; 112 reg = <0x1000000 0x400000>; 113 allwinner,sram = <&de2_sram 1>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges = <0 0x1000000 0x400000>; 117 118 display_clocks: clock@0 { 119 compatible = "allwinner,sun50i-h6-de3-clk"; 120 reg = <0x0 0x10000>; 121 clocks = <&ccu CLK_DE>, 122 <&ccu CLK_BUS_DE>; 123 clock-names = "mod", 124 "bus"; 125 resets = <&ccu RST_BUS_DE>; 126 #clock-cells = <1>; 127 #reset-cells = <1>; 128 }; 129 130 mixer0: mixer@100000 { 131 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 132 reg = <0x100000 0x100000>; 133 clocks = <&display_clocks CLK_BUS_MIXER0>, 134 <&display_clocks CLK_MIXER0>; 135 clock-names = "bus", 136 "mod"; 137 resets = <&display_clocks RST_MIXER0>; 138 iommus = <&iommu 0>; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 mixer0_out: port@1 { 145 reg = <1>; 146 147 mixer0_out_tcon_top_mixer0: endpoint { 148 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 149 }; 150 }; 151 }; 152 }; 153 }; 154 155 video-codec@1c0e000 { 156 compatible = "allwinner,sun50i-h6-video-engine"; 157 reg = <0x01c0e000 0x2000>; 158 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 159 <&ccu CLK_MBUS_VE>; 160 clock-names = "ahb", "mod", "ram"; 161 resets = <&ccu RST_BUS_VE>; 162 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 163 allwinner,sram = <&ve_sram 1>; 164 }; 165 166 gpu: gpu@1800000 { 167 compatible = "allwinner,sun50i-h6-mali", 168 "arm,mali-t720"; 169 reg = <0x01800000 0x4000>; 170 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 173 interrupt-names = "job", "mmu", "gpu"; 174 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 175 clock-names = "core", "bus"; 176 resets = <&ccu RST_BUS_GPU>; 177 status = "disabled"; 178 }; 179 180 crypto: crypto@1904000 { 181 compatible = "allwinner,sun50i-h6-crypto"; 182 reg = <0x01904000 0x1000>; 183 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 185 clock-names = "bus", "mod", "ram"; 186 resets = <&ccu RST_BUS_CE>; 187 }; 188 189 syscon: syscon@3000000 { 190 compatible = "allwinner,sun50i-h6-system-control", 191 "allwinner,sun50i-a64-system-control"; 192 reg = <0x03000000 0x1000>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges; 196 197 sram_c: sram@28000 { 198 compatible = "mmio-sram"; 199 reg = <0x00028000 0x1e000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 ranges = <0 0x00028000 0x1e000>; 203 204 de2_sram: sram-section@0 { 205 compatible = "allwinner,sun50i-h6-sram-c", 206 "allwinner,sun50i-a64-sram-c"; 207 reg = <0x0000 0x1e000>; 208 }; 209 }; 210 211 sram_c1: sram@1a00000 { 212 compatible = "mmio-sram"; 213 reg = <0x01a00000 0x200000>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges = <0 0x01a00000 0x200000>; 217 218 ve_sram: sram-section@0 { 219 compatible = "allwinner,sun50i-h6-sram-c1", 220 "allwinner,sun4i-a10-sram-c1"; 221 reg = <0x000000 0x200000>; 222 }; 223 }; 224 }; 225 226 ccu: clock@3001000 { 227 compatible = "allwinner,sun50i-h6-ccu"; 228 reg = <0x03001000 0x1000>; 229 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 230 clock-names = "hosc", "losc", "iosc"; 231 #clock-cells = <1>; 232 #reset-cells = <1>; 233 }; 234 235 dma: dma-controller@3002000 { 236 compatible = "allwinner,sun50i-h6-dma"; 237 reg = <0x03002000 0x1000>; 238 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 240 clock-names = "bus", "mbus"; 241 dma-channels = <16>; 242 dma-requests = <46>; 243 resets = <&ccu RST_BUS_DMA>; 244 #dma-cells = <1>; 245 }; 246 247 msgbox: mailbox@3003000 { 248 compatible = "allwinner,sun50i-h6-msgbox", 249 "allwinner,sun6i-a31-msgbox"; 250 reg = <0x03003000 0x1000>; 251 clocks = <&ccu CLK_BUS_MSGBOX>; 252 resets = <&ccu RST_BUS_MSGBOX>; 253 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 254 #mbox-cells = <1>; 255 }; 256 257 sid: efuse@3006000 { 258 compatible = "allwinner,sun50i-h6-sid"; 259 reg = <0x03006000 0x400>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 263 ths_calibration: thermal-sensor-calibration@14 { 264 reg = <0x14 0x8>; 265 }; 266 267 cpu_speed_grade: cpu-speed-grade@1c { 268 reg = <0x1c 0x4>; 269 }; 270 }; 271 272 watchdog: watchdog@30090a0 { 273 compatible = "allwinner,sun50i-h6-wdt", 274 "allwinner,sun6i-a31-wdt"; 275 reg = <0x030090a0 0x20>; 276 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&osc24M>; 278 /* Broken on some H6 boards */ 279 status = "disabled"; 280 }; 281 282 pwm: pwm@300a000 { 283 compatible = "allwinner,sun50i-h6-pwm"; 284 reg = <0x0300a000 0x400>; 285 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 286 clock-names = "mod", "bus"; 287 resets = <&ccu RST_BUS_PWM>; 288 #pwm-cells = <3>; 289 status = "disabled"; 290 }; 291 292 pio: pinctrl@300b000 { 293 compatible = "allwinner,sun50i-h6-pinctrl"; 294 reg = <0x0300b000 0x400>; 295 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 300 clock-names = "apb", "hosc", "losc"; 301 gpio-controller; 302 #gpio-cells = <3>; 303 interrupt-controller; 304 #interrupt-cells = <3>; 305 306 ext_rgmii_pins: rgmii-pins { 307 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 308 "PD5", "PD7", "PD8", "PD9", "PD10", 309 "PD11", "PD12", "PD13", "PD19", "PD20"; 310 function = "emac"; 311 drive-strength = <40>; 312 }; 313 314 hdmi_pins: hdmi-pins { 315 pins = "PH8", "PH9", "PH10"; 316 function = "hdmi"; 317 }; 318 319 i2c0_pins: i2c0-pins { 320 pins = "PD25", "PD26"; 321 function = "i2c0"; 322 }; 323 324 i2c1_pins: i2c1-pins { 325 pins = "PH5", "PH6"; 326 function = "i2c1"; 327 }; 328 329 i2c2_pins: i2c2-pins { 330 pins = "PD23", "PD24"; 331 function = "i2c2"; 332 }; 333 334 mmc0_pins: mmc0-pins { 335 pins = "PF0", "PF1", "PF2", "PF3", 336 "PF4", "PF5"; 337 function = "mmc0"; 338 drive-strength = <30>; 339 bias-pull-up; 340 }; 341 342 /omit-if-no-ref/ 343 mmc1_pins: mmc1-pins { 344 pins = "PG0", "PG1", "PG2", "PG3", 345 "PG4", "PG5"; 346 function = "mmc1"; 347 drive-strength = <30>; 348 bias-pull-up; 349 }; 350 351 mmc2_pins: mmc2-pins { 352 pins = "PC1", "PC4", "PC5", "PC6", 353 "PC7", "PC8", "PC9", "PC10", 354 "PC11", "PC12", "PC13", "PC14"; 355 function = "mmc2"; 356 drive-strength = <30>; 357 bias-pull-up; 358 }; 359 360 /omit-if-no-ref/ 361 spi0_pins: spi0-pins { 362 pins = "PC0", "PC2", "PC3"; 363 function = "spi0"; 364 }; 365 366 /* pin shared with MMC2-CMD (eMMC) */ 367 /omit-if-no-ref/ 368 spi0_cs_pin: spi0-cs-pin { 369 pins = "PC5"; 370 function = "spi0"; 371 }; 372 373 /omit-if-no-ref/ 374 spi1_pins: spi1-pins { 375 pins = "PH4", "PH5", "PH6"; 376 function = "spi1"; 377 }; 378 379 /omit-if-no-ref/ 380 spi1_cs_pin: spi1-cs-pin { 381 pins = "PH3"; 382 function = "spi1"; 383 }; 384 385 spdif_tx_pin: spdif-tx-pin { 386 pins = "PH7"; 387 function = "spdif"; 388 }; 389 390 uart0_ph_pins: uart0-ph-pins { 391 pins = "PH0", "PH1"; 392 function = "uart0"; 393 }; 394 395 uart1_pins: uart1-pins { 396 pins = "PG6", "PG7"; 397 function = "uart1"; 398 }; 399 400 uart1_rts_cts_pins: uart1-rts-cts-pins { 401 pins = "PG8", "PG9"; 402 function = "uart1"; 403 }; 404 }; 405 406 gic: interrupt-controller@3021000 { 407 compatible = "arm,gic-400"; 408 reg = <0x03021000 0x1000>, 409 <0x03022000 0x2000>, 410 <0x03024000 0x2000>, 411 <0x03026000 0x2000>; 412 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 413 interrupt-controller; 414 #interrupt-cells = <3>; 415 }; 416 417 iommu: iommu@30f0000 { 418 compatible = "allwinner,sun50i-h6-iommu"; 419 reg = <0x030f0000 0x10000>; 420 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&ccu CLK_BUS_IOMMU>; 422 resets = <&ccu RST_BUS_IOMMU>; 423 #iommu-cells = <1>; 424 }; 425 426 mmc0: mmc@4020000 { 427 compatible = "allwinner,sun50i-h6-mmc", 428 "allwinner,sun50i-a64-mmc"; 429 reg = <0x04020000 0x1000>; 430 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 431 clock-names = "ahb", "mmc"; 432 resets = <&ccu RST_BUS_MMC0>; 433 reset-names = "ahb"; 434 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&mmc0_pins>; 437 status = "disabled"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 442 mmc1: mmc@4021000 { 443 compatible = "allwinner,sun50i-h6-mmc", 444 "allwinner,sun50i-a64-mmc"; 445 reg = <0x04021000 0x1000>; 446 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 447 clock-names = "ahb", "mmc"; 448 resets = <&ccu RST_BUS_MMC1>; 449 reset-names = "ahb"; 450 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&mmc1_pins>; 453 status = "disabled"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 }; 457 458 mmc2: mmc@4022000 { 459 compatible = "allwinner,sun50i-h6-emmc", 460 "allwinner,sun50i-a64-emmc"; 461 reg = <0x04022000 0x1000>; 462 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 463 clock-names = "ahb", "mmc"; 464 resets = <&ccu RST_BUS_MMC2>; 465 reset-names = "ahb"; 466 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&mmc2_pins>; 469 status = "disabled"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 }; 473 474 uart0: serial@5000000 { 475 compatible = "snps,dw-apb-uart"; 476 reg = <0x05000000 0x400>; 477 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 478 reg-shift = <2>; 479 reg-io-width = <4>; 480 clocks = <&ccu CLK_BUS_UART0>; 481 resets = <&ccu RST_BUS_UART0>; 482 status = "disabled"; 483 }; 484 485 uart1: serial@5000400 { 486 compatible = "snps,dw-apb-uart"; 487 reg = <0x05000400 0x400>; 488 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 489 reg-shift = <2>; 490 reg-io-width = <4>; 491 clocks = <&ccu CLK_BUS_UART1>; 492 resets = <&ccu RST_BUS_UART1>; 493 status = "disabled"; 494 }; 495 496 uart2: serial@5000800 { 497 compatible = "snps,dw-apb-uart"; 498 reg = <0x05000800 0x400>; 499 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 500 reg-shift = <2>; 501 reg-io-width = <4>; 502 clocks = <&ccu CLK_BUS_UART2>; 503 resets = <&ccu RST_BUS_UART2>; 504 status = "disabled"; 505 }; 506 507 uart3: serial@5000c00 { 508 compatible = "snps,dw-apb-uart"; 509 reg = <0x05000c00 0x400>; 510 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 511 reg-shift = <2>; 512 reg-io-width = <4>; 513 clocks = <&ccu CLK_BUS_UART3>; 514 resets = <&ccu RST_BUS_UART3>; 515 status = "disabled"; 516 }; 517 518 i2c0: i2c@5002000 { 519 compatible = "allwinner,sun50i-h6-i2c", 520 "allwinner,sun6i-a31-i2c"; 521 reg = <0x05002000 0x400>; 522 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&ccu CLK_BUS_I2C0>; 524 resets = <&ccu RST_BUS_I2C0>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&i2c0_pins>; 527 status = "disabled"; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 }; 531 532 i2c1: i2c@5002400 { 533 compatible = "allwinner,sun50i-h6-i2c", 534 "allwinner,sun6i-a31-i2c"; 535 reg = <0x05002400 0x400>; 536 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&ccu CLK_BUS_I2C1>; 538 resets = <&ccu RST_BUS_I2C1>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c1_pins>; 541 status = "disabled"; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 }; 545 546 i2c2: i2c@5002800 { 547 compatible = "allwinner,sun50i-h6-i2c", 548 "allwinner,sun6i-a31-i2c"; 549 reg = <0x05002800 0x400>; 550 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&ccu CLK_BUS_I2C2>; 552 resets = <&ccu RST_BUS_I2C2>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&i2c2_pins>; 555 status = "disabled"; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 }; 559 560 spi0: spi@5010000 { 561 compatible = "allwinner,sun50i-h6-spi", 562 "allwinner,sun8i-h3-spi"; 563 reg = <0x05010000 0x1000>; 564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 566 clock-names = "ahb", "mod"; 567 dmas = <&dma 22>, <&dma 22>; 568 dma-names = "rx", "tx"; 569 resets = <&ccu RST_BUS_SPI0>; 570 status = "disabled"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 }; 574 575 spi1: spi@5011000 { 576 compatible = "allwinner,sun50i-h6-spi", 577 "allwinner,sun8i-h3-spi"; 578 reg = <0x05011000 0x1000>; 579 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 581 clock-names = "ahb", "mod"; 582 dmas = <&dma 23>, <&dma 23>; 583 dma-names = "rx", "tx"; 584 resets = <&ccu RST_BUS_SPI1>; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 590 emac: ethernet@5020000 { 591 compatible = "allwinner,sun50i-h6-emac", 592 "allwinner,sun50i-a64-emac"; 593 syscon = <&syscon>; 594 reg = <0x05020000 0x10000>; 595 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 596 interrupt-names = "macirq"; 597 resets = <&ccu RST_BUS_EMAC>; 598 reset-names = "stmmaceth"; 599 clocks = <&ccu CLK_BUS_EMAC>; 600 clock-names = "stmmaceth"; 601 status = "disabled"; 602 603 mdio: mdio { 604 compatible = "snps,dwmac-mdio"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 }; 608 }; 609 610 spdif: spdif@5093000 { 611 #sound-dai-cells = <0>; 612 compatible = "allwinner,sun50i-h6-spdif"; 613 reg = <0x05093000 0x400>; 614 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 616 clock-names = "apb", "spdif"; 617 resets = <&ccu RST_BUS_SPDIF>; 618 dmas = <&dma 2>; 619 dma-names = "tx"; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&spdif_tx_pin>; 622 status = "disabled"; 623 }; 624 625 usb2otg: usb@5100000 { 626 compatible = "allwinner,sun50i-h6-musb", 627 "allwinner,sun8i-a33-musb"; 628 reg = <0x05100000 0x0400>; 629 clocks = <&ccu CLK_BUS_OTG>; 630 resets = <&ccu RST_BUS_OTG>; 631 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 632 interrupt-names = "mc"; 633 phys = <&usb2phy 0>; 634 phy-names = "usb"; 635 extcon = <&usb2phy 0>; 636 status = "disabled"; 637 }; 638 639 usb2phy: phy@5100400 { 640 compatible = "allwinner,sun50i-h6-usb-phy"; 641 reg = <0x05100400 0x24>, 642 <0x05101800 0x4>, 643 <0x05311800 0x4>; 644 reg-names = "phy_ctrl", 645 "pmu0", 646 "pmu3"; 647 clocks = <&ccu CLK_USB_PHY0>, 648 <&ccu CLK_USB_PHY3>; 649 clock-names = "usb0_phy", 650 "usb3_phy"; 651 resets = <&ccu RST_USB_PHY0>, 652 <&ccu RST_USB_PHY3>; 653 reset-names = "usb0_reset", 654 "usb3_reset"; 655 status = "disabled"; 656 #phy-cells = <1>; 657 }; 658 659 ehci0: usb@5101000 { 660 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 661 reg = <0x05101000 0x100>; 662 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&ccu CLK_BUS_OHCI0>, 664 <&ccu CLK_BUS_EHCI0>, 665 <&ccu CLK_USB_OHCI0>; 666 resets = <&ccu RST_BUS_OHCI0>, 667 <&ccu RST_BUS_EHCI0>; 668 status = "disabled"; 669 }; 670 671 ohci0: usb@5101400 { 672 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 673 reg = <0x05101400 0x100>; 674 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&ccu CLK_BUS_OHCI0>, 676 <&ccu CLK_USB_OHCI0>; 677 resets = <&ccu RST_BUS_OHCI0>; 678 status = "disabled"; 679 }; 680 681 dwc3: dwc3@5200000 { 682 compatible = "snps,dwc3"; 683 reg = <0x05200000 0x10000>; 684 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&ccu CLK_BUS_XHCI>, 686 <&ccu CLK_BUS_XHCI>, 687 <&rtc 0>; 688 clock-names = "ref", "bus_early", "suspend"; 689 resets = <&ccu RST_BUS_XHCI>; 690 /* 691 * The datasheet of the chip doesn't declare the 692 * peripheral function, and there's no boards known 693 * to have a USB Type-B port routed to the port. 694 * In addition, no one has tested the peripheral 695 * function yet. 696 * So set the dr_mode to "host" in the DTSI file. 697 */ 698 dr_mode = "host"; 699 phys = <&usb3phy>; 700 phy-names = "usb3-phy"; 701 status = "disabled"; 702 }; 703 704 usb3phy: phy@5210000 { 705 compatible = "allwinner,sun50i-h6-usb3-phy"; 706 reg = <0x5210000 0x10000>; 707 clocks = <&ccu CLK_USB_PHY1>; 708 resets = <&ccu RST_USB_PHY1>; 709 #phy-cells = <0>; 710 status = "disabled"; 711 }; 712 713 ehci3: usb@5311000 { 714 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 715 reg = <0x05311000 0x100>; 716 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&ccu CLK_BUS_OHCI3>, 718 <&ccu CLK_BUS_EHCI3>, 719 <&ccu CLK_USB_OHCI3>; 720 resets = <&ccu RST_BUS_OHCI3>, 721 <&ccu RST_BUS_EHCI3>; 722 phys = <&usb2phy 3>; 723 phy-names = "usb"; 724 status = "disabled"; 725 }; 726 727 ohci3: usb@5311400 { 728 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 729 reg = <0x05311400 0x100>; 730 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&ccu CLK_BUS_OHCI3>, 732 <&ccu CLK_USB_OHCI3>; 733 resets = <&ccu RST_BUS_OHCI3>; 734 phys = <&usb2phy 3>; 735 phy-names = "usb"; 736 status = "disabled"; 737 }; 738 739 hdmi: hdmi@6000000 { 740 compatible = "allwinner,sun50i-h6-dw-hdmi"; 741 reg = <0x06000000 0x10000>; 742 reg-io-width = <1>; 743 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 745 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 746 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 747 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 748 "hdcp-bus"; 749 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 750 reset-names = "ctrl", "hdcp"; 751 phys = <&hdmi_phy>; 752 phy-names = "phy"; 753 pinctrl-names = "default"; 754 pinctrl-0 = <&hdmi_pins>; 755 status = "disabled"; 756 757 ports { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 hdmi_in: port@0 { 762 reg = <0>; 763 764 hdmi_in_tcon_top: endpoint { 765 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 766 }; 767 }; 768 769 hdmi_out: port@1 { 770 reg = <1>; 771 }; 772 }; 773 }; 774 775 hdmi_phy: hdmi-phy@6010000 { 776 compatible = "allwinner,sun50i-h6-hdmi-phy"; 777 reg = <0x06010000 0x10000>; 778 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 779 clock-names = "bus", "mod"; 780 resets = <&ccu RST_BUS_HDMI>; 781 reset-names = "phy"; 782 #phy-cells = <0>; 783 }; 784 785 tcon_top: tcon-top@6510000 { 786 compatible = "allwinner,sun50i-h6-tcon-top"; 787 reg = <0x06510000 0x1000>; 788 clocks = <&ccu CLK_BUS_TCON_TOP>, 789 <&ccu CLK_TCON_TV0>; 790 clock-names = "bus", 791 "tcon-tv0"; 792 clock-output-names = "tcon-top-tv0"; 793 resets = <&ccu RST_BUS_TCON_TOP>; 794 #clock-cells = <1>; 795 796 ports { 797 #address-cells = <1>; 798 #size-cells = <0>; 799 800 tcon_top_mixer0_in: port@0 { 801 #address-cells = <1>; 802 #size-cells = <0>; 803 reg = <0>; 804 805 tcon_top_mixer0_in_mixer0: endpoint@0 { 806 reg = <0>; 807 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 808 }; 809 }; 810 811 tcon_top_mixer0_out: port@1 { 812 #address-cells = <1>; 813 #size-cells = <0>; 814 reg = <1>; 815 816 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 817 reg = <2>; 818 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 819 }; 820 }; 821 822 tcon_top_hdmi_in: port@4 { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 reg = <4>; 826 827 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 828 reg = <0>; 829 remote-endpoint = <&tcon_tv_out_tcon_top>; 830 }; 831 }; 832 833 tcon_top_hdmi_out: port@5 { 834 reg = <5>; 835 836 tcon_top_hdmi_out_hdmi: endpoint { 837 remote-endpoint = <&hdmi_in_tcon_top>; 838 }; 839 }; 840 }; 841 }; 842 843 tcon_tv: lcd-controller@6515000 { 844 compatible = "allwinner,sun50i-h6-tcon-tv", 845 "allwinner,sun8i-r40-tcon-tv"; 846 reg = <0x06515000 0x1000>; 847 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&ccu CLK_BUS_TCON_TV0>, 849 <&tcon_top CLK_TCON_TOP_TV0>; 850 clock-names = "ahb", 851 "tcon-ch1"; 852 resets = <&ccu RST_BUS_TCON_TV0>; 853 reset-names = "lcd"; 854 855 ports { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 859 tcon_tv_in: port@0 { 860 reg = <0>; 861 862 tcon_tv_in_tcon_top_mixer0: endpoint { 863 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 864 }; 865 }; 866 867 tcon_tv_out: port@1 { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 reg = <1>; 871 872 tcon_tv_out_tcon_top: endpoint@1 { 873 reg = <1>; 874 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 875 }; 876 }; 877 }; 878 }; 879 880 rtc: rtc@7000000 { 881 compatible = "allwinner,sun50i-h6-rtc"; 882 reg = <0x07000000 0x400>; 883 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 885 clock-output-names = "osc32k", "osc32k-out", "iosc"; 886 #clock-cells = <1>; 887 }; 888 889 r_ccu: clock@7010000 { 890 compatible = "allwinner,sun50i-h6-r-ccu"; 891 reg = <0x07010000 0x400>; 892 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 893 <&ccu CLK_PLL_PERIPH0>; 894 clock-names = "hosc", "losc", "iosc", "pll-periph"; 895 #clock-cells = <1>; 896 #reset-cells = <1>; 897 }; 898 899 r_watchdog: watchdog@7020400 { 900 compatible = "allwinner,sun50i-h6-wdt", 901 "allwinner,sun6i-a31-wdt"; 902 reg = <0x07020400 0x20>; 903 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&osc24M>; 905 }; 906 907 r_intc: interrupt-controller@7021000 { 908 compatible = "allwinner,sun50i-h6-r-intc", 909 "allwinner,sun6i-a31-r-intc"; 910 interrupt-controller; 911 #interrupt-cells = <2>; 912 reg = <0x07021000 0x400>; 913 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 914 }; 915 916 r_pio: pinctrl@7022000 { 917 compatible = "allwinner,sun50i-h6-r-pinctrl"; 918 reg = <0x07022000 0x400>; 919 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 922 clock-names = "apb", "hosc", "losc"; 923 gpio-controller; 924 #gpio-cells = <3>; 925 interrupt-controller; 926 #interrupt-cells = <3>; 927 928 r_i2c_pins: r-i2c-pins { 929 pins = "PL0", "PL1"; 930 function = "s_i2c"; 931 }; 932 933 r_ir_rx_pin: r-ir-rx-pin { 934 pins = "PL9"; 935 function = "s_cir_rx"; 936 }; 937 }; 938 939 r_ir: ir@7040000 { 940 compatible = "allwinner,sun50i-h6-ir", 941 "allwinner,sun6i-a31-ir"; 942 reg = <0x07040000 0x400>; 943 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&r_ccu CLK_R_APB1_IR>, 945 <&r_ccu CLK_IR>; 946 clock-names = "apb", "ir"; 947 resets = <&r_ccu RST_R_APB1_IR>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&r_ir_rx_pin>; 950 status = "disabled"; 951 }; 952 953 r_i2c: i2c@7081400 { 954 compatible = "allwinner,sun50i-h6-i2c", 955 "allwinner,sun6i-a31-i2c"; 956 reg = <0x07081400 0x400>; 957 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&r_ccu CLK_R_APB2_I2C>; 959 resets = <&r_ccu RST_R_APB2_I2C>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&r_i2c_pins>; 962 status = "disabled"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 }; 966 967 ths: thermal-sensor@5070400 { 968 compatible = "allwinner,sun50i-h6-ths"; 969 reg = <0x05070400 0x100>; 970 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&ccu CLK_BUS_THS>; 972 clock-names = "bus"; 973 resets = <&ccu RST_BUS_THS>; 974 nvmem-cells = <&ths_calibration>; 975 nvmem-cell-names = "calibration"; 976 #thermal-sensor-cells = <1>; 977 }; 978 }; 979 980 thermal-zones { 981 cpu-thermal { 982 polling-delay-passive = <0>; 983 polling-delay = <0>; 984 thermal-sensors = <&ths 0>; 985 986 trips { 987 cpu_alert: cpu-alert { 988 temperature = <85000>; 989 hysteresis = <2000>; 990 type = "passive"; 991 }; 992 993 cpu-crit { 994 temperature = <100000>; 995 hysteresis = <0>; 996 type = "critical"; 997 }; 998 }; 999 1000 cooling-maps { 1001 map0 { 1002 trip = <&cpu_alert>; 1003 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1004 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1005 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1006 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1007 }; 1008 }; 1009 }; 1010 1011 gpu-thermal { 1012 polling-delay-passive = <0>; 1013 polling-delay = <0>; 1014 thermal-sensors = <&ths 1>; 1015 }; 1016 }; 1017}; 1018