1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/device.h> 9 #include <linux/errno.h> 10 #include <linux/io.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 15 #include "hinic_hw_csr.h" 16 #include "hinic_hw_if.h" 17 18 #define PCIE_ATTR_ENTRY 0 19 20 #define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs) 21 22 #define WAIT_HWIF_READY_TIMEOUT 10000 23 24 /** 25 * hinic_msix_attr_set - set message attribute for msix entry 26 * @hwif: the HW interface of a pci function device 27 * @msix_index: msix_index 28 * @pending_limit: the maximum pending interrupt events (unit 8) 29 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 30 * @lli_timer: replenishing period for low latency credit (unit 8 us) 31 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 32 * @resend_timer: maximum wait for resending msix (unit coalesc period) 33 * 34 * Return 0 - Success, negative - Failure 35 **/ 36 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, 37 u8 pending_limit, u8 coalesc_timer, 38 u8 lli_timer, u8 lli_credit_limit, 39 u8 resend_timer) 40 { 41 u32 msix_ctrl, addr; 42 43 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 44 return -EINVAL; 45 46 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | 47 HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) | 48 HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) | 49 HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) | 50 HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER); 51 52 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 53 54 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 55 return 0; 56 } 57 58 /** 59 * hinic_msix_attr_get - get message attribute of msix entry 60 * @hwif: the HW interface of a pci function device 61 * @msix_index: msix_index 62 * @pending_limit: the maximum pending interrupt events (unit 8) 63 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 64 * @lli_timer: replenishing period for low latency credit (unit 8 us) 65 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 66 * @resend_timer: maximum wait for resending msix (unit coalesc period) 67 * 68 * Return 0 - Success, negative - Failure 69 **/ 70 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, 71 u8 *pending_limit, u8 *coalesc_timer, 72 u8 *lli_timer, u8 *lli_credit_limit, 73 u8 *resend_timer) 74 { 75 u32 addr, val; 76 77 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 78 return -EINVAL; 79 80 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 81 val = hinic_hwif_read_reg(hwif, addr); 82 83 *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); 84 *coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER); 85 *lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER); 86 *lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT); 87 *resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER); 88 return 0; 89 } 90 91 /** 92 * hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry 93 * @hwif: the HW interface of a pci function device 94 * @msix_index: msix_index 95 * 96 * Return 0 - Success, negative - Failure 97 **/ 98 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index) 99 { 100 u32 msix_ctrl, addr; 101 102 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 103 return -EINVAL; 104 105 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); 106 addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index); 107 108 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 109 return 0; 110 } 111 112 /** 113 * hinic_set_pf_action - set action on pf channel 114 * @hwif: the HW interface of a pci function device 115 * @action: action on pf channel 116 * 117 * Return 0 - Success, negative - Failure 118 **/ 119 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action) 120 { 121 u32 attr5; 122 123 if (HINIC_IS_VF(hwif)) 124 return; 125 126 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); 127 attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION); 128 attr5 |= HINIC_FA5_SET(action, PF_ACTION); 129 130 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5); 131 } 132 133 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif) 134 { 135 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 136 137 return HINIC_FA4_GET(attr4, OUTBOUND_STATE); 138 } 139 140 void hinic_outbound_state_set(struct hinic_hwif *hwif, 141 enum hinic_outbound_state outbound_state) 142 { 143 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 144 145 attr4 = HINIC_FA4_CLEAR(attr4, OUTBOUND_STATE); 146 attr4 |= HINIC_FA4_SET(outbound_state, OUTBOUND_STATE); 147 148 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 149 } 150 151 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif) 152 { 153 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 154 155 return HINIC_FA4_GET(attr4, DB_STATE); 156 } 157 158 void hinic_db_state_set(struct hinic_hwif *hwif, 159 enum hinic_db_state db_state) 160 { 161 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 162 163 attr4 = HINIC_FA4_CLEAR(attr4, DB_STATE); 164 attr4 |= HINIC_FA4_SET(db_state, DB_STATE); 165 166 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 167 } 168 169 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, 170 enum hinic_msix_state flag) 171 { 172 u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + 173 HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; 174 u32 mask_bits; 175 176 mask_bits = readl(hwif->intr_regs_base + offset); 177 mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 178 179 if (flag) 180 mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 181 182 writel(mask_bits, hwif->intr_regs_base + offset); 183 } 184 185 /** 186 * hwif_ready - test if the HW is ready for use 187 * @hwif: the HW interface of a pci function device 188 * 189 * Return 0 - Success, negative - Failure 190 **/ 191 static int hwif_ready(struct hinic_hwif *hwif) 192 { 193 u32 addr, attr1; 194 195 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 196 attr1 = hinic_hwif_read_reg(hwif, addr); 197 198 if (!HINIC_FA1_GET(attr1, MGMT_INIT_STATUS)) 199 return -EBUSY; 200 201 if (HINIC_IS_VF(hwif)) { 202 if (!HINIC_FA1_GET(attr1, PF_INIT_STATUS)) 203 return -EBUSY; 204 } 205 206 return 0; 207 } 208 209 static int wait_hwif_ready(struct hinic_hwif *hwif) 210 { 211 unsigned long timeout = 0; 212 213 do { 214 if (!hwif_ready(hwif)) 215 return 0; 216 217 usleep_range(999, 1000); 218 timeout++; 219 } while (timeout <= WAIT_HWIF_READY_TIMEOUT); 220 221 dev_err(&hwif->pdev->dev, "Wait for hwif timeout\n"); 222 223 return -EBUSY; 224 } 225 226 /** 227 * set_hwif_attr - set the attributes in the relevant members in hwif 228 * @hwif: the HW interface of a pci function device 229 * @attr0: the first attribute that was read from the hw 230 * @attr1: the second attribute that was read from the hw 231 **/ 232 static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1, 233 u32 attr2) 234 { 235 hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX); 236 hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX); 237 hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX); 238 hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE); 239 240 hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); 241 hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); 242 hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); 243 hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); 244 hwif->attr.global_vf_id_of_pf = HINIC_FA2_GET(attr2, 245 GLOBAL_VF_ID_OF_PF); 246 } 247 248 /** 249 * read_hwif_attr - read the attributes and set members in hwif 250 * @hwif: the HW interface of a pci function device 251 **/ 252 static void read_hwif_attr(struct hinic_hwif *hwif) 253 { 254 u32 addr, attr0, attr1, attr2; 255 256 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 257 attr0 = hinic_hwif_read_reg(hwif, addr); 258 259 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 260 attr1 = hinic_hwif_read_reg(hwif, addr); 261 262 addr = HINIC_CSR_FUNC_ATTR2_ADDR; 263 attr2 = hinic_hwif_read_reg(hwif, addr); 264 265 set_hwif_attr(hwif, attr0, attr1, attr2); 266 } 267 268 /** 269 * set_ppf - try to set hwif as ppf and set the type of hwif in this case 270 * @hwif: the HW interface of a pci function device 271 **/ 272 static void set_ppf(struct hinic_hwif *hwif) 273 { 274 struct hinic_func_attr *attr = &hwif->attr; 275 u32 addr, val, ppf_election; 276 277 /* Read Modify Write */ 278 addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif)); 279 280 val = hinic_hwif_read_reg(hwif, addr); 281 val = HINIC_PPF_ELECTION_CLEAR(val, IDX); 282 283 ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX); 284 285 val |= ppf_election; 286 hinic_hwif_write_reg(hwif, addr, val); 287 288 /* check PPF */ 289 val = hinic_hwif_read_reg(hwif, addr); 290 291 attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); 292 if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif)) 293 attr->func_type = HINIC_PPF; 294 } 295 296 /** 297 * set_dma_attr - set the dma attributes in the HW 298 * @hwif: the HW interface of a pci function device 299 * @entry_idx: the entry index in the dma table 300 * @st: PCIE TLP steering tag 301 * @at: PCIE TLP AT field 302 * @ph: PCIE TLP Processing Hint field 303 * @no_snooping: PCIE TLP No snooping 304 * @tph_en: PCIE TLP Processing Hint Enable 305 **/ 306 static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx, 307 u8 st, u8 at, u8 ph, 308 enum hinic_pcie_nosnoop no_snooping, 309 enum hinic_pcie_tph tph_en) 310 { 311 u32 addr, val, dma_attr_entry; 312 313 /* Read Modify Write */ 314 addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx); 315 316 val = hinic_hwif_read_reg(hwif, addr); 317 val = HINIC_DMA_ATTR_CLEAR(val, ST) & 318 HINIC_DMA_ATTR_CLEAR(val, AT) & 319 HINIC_DMA_ATTR_CLEAR(val, PH) & 320 HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & 321 HINIC_DMA_ATTR_CLEAR(val, TPH_EN); 322 323 dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) | 324 HINIC_DMA_ATTR_SET(at, AT) | 325 HINIC_DMA_ATTR_SET(ph, PH) | 326 HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) | 327 HINIC_DMA_ATTR_SET(tph_en, TPH_EN); 328 329 val |= dma_attr_entry; 330 hinic_hwif_write_reg(hwif, addr, val); 331 } 332 333 /** 334 * dma_attr_table_init - initialize the the default dma attributes 335 * @hwif: the HW interface of a pci function device 336 **/ 337 static void dma_attr_init(struct hinic_hwif *hwif) 338 { 339 set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE, 340 HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE, 341 HINIC_PCIE_SNOOP, HINIC_PCIE_TPH_DISABLE); 342 } 343 344 u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif) 345 { 346 if (!hwif) 347 return 0; 348 349 return hwif->attr.global_vf_id_of_pf; 350 } 351 352 u16 hinic_global_func_id_hw(struct hinic_hwif *hwif) 353 { 354 u32 addr, attr0; 355 356 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 357 attr0 = hinic_hwif_read_reg(hwif, addr); 358 359 return HINIC_FA0_GET(attr0, FUNC_IDX); 360 } 361 362 u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif) 363 { 364 u32 addr, attr0; 365 366 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 367 attr0 = hinic_hwif_read_reg(hwif, addr); 368 369 return HINIC_FA0_GET(attr0, PF_IDX); 370 } 371 372 /** 373 * hinic_init_hwif - initialize the hw interface 374 * @hwif: the HW interface of a pci function device 375 * @pdev: the pci device for acessing PCI resources 376 * 377 * Return 0 - Success, negative - Failure 378 **/ 379 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev) 380 { 381 int err; 382 383 hwif->pdev = pdev; 384 385 hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR); 386 if (!hwif->cfg_regs_bar) { 387 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 388 return -ENOMEM; 389 } 390 391 hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR); 392 if (!hwif->intr_regs_base) { 393 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 394 err = -ENOMEM; 395 goto err_map_intr_bar; 396 } 397 398 err = wait_hwif_ready(hwif); 399 if (err) { 400 dev_err(&pdev->dev, "HW interface is not ready\n"); 401 goto err_hwif_ready; 402 } 403 404 read_hwif_attr(hwif); 405 406 if (HINIC_IS_PF(hwif)) 407 set_ppf(hwif); 408 409 /* No transactionss before DMA is initialized */ 410 dma_attr_init(hwif); 411 return 0; 412 413 err_hwif_ready: 414 iounmap(hwif->intr_regs_base); 415 416 err_map_intr_bar: 417 iounmap(hwif->cfg_regs_bar); 418 419 return err; 420 } 421 422 /** 423 * hinic_free_hwif - free the HW interface 424 * @hwif: the HW interface of a pci function device 425 **/ 426 void hinic_free_hwif(struct hinic_hwif *hwif) 427 { 428 iounmap(hwif->intr_regs_base); 429 iounmap(hwif->cfg_regs_bar); 430 } 431