1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11#include "sdm845.dtsi" 12 13/* PMICs depend on spmi_bus label and so must come after SoC */ 14#include "pm8005.dtsi" 15#include "pm8998.dtsi" 16 17/ { 18 aliases { 19 bluetooth0 = &bluetooth; 20 hsuart0 = &uart6; 21 serial0 = &uart9; 22 wifi0 = &wifi; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 backlight: backlight { 30 compatible = "pwm-backlight"; 31 pwms = <&cros_ec_pwm 0>; 32 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 33 power-supply = <&ppvar_sys>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&ap_edp_bklten>; 36 }; 37 38 /* FIXED REGULATORS - parents above children */ 39 40 /* This is the top level supply and variable voltage */ 41 ppvar_sys: ppvar-sys-regulator { 42 compatible = "regulator-fixed"; 43 regulator-name = "ppvar_sys"; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 /* This divides ppvar_sys by 2, so voltage is variable */ 49 src_vph_pwr: src-vph-pwr-regulator { 50 compatible = "regulator-fixed"; 51 regulator-name = "src_vph_pwr"; 52 53 /* EC turns on with switchcap_on_l; always on for AP */ 54 regulator-always-on; 55 regulator-boot-on; 56 57 vin-supply = <&ppvar_sys>; 58 }; 59 60 pp5000_a: pp5000-a-regulator { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp5000_a"; 63 64 /* EC turns on with en_pp5000_a; always on for AP */ 65 regulator-always-on; 66 regulator-boot-on; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 70 vin-supply = <&ppvar_sys>; 71 }; 72 73 src_vreg_bob: src-vreg-bob-regulator { 74 compatible = "regulator-fixed"; 75 regulator-name = "src_vreg_bob"; 76 77 /* EC turns on with vbob_en; always on for AP */ 78 regulator-always-on; 79 regulator-boot-on; 80 regulator-min-microvolt = <3600000>; 81 regulator-max-microvolt = <3600000>; 82 83 vin-supply = <&ppvar_sys>; 84 }; 85 86 pp3300_dx_edp: pp3300-dx-edp-regulator { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp3300_dx_edp"; 89 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 93 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 94 enable-active-high; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&en_pp3300_dx_edp>; 97 }; 98 99 /* 100 * Apparently RPMh does not provide support for PM8998 S4 because it 101 * is always-on; model it as a fixed regulator. 102 */ 103 src_pp1800_s4a: pm8998-smps4 { 104 compatible = "regulator-fixed"; 105 regulator-name = "src_pp1800_s4a"; 106 107 regulator-min-microvolt = <1800000>; 108 regulator-max-microvolt = <1800000>; 109 110 regulator-always-on; 111 regulator-boot-on; 112 113 vin-supply = <&src_vph_pwr>; 114 }; 115 116 /* BOARD-SPECIFIC TOP LEVEL NODES */ 117 118 gpio-keys { 119 compatible = "gpio-keys"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pen_eject_odl>; 122 123 pen-insert { 124 label = "Pen Insert"; 125 /* Insert = low, eject = high */ 126 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 127 linux,code = <SW_PEN_INSERTED>; 128 linux,input-type = <EV_SW>; 129 wakeup-source; 130 }; 131 }; 132 133 panel: panel { 134 compatible ="innolux,p120zdg-bf1"; 135 power-supply = <&pp3300_dx_edp>; 136 backlight = <&backlight>; 137 no-hpd; 138 139 ports { 140 panel_in: port { 141 panel_in_edp: endpoint { 142 remote-endpoint = <&sn65dsi86_out>; 143 }; 144 }; 145 }; 146 }; 147}; 148 149/* 150 * Reserved memory changes 151 * 152 * Putting this all together (out of order with the rest of the file) to keep 153 * all modifications to the memory map (from sdm845.dtsi) in one place. 154 */ 155 156/* 157 * Our mpss_region is 8MB bigger than the default one and that conflicts 158 * with venus_mem and cdsp_mem. 159 * 160 * For venus_mem we'll delete and re-create at a different address. 161 * 162 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 163 * that also means we need to delete cdsp_pas. 164 */ 165/delete-node/ &venus_mem; 166/delete-node/ &cdsp_mem; 167/delete-node/ &cdsp_pas; 168/delete-node/ &gpu_mem; 169 170/* Increase the size from 120 MB to 128 MB */ 171&mpss_region { 172 reg = <0 0x8e000000 0 0x8000000>; 173}; 174 175/* Increase the size from 2MB to 8MB */ 176&rmtfs_mem { 177 reg = <0 0x88f00000 0 0x800000>; 178}; 179 180/ { 181 reserved-memory { 182 venus_mem: memory@96000000 { 183 reg = <0 0x96000000 0 0x500000>; 184 no-map; 185 }; 186 }; 187}; 188 189&qspi { 190 status = "okay"; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; 193 194 flash@0 { 195 compatible = "jedec,spi-nor"; 196 reg = <0>; 197 198 /* 199 * In theory chip supports up to 104 MHz and controller up 200 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 201 * that for now. b:117440651 202 */ 203 spi-max-frequency = <25000000>; 204 spi-tx-bus-width = <2>; 205 spi-rx-bus-width = <2>; 206 }; 207}; 208 209 210&apps_rsc { 211 pm8998-rpmh-regulators { 212 compatible = "qcom,pm8998-rpmh-regulators"; 213 qcom,pmic-id = "a"; 214 215 vdd-s1-supply = <&src_vph_pwr>; 216 vdd-s2-supply = <&src_vph_pwr>; 217 vdd-s3-supply = <&src_vph_pwr>; 218 vdd-s4-supply = <&src_vph_pwr>; 219 vdd-s5-supply = <&src_vph_pwr>; 220 vdd-s6-supply = <&src_vph_pwr>; 221 vdd-s7-supply = <&src_vph_pwr>; 222 vdd-s8-supply = <&src_vph_pwr>; 223 vdd-s9-supply = <&src_vph_pwr>; 224 vdd-s10-supply = <&src_vph_pwr>; 225 vdd-s11-supply = <&src_vph_pwr>; 226 vdd-s12-supply = <&src_vph_pwr>; 227 vdd-s13-supply = <&src_vph_pwr>; 228 vdd-l1-l27-supply = <&src_pp1025_s7a>; 229 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 230 vdd-l3-l11-supply = <&src_pp1025_s7a>; 231 vdd-l4-l5-supply = <&src_pp1025_s7a>; 232 vdd-l6-supply = <&src_vph_pwr>; 233 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 234 vdd-l9-supply = <&src_pp2040_s5a>; 235 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 236 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 237 vdd-l16-l28-supply = <&src_vreg_bob>; 238 vdd-l18-l22-supply = <&src_vreg_bob>; 239 vdd-l20-l24-supply = <&src_vreg_bob>; 240 vdd-l26-supply = <&src_pp1350_s3a>; 241 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 242 243 src_pp1125_s2a: smps2 { 244 regulator-min-microvolt = <1100000>; 245 regulator-max-microvolt = <1100000>; 246 }; 247 248 src_pp1350_s3a: smps3 { 249 regulator-min-microvolt = <1352000>; 250 regulator-max-microvolt = <1352000>; 251 }; 252 253 src_pp2040_s5a: smps5 { 254 regulator-min-microvolt = <1904000>; 255 regulator-max-microvolt = <2040000>; 256 }; 257 258 src_pp1025_s7a: smps7 { 259 regulator-min-microvolt = <900000>; 260 regulator-max-microvolt = <1028000>; 261 }; 262 263 vdd_qusb_hs0: 264 vdda_hp_pcie_core: 265 vdda_mipi_csi0_0p9: 266 vdda_mipi_csi1_0p9: 267 vdda_mipi_csi2_0p9: 268 vdda_mipi_dsi0_pll: 269 vdda_mipi_dsi1_pll: 270 vdda_qlink_lv: 271 vdda_qlink_lv_ck: 272 vdda_qrefs_0p875: 273 vdda_pcie_core: 274 vdda_pll_cc_ebi01: 275 vdda_pll_cc_ebi23: 276 vdda_sp_sensor: 277 vdda_ufs1_core: 278 vdda_ufs2_core: 279 vdda_usb1_ss_core: 280 vdda_usb2_ss_core: 281 src_pp875_l1a: ldo1 { 282 regulator-min-microvolt = <880000>; 283 regulator-max-microvolt = <880000>; 284 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 285 }; 286 287 vddpx_10: 288 src_pp1200_l2a: ldo2 { 289 regulator-min-microvolt = <1200000>; 290 regulator-max-microvolt = <1200000>; 291 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 292 293 /* TODO: why??? */ 294 regulator-always-on; 295 }; 296 297 pp1000_l3a_sdr845: ldo3 { 298 regulator-min-microvolt = <1000000>; 299 regulator-max-microvolt = <1000000>; 300 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 301 }; 302 303 vdd_wcss_cx: 304 vdd_wcss_mx: 305 vdda_wcss_pll: 306 src_pp800_l5a: ldo5 { 307 regulator-min-microvolt = <800000>; 308 regulator-max-microvolt = <800000>; 309 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 310 }; 311 312 vddpx_13: 313 src_pp1800_l6a: ldo6 { 314 regulator-min-microvolt = <1856000>; 315 regulator-max-microvolt = <1856000>; 316 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 317 }; 318 319 pp1800_l7a_wcn3990: ldo7 { 320 regulator-min-microvolt = <1800000>; 321 regulator-max-microvolt = <1800000>; 322 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 323 }; 324 325 src_pp1200_l8a: ldo8 { 326 regulator-min-microvolt = <1200000>; 327 regulator-max-microvolt = <1248000>; 328 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 329 }; 330 331 pp1800_dx_pen: 332 src_pp1800_l9a: ldo9 { 333 regulator-min-microvolt = <1800000>; 334 regulator-max-microvolt = <1800000>; 335 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 336 }; 337 338 src_pp1800_l10a: ldo10 { 339 regulator-min-microvolt = <1800000>; 340 regulator-max-microvolt = <1800000>; 341 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 342 }; 343 344 pp1000_l11a_sdr845: ldo11 { 345 regulator-min-microvolt = <1000000>; 346 regulator-max-microvolt = <1048000>; 347 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 348 }; 349 350 vdd_qfprom: 351 vdd_qfprom_sp: 352 vdda_apc1_cs_1p8: 353 vdda_gfx_cs_1p8: 354 vdda_qrefs_1p8: 355 vdda_qusb_hs0_1p8: 356 vddpx_11: 357 src_pp1800_l12a: ldo12 { 358 regulator-min-microvolt = <1800000>; 359 regulator-max-microvolt = <1800000>; 360 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 361 }; 362 363 vddpx_2: 364 src_pp2950_l13a: ldo13 { 365 regulator-min-microvolt = <1800000>; 366 regulator-max-microvolt = <2960000>; 367 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 368 }; 369 370 src_pp1800_l14a: ldo14 { 371 regulator-min-microvolt = <1800000>; 372 regulator-max-microvolt = <1800000>; 373 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 374 }; 375 376 src_pp1800_l15a: ldo15 { 377 regulator-min-microvolt = <1800000>; 378 regulator-max-microvolt = <1800000>; 379 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 380 }; 381 382 pp2700_l16a: ldo16 { 383 regulator-min-microvolt = <2704000>; 384 regulator-max-microvolt = <2704000>; 385 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 386 }; 387 388 src_pp1300_l17a: ldo17 { 389 regulator-min-microvolt = <1304000>; 390 regulator-max-microvolt = <1304000>; 391 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 392 }; 393 394 pp2700_l18a: ldo18 { 395 regulator-min-microvolt = <2704000>; 396 regulator-max-microvolt = <2960000>; 397 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 398 }; 399 400 /* 401 * NOTE: this rail should have been called 402 * src_pp3300_l19a in the schematic 403 */ 404 src_pp3000_l19a: ldo19 { 405 regulator-min-microvolt = <3304000>; 406 regulator-max-microvolt = <3304000>; 407 408 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 409 }; 410 411 src_pp2950_l20a: ldo20 { 412 regulator-min-microvolt = <2704000>; 413 regulator-max-microvolt = <2960000>; 414 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 415 }; 416 417 src_pp2950_l21a: ldo21 { 418 regulator-min-microvolt = <2704000>; 419 regulator-max-microvolt = <2960000>; 420 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 421 }; 422 423 pp3300_hub: 424 src_pp3300_l22a: ldo22 { 425 regulator-min-microvolt = <3304000>; 426 regulator-max-microvolt = <3304000>; 427 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 428 /* 429 * HACK: Should add a usb hub node and driver 430 * to turn this on and off at suspend/resume time 431 */ 432 regulator-boot-on; 433 regulator-always-on; 434 }; 435 436 pp3300_l23a_ch1_wcn3990: ldo23 { 437 regulator-min-microvolt = <3000000>; 438 regulator-max-microvolt = <3312000>; 439 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 440 }; 441 442 vdda_qusb_hs0_3p1: 443 src_pp3075_l24a: ldo24 { 444 regulator-min-microvolt = <3088000>; 445 regulator-max-microvolt = <3088000>; 446 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 447 }; 448 449 pp3300_l25a_ch0_wcn3990: ldo25 { 450 regulator-min-microvolt = <3304000>; 451 regulator-max-microvolt = <3304000>; 452 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 453 }; 454 455 pp1200_hub: 456 vdda_hp_pcie_1p2: 457 vdda_hv_ebi0: 458 vdda_hv_ebi1: 459 vdda_hv_ebi2: 460 vdda_hv_ebi3: 461 vdda_mipi_csi_1p25: 462 vdda_mipi_dsi0_1p2: 463 vdda_mipi_dsi1_1p2: 464 vdda_pcie_1p2: 465 vdda_ufs1_1p2: 466 vdda_ufs2_1p2: 467 vdda_usb1_ss_1p2: 468 vdda_usb2_ss_1p2: 469 src_pp1200_l26a: ldo26 { 470 regulator-min-microvolt = <1200000>; 471 regulator-max-microvolt = <1200000>; 472 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 473 }; 474 475 pp3300_dx_pen: 476 src_pp3300_l28a: ldo28 { 477 regulator-min-microvolt = <3304000>; 478 regulator-max-microvolt = <3304000>; 479 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 480 }; 481 482 src_pp1800_lvs1: lvs1 { 483 regulator-min-microvolt = <1800000>; 484 regulator-max-microvolt = <1800000>; 485 }; 486 487 src_pp1800_lvs2: lvs2 { 488 regulator-min-microvolt = <1800000>; 489 regulator-max-microvolt = <1800000>; 490 }; 491 }; 492 493 pm8005-rpmh-regulators { 494 compatible = "qcom,pm8005-rpmh-regulators"; 495 qcom,pmic-id = "c"; 496 497 vdd-s1-supply = <&src_vph_pwr>; 498 vdd-s2-supply = <&src_vph_pwr>; 499 vdd-s3-supply = <&src_vph_pwr>; 500 vdd-s4-supply = <&src_vph_pwr>; 501 502 src_pp600_s3c: smps3 { 503 regulator-min-microvolt = <600000>; 504 regulator-max-microvolt = <600000>; 505 }; 506 }; 507}; 508 509&dsi0 { 510 status = "okay"; 511 vdda-supply = <&vdda_mipi_dsi0_1p2>; 512 513 ports { 514 port@1 { 515 endpoint { 516 remote-endpoint = <&sn65dsi86_in>; 517 data-lanes = <0 1 2 3>; 518 }; 519 }; 520 }; 521}; 522 523&dsi0_phy { 524 status = "okay"; 525 vdds-supply = <&vdda_mipi_dsi0_pll>; 526}; 527 528edp_brij_i2c: &i2c3 { 529 status = "okay"; 530 clock-frequency = <400000>; 531 532 sn65dsi86_bridge: bridge@2d { 533 compatible = "ti,sn65dsi86"; 534 reg = <0x2d>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 537 538 interrupt-parent = <&tlmm>; 539 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 540 541 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 542 543 vpll-supply = <&src_pp1800_s4a>; 544 vccio-supply = <&src_pp1800_s4a>; 545 vcca-supply = <&src_pp1200_l2a>; 546 vcc-supply = <&src_pp1200_l2a>; 547 548 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 549 clock-names = "refclk"; 550 551 ports { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 port@0 { 556 reg = <0>; 557 sn65dsi86_in: endpoint { 558 remote-endpoint = <&dsi0_out>; 559 }; 560 }; 561 562 port@1 { 563 reg = <1>; 564 sn65dsi86_out: endpoint { 565 remote-endpoint = <&panel_in_edp>; 566 }; 567 }; 568 }; 569 }; 570}; 571 572ap_pen_1v8: &i2c11 { 573 status = "okay"; 574 clock-frequency = <400000>; 575 576 digitizer@9 { 577 compatible = "wacom,w9013", "hid-over-i2c"; 578 reg = <0x9>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 581 582 vdd-supply = <&pp3300_dx_pen>; 583 vddl-supply = <&pp1800_dx_pen>; 584 post-power-on-delay-ms = <100>; 585 586 interrupt-parent = <&tlmm>; 587 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 588 589 hid-descr-addr = <0x1>; 590 }; 591}; 592 593amp_i2c: &i2c12 { 594 status = "okay"; 595 clock-frequency = <400000>; 596}; 597 598ap_ts_i2c: &i2c14 { 599 status = "okay"; 600 clock-frequency = <400000>; 601 602 touchscreen@10 { 603 compatible = "elan,ekth3500"; 604 reg = <0x10>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&ts_int_l &ts_reset_l>; 607 608 interrupt-parent = <&tlmm>; 609 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 610 611 vcc33-supply = <&src_pp3300_l28a>; 612 613 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 614 }; 615}; 616 617&lpasscc { 618 status = "okay"; 619}; 620 621&mdss { 622 status = "okay"; 623}; 624 625&mdss_mdp { 626 status = "okay"; 627}; 628 629&qupv3_id_0 { 630 status = "okay"; 631}; 632 633&qupv3_id_1 { 634 status = "okay"; 635}; 636 637&sdhc_2 { 638 status = "okay"; 639 640 pinctrl-names = "default"; 641 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 642 643 vmmc-supply = <&src_pp2950_l21a>; 644 vqmmc-supply = <&vddpx_2>; 645 646 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 647}; 648 649&spi0 { 650 status = "okay"; 651}; 652 653&spi5 { 654 status = "okay"; 655 656 tpm@0 { 657 compatible = "google,cr50"; 658 reg = <0>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&h1_ap_int_odl>; 661 spi-max-frequency = <800000>; 662 interrupt-parent = <&tlmm>; 663 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 664 }; 665}; 666 667&spi10 { 668 status = "okay"; 669 670 cros_ec: ec@0 { 671 compatible = "google,cros-ec-spi"; 672 reg = <0>; 673 interrupt-parent = <&tlmm>; 674 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&ec_ap_int_l>; 677 spi-max-frequency = <3000000>; 678 679 cros_ec_pwm: ec-pwm { 680 compatible = "google,cros-ec-pwm"; 681 #pwm-cells = <1>; 682 }; 683 684 i2c_tunnel: i2c-tunnel { 685 compatible = "google,cros-ec-i2c-tunnel"; 686 google,remote-bus = <0>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 }; 690 691 pdupdate { 692 compatible = "google,cros-ec-pd-update"; 693 }; 694 }; 695}; 696 697#include <arm/cros-ec-keyboard.dtsi> 698#include <arm/cros-ec-sbs.dtsi> 699 700&uart6 { 701 status = "okay"; 702 703 bluetooth: wcn3990-bt { 704 compatible = "qcom,wcn3990-bt"; 705 vddio-supply = <&src_pp1800_s4a>; 706 vddxo-supply = <&pp1800_l7a_wcn3990>; 707 vddrf-supply = <&src_pp1300_l17a>; 708 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 709 max-speed = <3200000>; 710 }; 711}; 712 713&uart9 { 714 status = "okay"; 715}; 716 717&ufs_mem_hc { 718 status = "okay"; 719 720 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 721 722 vcc-supply = <&src_pp2950_l20a>; 723 vcc-max-microamp = <600000>; 724}; 725 726&ufs_mem_phy { 727 status = "okay"; 728 729 vdda-phy-supply = <&vdda_ufs1_core>; 730 vdda-pll-supply = <&vdda_ufs1_1p2>; 731}; 732 733&usb_1 { 734 status = "okay"; 735 736 /* We'll use this as USB 2.0 only */ 737 qcom,select-utmi-as-pipe-clk; 738}; 739 740&usb_1_dwc3 { 741 /* 742 * The hardware design intends this port to be hooked up in peripheral 743 * mode, so we'll hardcode it here. Some details: 744 * - SDM845 expects only a single Type C connector so it has only one 745 * native Type C port but cheza has two Type C connectors. 746 * - The only source of DP is the single native Type C port. 747 * - On cheza we want to be able to hook DP up to _either_ of the 748 * two Type C connectors and want to be able to achieve 4 lanes of DP. 749 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 750 * - In order to make everything work, the native Type C port is always 751 * configured as 4-lanes DP so it's always available. 752 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 753 * sent to the two Type C connectors. 754 * - The extra USB2 lines from the native Type C port are always 755 * setup as "peripheral" so that we can mux them over to one connector 756 * or the other if someone needs the connector configured as a gadget 757 * (but they only get USB2 speeds). 758 * 759 * All the hardware muxes would allow us to hook things up in different 760 * ways to some potential benefit for static configurations (you could 761 * achieve extra USB2 bandwidth by using two different ports for the 762 * two connectors or possibly even get USB3 peripheral mode), but in 763 * each case you end up forcing to disconnect/reconnect an in-use 764 * USB session in some cases depending on what you hotplug into the 765 * other connector. Thus hardcoding this as peripheral makes sense. 766 */ 767 dr_mode = "peripheral"; 768 769 /* 770 * We always need the high speed pins as 4-lanes DP in case someone 771 * hotplugs a DP peripheral. Thus limit this port to a max of high 772 * speed. 773 */ 774 maximum-speed = "high-speed"; 775 776 /* 777 * We don't need the usb3-phy since we run in highspeed mode always, so 778 * re-define these properties removing the superspeed USB PHY reference. 779 */ 780 phys = <&usb_1_hsphy>; 781 phy-names = "usb2-phy"; 782}; 783 784&usb_1_hsphy { 785 status = "okay"; 786 787 vdd-supply = <&vdda_usb1_ss_core>; 788 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 789 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 790 791 qcom,imp-res-offset-value = <8>; 792 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 793 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 794 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 795}; 796 797&usb_2 { 798 status = "okay"; 799}; 800 801&usb_2_dwc3 { 802 /* We have this hooked up to a hub and we always use in host mode */ 803 dr_mode = "host"; 804}; 805 806&usb_2_hsphy { 807 status = "okay"; 808 809 vdd-supply = <&vdda_usb2_ss_core>; 810 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 811 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 812 813 qcom,imp-res-offset-value = <8>; 814 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 815}; 816 817&usb_2_qmpphy { 818 status = "okay"; 819 820 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 821 vdda-pll-supply = <&vdda_usb2_ss_core>; 822}; 823 824&wifi { 825 status = "okay"; 826 827 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 828 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 829 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 830 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 831}; 832 833/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 834 835&qspi_cs0 { 836 pinconf { 837 pins = "gpio90"; 838 bias-disable; 839 }; 840}; 841 842&qspi_clk { 843 pinconf { 844 pins = "gpio95"; 845 bias-disable; 846 }; 847}; 848 849&qspi_data01 { 850 pinconf { 851 pins = "gpio91", "gpio92"; 852 853 /* High-Z when no transfers; nice to park the lines */ 854 bias-pull-up; 855 }; 856}; 857 858&qup_i2c3_default { 859 pinconf { 860 pins = "gpio41", "gpio42"; 861 drive-strength = <2>; 862 863 /* Has external pullup */ 864 bias-disable; 865 }; 866}; 867 868&qup_i2c11_default { 869 pinconf { 870 pins = "gpio31", "gpio32"; 871 drive-strength = <2>; 872 873 /* Has external pullup */ 874 bias-disable; 875 }; 876}; 877 878&qup_i2c12_default { 879 pinconf { 880 pins = "gpio49", "gpio50"; 881 drive-strength = <2>; 882 883 /* Has external pullup */ 884 bias-disable; 885 }; 886}; 887 888&qup_i2c14_default { 889 pinconf { 890 pins = "gpio33", "gpio34"; 891 drive-strength = <2>; 892 893 /* Has external pullup */ 894 bias-disable; 895 }; 896}; 897 898&qup_spi0_default { 899 pinconf { 900 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 901 drive-strength = <2>; 902 bias-disable; 903 }; 904}; 905 906&qup_spi5_default { 907 pinconf { 908 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 909 drive-strength = <2>; 910 bias-disable; 911 }; 912}; 913 914&qup_spi10_default { 915 pinconf { 916 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 917 drive-strength = <2>; 918 bias-disable; 919 }; 920}; 921 922&qup_uart6_default { 923 /* Change pinmux to all 4 pins since CTS and RTS are connected */ 924 pinmux { 925 pins = "gpio45", "gpio46", 926 "gpio47", "gpio48"; 927 }; 928 929 pinconf-cts { 930 /* 931 * Configure a pull-down on 45 (CTS) to match the pull of 932 * the Bluetooth module. 933 */ 934 pins = "gpio45"; 935 bias-pull-down; 936 }; 937 938 pinconf-rts-tx { 939 /* We'll drive 46 (RTS) and 47 (TX), so no pull */ 940 pins = "gpio46", "gpio47"; 941 drive-strength = <2>; 942 bias-disable; 943 }; 944 945 pinconf-rx { 946 /* 947 * Configure a pull-up on 48 (RX). This is needed to avoid 948 * garbage data when the TX pin of the Bluetooth module is 949 * in tri-state (module powered off or not driving the 950 * signal yet). 951 */ 952 pins = "gpio48"; 953 bias-pull-up; 954 }; 955}; 956 957&qup_uart9_default { 958 pinconf-tx { 959 pins = "gpio4"; 960 drive-strength = <2>; 961 bias-disable; 962 }; 963 964 pinconf-rx { 965 pins = "gpio5"; 966 drive-strength = <2>; 967 bias-pull-up; 968 }; 969}; 970 971/* PINCTRL - board-specific pinctrl */ 972&pm8005_gpio { 973 gpio-line-names = "", 974 "", 975 "SLB", 976 ""; 977}; 978 979&pm8998_adc { 980 adc-chan@4d { 981 reg = <ADC5_AMUX_THM1_100K_PU>; 982 label = "sdm_temp"; 983 }; 984 985 adc-chan@4e { 986 reg = <ADC5_AMUX_THM2_100K_PU>; 987 label = "quiet_temp"; 988 }; 989 990 adc-chan@4f { 991 reg = <ADC5_AMUX_THM3_100K_PU>; 992 label = "lte_temp_1"; 993 }; 994 995 adc-chan@50 { 996 reg = <ADC5_AMUX_THM4_100K_PU>; 997 label = "lte_temp_2"; 998 }; 999 1000 adc-chan@51 { 1001 reg = <ADC5_AMUX_THM5_100K_PU>; 1002 label = "charger_temp"; 1003 }; 1004}; 1005 1006&pm8998_gpio { 1007 gpio-line-names = "", 1008 "", 1009 "SW_CTRL", 1010 "", 1011 "", 1012 "", 1013 "", 1014 "", 1015 "", 1016 "", 1017 "", 1018 "", 1019 "", 1020 "", 1021 "", 1022 "", 1023 "", 1024 "", 1025 "", 1026 "", 1027 "", 1028 "CFG_OPT1", 1029 "WCSS_PWR_REQ", 1030 "", 1031 "CFG_OPT2", 1032 "SLB"; 1033}; 1034 1035&tlmm { 1036 /* 1037 * pinctrl settings for pins that have no real owners. 1038 */ 1039 pinctrl-names = "default", "sleep"; 1040 pinctrl-0 = <&bios_flash_wp_r_l>, 1041 <&ap_suspend_l_deassert>; 1042 1043 pinctrl-1 = <&bios_flash_wp_r_l>, 1044 <&ap_suspend_l_assert>; 1045 1046 /* 1047 * Hogs prevent usermode from changing the value. A GPIO can be both 1048 * here and in the pinctrl section. 1049 */ 1050 ap-suspend-l-hog { 1051 gpio-hog; 1052 gpios = <126 GPIO_ACTIVE_LOW>; 1053 output-low; 1054 }; 1055 1056 ap_edp_bklten: ap-edp-bklten { 1057 pinmux { 1058 pins = "gpio37"; 1059 function = "gpio"; 1060 }; 1061 1062 pinconf { 1063 pins = "gpio37"; 1064 drive-strength = <2>; 1065 bias-disable; 1066 }; 1067 }; 1068 1069 bios_flash_wp_r_l: bios-flash-wp-r-l { 1070 pinmux { 1071 pins = "gpio128"; 1072 function = "gpio"; 1073 input-enable; 1074 }; 1075 1076 pinconf { 1077 pins = "gpio128"; 1078 bias-disable; 1079 }; 1080 }; 1081 1082 ec_ap_int_l: ec-ap-int-l { 1083 pinmux { 1084 pins = "gpio122"; 1085 function = "gpio"; 1086 input-enable; 1087 }; 1088 1089 pinconf { 1090 pins = "gpio122"; 1091 bias-pull-up; 1092 }; 1093 }; 1094 1095 edp_brij_en: edp-brij-en { 1096 pinmux { 1097 pins = "gpio102"; 1098 function = "gpio"; 1099 }; 1100 1101 pinconf { 1102 pins = "gpio102"; 1103 drive-strength = <2>; 1104 bias-disable; 1105 }; 1106 }; 1107 1108 edp_brij_irq: edp-brij-irq { 1109 pinmux { 1110 pins = "gpio10"; 1111 function = "gpio"; 1112 }; 1113 1114 pinconf { 1115 pins = "gpio10"; 1116 drive-strength = <2>; 1117 bias-pull-down; 1118 }; 1119 }; 1120 1121 en_pp3300_dx_edp: en-pp3300-dx-edp { 1122 pinmux { 1123 pins = "gpio43"; 1124 function = "gpio"; 1125 }; 1126 1127 pinconf { 1128 pins = "gpio43"; 1129 drive-strength = <2>; 1130 bias-disable; 1131 }; 1132 }; 1133 1134 h1_ap_int_odl: h1-ap-int-odl { 1135 pinmux { 1136 pins = "gpio129"; 1137 function = "gpio"; 1138 input-enable; 1139 }; 1140 1141 pinconf { 1142 pins = "gpio129"; 1143 bias-pull-up; 1144 }; 1145 }; 1146 1147 pen_eject_odl: pen-eject-odl { 1148 pinmux { 1149 pins = "gpio119"; 1150 function = "gpio"; 1151 bias-pull-up; 1152 }; 1153 }; 1154 1155 pen_irq_l: pen-irq-l { 1156 pinmux { 1157 pins = "gpio24"; 1158 function = "gpio"; 1159 }; 1160 1161 pinconf { 1162 pins = "gpio24"; 1163 1164 /* Has external pullup */ 1165 bias-disable; 1166 }; 1167 }; 1168 1169 pen_pdct_l: pen-pdct-l { 1170 pinmux { 1171 pins = "gpio63"; 1172 function = "gpio"; 1173 }; 1174 1175 pinconf { 1176 pins = "gpio63"; 1177 1178 /* Has external pullup */ 1179 bias-disable; 1180 }; 1181 }; 1182 1183 pen_rst_l: pen-rst-l { 1184 pinmux { 1185 pins = "gpio23"; 1186 function = "gpio"; 1187 }; 1188 1189 pinconf { 1190 pins = "gpio23"; 1191 bias-disable; 1192 drive-strength = <2>; 1193 1194 /* 1195 * The pen driver doesn't currently support 1196 * driving this reset line. By specifying 1197 * output-high here we're relying on the fact 1198 * that this pin has a default pulldown at boot 1199 * (which makes sure the pen was in reset if it 1200 * was powered) and then we set it high here to 1201 * take it out of reset. Better would be if the 1202 * pen driver could control this and we could 1203 * remove "output-high" here. 1204 */ 1205 output-high; 1206 }; 1207 }; 1208 1209 sdc2_clk: sdc2-clk { 1210 pinconf { 1211 pins = "sdc2_clk"; 1212 bias-disable; 1213 1214 /* 1215 * It seems that mmc_test reports errors if drive 1216 * strength is not 16. 1217 */ 1218 drive-strength = <16>; 1219 }; 1220 }; 1221 1222 sdc2_cmd: sdc2-cmd { 1223 pinconf { 1224 pins = "sdc2_cmd"; 1225 bias-pull-up; 1226 drive-strength = <16>; 1227 }; 1228 }; 1229 1230 sdc2_data: sdc2-data { 1231 pinconf { 1232 pins = "sdc2_data"; 1233 bias-pull-up; 1234 drive-strength = <16>; 1235 }; 1236 }; 1237 1238 sd_cd_odl: sd-cd-odl { 1239 pinmux { 1240 pins = "gpio44"; 1241 function = "gpio"; 1242 }; 1243 1244 pinconf { 1245 pins = "gpio44"; 1246 bias-pull-up; 1247 }; 1248 }; 1249 1250 ts_int_l: ts-int-l { 1251 pinmux { 1252 pins = "gpio125"; 1253 function = "gpio"; 1254 }; 1255 1256 pinconf { 1257 pins = "gpio125"; 1258 bias-pull-up; 1259 }; 1260 }; 1261 1262 ts_reset_l: ts-reset-l { 1263 pinmux { 1264 pins = "gpio118"; 1265 function = "gpio"; 1266 }; 1267 1268 pinconf { 1269 pins = "gpio118"; 1270 bias-disable; 1271 drive-strength = <2>; 1272 }; 1273 }; 1274 1275 ap_suspend_l_assert: ap_suspend_l_assert { 1276 config { 1277 pins = "gpio126"; 1278 function = "gpio"; 1279 bias-no-pull; 1280 drive-strength = <2>; 1281 output-low; 1282 }; 1283 }; 1284 1285 ap_suspend_l_deassert: ap_suspend_l_deassert { 1286 config { 1287 pins = "gpio126"; 1288 function = "gpio"; 1289 bias-no-pull; 1290 drive-strength = <2>; 1291 output-high; 1292 }; 1293 }; 1294}; 1295