1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation 4 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 5 * 6 * RTAS specific routines for PCI. 7 * 8 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/threads.h> 13 #include <linux/pci.h> 14 #include <linux/string.h> 15 #include <linux/init.h> 16 #include <linux/pgtable.h> 17 18 #include <asm/io.h> 19 #include <asm/irq.h> 20 #include <asm/prom.h> 21 #include <asm/machdep.h> 22 #include <asm/pci-bridge.h> 23 #include <asm/iommu.h> 24 #include <asm/rtas.h> 25 #include <asm/mpic.h> 26 #include <asm/ppc-pci.h> 27 #include <asm/eeh.h> 28 29 /* RTAS tokens */ 30 static int read_pci_config; 31 static int write_pci_config; 32 static int ibm_read_pci_config; 33 static int ibm_write_pci_config; 34 35 static inline int config_access_valid(struct pci_dn *dn, int where) 36 { 37 if (where < 256) 38 return 1; 39 if (where < 4096 && dn->pci_ext_config_space) 40 return 1; 41 42 return 0; 43 } 44 45 int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val) 46 { 47 int returnval = -1; 48 unsigned long buid, addr; 49 int ret; 50 51 if (!pdn) 52 return PCIBIOS_DEVICE_NOT_FOUND; 53 if (!config_access_valid(pdn, where)) 54 return PCIBIOS_BAD_REGISTER_NUMBER; 55 #ifdef CONFIG_EEH 56 if (pdn->edev && pdn->edev->pe && 57 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) 58 return PCIBIOS_SET_FAILED; 59 #endif 60 61 addr = rtas_config_addr(pdn->busno, pdn->devfn, where); 62 buid = pdn->phb->buid; 63 if (buid) { 64 ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval, 65 addr, BUID_HI(buid), BUID_LO(buid), size); 66 } else { 67 ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size); 68 } 69 *val = returnval; 70 71 if (ret) 72 return PCIBIOS_DEVICE_NOT_FOUND; 73 74 return PCIBIOS_SUCCESSFUL; 75 } 76 77 static int rtas_pci_read_config(struct pci_bus *bus, 78 unsigned int devfn, 79 int where, int size, u32 *val) 80 { 81 struct pci_dn *pdn; 82 int ret; 83 84 *val = 0xFFFFFFFF; 85 86 pdn = pci_get_pdn_by_devfn(bus, devfn); 87 88 /* Validity of pdn is checked in here */ 89 ret = rtas_read_config(pdn, where, size, val); 90 if (*val == EEH_IO_ERROR_VALUE(size) && 91 eeh_dev_check_failure(pdn_to_eeh_dev(pdn))) 92 return PCIBIOS_DEVICE_NOT_FOUND; 93 94 return ret; 95 } 96 97 int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val) 98 { 99 unsigned long buid, addr; 100 int ret; 101 102 if (!pdn) 103 return PCIBIOS_DEVICE_NOT_FOUND; 104 if (!config_access_valid(pdn, where)) 105 return PCIBIOS_BAD_REGISTER_NUMBER; 106 #ifdef CONFIG_EEH 107 if (pdn->edev && pdn->edev->pe && 108 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) 109 return PCIBIOS_SET_FAILED; 110 #endif 111 112 addr = rtas_config_addr(pdn->busno, pdn->devfn, where); 113 buid = pdn->phb->buid; 114 if (buid) { 115 ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr, 116 BUID_HI(buid), BUID_LO(buid), size, (ulong) val); 117 } else { 118 ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val); 119 } 120 121 if (ret) 122 return PCIBIOS_DEVICE_NOT_FOUND; 123 124 return PCIBIOS_SUCCESSFUL; 125 } 126 127 static int rtas_pci_write_config(struct pci_bus *bus, 128 unsigned int devfn, 129 int where, int size, u32 val) 130 { 131 struct pci_dn *pdn; 132 133 pdn = pci_get_pdn_by_devfn(bus, devfn); 134 135 /* Validity of pdn is checked in here. */ 136 return rtas_write_config(pdn, where, size, val); 137 } 138 139 static struct pci_ops rtas_pci_ops = { 140 .read = rtas_pci_read_config, 141 .write = rtas_pci_write_config, 142 }; 143 144 static int is_python(struct device_node *dev) 145 { 146 const char *model = of_get_property(dev, "model", NULL); 147 148 if (model && strstr(model, "Python")) 149 return 1; 150 151 return 0; 152 } 153 154 static void python_countermeasures(struct device_node *dev) 155 { 156 struct resource registers; 157 void __iomem *chip_regs; 158 volatile u32 val; 159 160 if (of_address_to_resource(dev, 0, ®isters)) { 161 printk(KERN_ERR "Can't get address for Python workarounds !\n"); 162 return; 163 } 164 165 /* Python's register file is 1 MB in size. */ 166 chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000); 167 168 /* 169 * Firmware doesn't always clear this bit which is critical 170 * for good performance - Anton 171 */ 172 173 #define PRG_CL_RESET_VALID 0x00010000 174 175 val = in_be32(chip_regs + 0xf6030); 176 if (val & PRG_CL_RESET_VALID) { 177 printk(KERN_INFO "Python workaround: "); 178 val &= ~PRG_CL_RESET_VALID; 179 out_be32(chip_regs + 0xf6030, val); 180 /* 181 * We must read it back for changes to 182 * take effect 183 */ 184 val = in_be32(chip_regs + 0xf6030); 185 printk("reg0: %x\n", val); 186 } 187 188 iounmap(chip_regs); 189 } 190 191 void __init init_pci_config_tokens(void) 192 { 193 read_pci_config = rtas_token("read-pci-config"); 194 write_pci_config = rtas_token("write-pci-config"); 195 ibm_read_pci_config = rtas_token("ibm,read-pci-config"); 196 ibm_write_pci_config = rtas_token("ibm,write-pci-config"); 197 } 198 199 unsigned long get_phb_buid(struct device_node *phb) 200 { 201 struct resource r; 202 203 if (ibm_read_pci_config == -1) 204 return 0; 205 if (of_address_to_resource(phb, 0, &r)) 206 return 0; 207 return r.start; 208 } 209 210 static int phb_set_bus_ranges(struct device_node *dev, 211 struct pci_controller *phb) 212 { 213 const __be32 *bus_range; 214 unsigned int len; 215 216 bus_range = of_get_property(dev, "bus-range", &len); 217 if (bus_range == NULL || len < 2 * sizeof(int)) { 218 return 1; 219 } 220 221 phb->first_busno = be32_to_cpu(bus_range[0]); 222 phb->last_busno = be32_to_cpu(bus_range[1]); 223 224 return 0; 225 } 226 227 int rtas_setup_phb(struct pci_controller *phb) 228 { 229 struct device_node *dev = phb->dn; 230 231 if (is_python(dev)) 232 python_countermeasures(dev); 233 234 if (phb_set_bus_ranges(dev, phb)) 235 return 1; 236 237 phb->ops = &rtas_pci_ops; 238 phb->buid = get_phb_buid(dev); 239 240 return 0; 241 } 242