1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * SMP support for power macintosh. 4 * 5 * We support both the old "powersurge" SMP architecture 6 * and the current Core99 (G4 PowerMac) machines. 7 * 8 * Note that we don't support the very first rev. of 9 * Apple/DayStar 2 CPUs board, the one with the funky 10 * watchdog. Hopefully, none of these should be there except 11 * maybe internally to Apple. I should probably still add some 12 * code to detect this card though and disable SMP. --BenH. 13 * 14 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 15 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 16 * 17 * Support for DayStar quad CPU cards 18 * Copyright (C) XLR8, Inc. 1994-2000 19 */ 20 #include <linux/kernel.h> 21 #include <linux/sched.h> 22 #include <linux/sched/hotplug.h> 23 #include <linux/smp.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel_stat.h> 26 #include <linux/delay.h> 27 #include <linux/init.h> 28 #include <linux/spinlock.h> 29 #include <linux/errno.h> 30 #include <linux/hardirq.h> 31 #include <linux/cpu.h> 32 #include <linux/compiler.h> 33 34 #include <asm/ptrace.h> 35 #include <linux/atomic.h> 36 #include <asm/code-patching.h> 37 #include <asm/irq.h> 38 #include <asm/page.h> 39 #include <asm/pgtable.h> 40 #include <asm/sections.h> 41 #include <asm/io.h> 42 #include <asm/prom.h> 43 #include <asm/smp.h> 44 #include <asm/machdep.h> 45 #include <asm/pmac_feature.h> 46 #include <asm/time.h> 47 #include <asm/mpic.h> 48 #include <asm/cacheflush.h> 49 #include <asm/keylargo.h> 50 #include <asm/pmac_low_i2c.h> 51 #include <asm/pmac_pfunc.h> 52 53 #include "pmac.h" 54 55 #undef DEBUG 56 57 #ifdef DEBUG 58 #define DBG(fmt...) udbg_printf(fmt) 59 #else 60 #define DBG(fmt...) 61 #endif 62 63 extern void __secondary_start_pmac_0(void); 64 65 static void (*pmac_tb_freeze)(int freeze); 66 static u64 timebase; 67 static int tb_req; 68 69 #ifdef CONFIG_PPC_PMAC32_PSURGE 70 71 /* 72 * Powersurge (old powermac SMP) support. 73 */ 74 75 /* Addresses for powersurge registers */ 76 #define HAMMERHEAD_BASE 0xf8000000 77 #define HHEAD_CONFIG 0x90 78 #define HHEAD_SEC_INTR 0xc0 79 80 /* register for interrupting the primary processor on the powersurge */ 81 /* N.B. this is actually the ethernet ROM! */ 82 #define PSURGE_PRI_INTR 0xf3019000 83 84 /* register for storing the start address for the secondary processor */ 85 /* N.B. this is the PCI config space address register for the 1st bridge */ 86 #define PSURGE_START 0xf2800000 87 88 /* Daystar/XLR8 4-CPU card */ 89 #define PSURGE_QUAD_REG_ADDR 0xf8800000 90 91 #define PSURGE_QUAD_IRQ_SET 0 92 #define PSURGE_QUAD_IRQ_CLR 1 93 #define PSURGE_QUAD_IRQ_PRIMARY 2 94 #define PSURGE_QUAD_CKSTOP_CTL 3 95 #define PSURGE_QUAD_PRIMARY_ARB 4 96 #define PSURGE_QUAD_BOARD_ID 6 97 #define PSURGE_QUAD_WHICH_CPU 7 98 #define PSURGE_QUAD_CKSTOP_RDBK 8 99 #define PSURGE_QUAD_RESET_CTL 11 100 101 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 102 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 103 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 104 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 105 106 /* virtual addresses for the above */ 107 static volatile u8 __iomem *hhead_base; 108 static volatile u8 __iomem *quad_base; 109 static volatile u32 __iomem *psurge_pri_intr; 110 static volatile u8 __iomem *psurge_sec_intr; 111 static volatile u32 __iomem *psurge_start; 112 113 /* values for psurge_type */ 114 #define PSURGE_NONE -1 115 #define PSURGE_DUAL 0 116 #define PSURGE_QUAD_OKEE 1 117 #define PSURGE_QUAD_COTTON 2 118 #define PSURGE_QUAD_ICEGRASS 3 119 120 /* what sort of powersurge board we have */ 121 static int psurge_type = PSURGE_NONE; 122 123 /* irq for secondary cpus to report */ 124 static struct irq_domain *psurge_host; 125 int psurge_secondary_virq; 126 127 /* 128 * Set and clear IPIs for powersurge. 129 */ 130 static inline void psurge_set_ipi(int cpu) 131 { 132 if (psurge_type == PSURGE_NONE) 133 return; 134 if (cpu == 0) 135 in_be32(psurge_pri_intr); 136 else if (psurge_type == PSURGE_DUAL) 137 out_8(psurge_sec_intr, 0); 138 else 139 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 140 } 141 142 static inline void psurge_clr_ipi(int cpu) 143 { 144 if (cpu > 0) { 145 switch(psurge_type) { 146 case PSURGE_DUAL: 147 out_8(psurge_sec_intr, ~0); 148 case PSURGE_NONE: 149 break; 150 default: 151 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 152 } 153 } 154 } 155 156 /* 157 * On powersurge (old SMP powermac architecture) we don't have 158 * separate IPIs for separate messages like openpic does. Instead 159 * use the generic demux helpers 160 * -- paulus. 161 */ 162 static irqreturn_t psurge_ipi_intr(int irq, void *d) 163 { 164 psurge_clr_ipi(smp_processor_id()); 165 smp_ipi_demux(); 166 167 return IRQ_HANDLED; 168 } 169 170 static void smp_psurge_cause_ipi(int cpu) 171 { 172 psurge_set_ipi(cpu); 173 } 174 175 static int psurge_host_map(struct irq_domain *h, unsigned int virq, 176 irq_hw_number_t hw) 177 { 178 irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq); 179 180 return 0; 181 } 182 183 static const struct irq_domain_ops psurge_host_ops = { 184 .map = psurge_host_map, 185 }; 186 187 static int psurge_secondary_ipi_init(void) 188 { 189 int rc = -ENOMEM; 190 191 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL); 192 193 if (psurge_host) 194 psurge_secondary_virq = irq_create_direct_mapping(psurge_host); 195 196 if (psurge_secondary_virq) 197 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr, 198 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL); 199 200 if (rc) 201 pr_err("Failed to setup secondary cpu IPI\n"); 202 203 return rc; 204 } 205 206 /* 207 * Determine a quad card presence. We read the board ID register, we 208 * force the data bus to change to something else, and we read it again. 209 * It it's stable, then the register probably exist (ugh !) 210 */ 211 static int __init psurge_quad_probe(void) 212 { 213 int type; 214 unsigned int i; 215 216 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 217 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 218 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 219 return PSURGE_DUAL; 220 221 /* looks OK, try a slightly more rigorous test */ 222 /* bogus is not necessarily cacheline-aligned, 223 though I don't suppose that really matters. -- paulus */ 224 for (i = 0; i < 100; i++) { 225 volatile u32 bogus[8]; 226 bogus[(0+i)%8] = 0x00000000; 227 bogus[(1+i)%8] = 0x55555555; 228 bogus[(2+i)%8] = 0xFFFFFFFF; 229 bogus[(3+i)%8] = 0xAAAAAAAA; 230 bogus[(4+i)%8] = 0x33333333; 231 bogus[(5+i)%8] = 0xCCCCCCCC; 232 bogus[(6+i)%8] = 0xCCCCCCCC; 233 bogus[(7+i)%8] = 0x33333333; 234 wmb(); 235 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 236 mb(); 237 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 238 return PSURGE_DUAL; 239 } 240 return type; 241 } 242 243 static void __init psurge_quad_init(void) 244 { 245 int procbits; 246 247 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 248 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 249 if (psurge_type == PSURGE_QUAD_ICEGRASS) 250 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 251 else 252 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 253 mdelay(33); 254 out_8(psurge_sec_intr, ~0); 255 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 256 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 257 if (psurge_type != PSURGE_QUAD_ICEGRASS) 258 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 259 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 260 mdelay(33); 261 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 262 mdelay(33); 263 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 264 mdelay(33); 265 } 266 267 static void __init smp_psurge_probe(void) 268 { 269 int i, ncpus; 270 struct device_node *dn; 271 272 /* We don't do SMP on the PPC601 -- paulus */ 273 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 274 return; 275 276 /* 277 * The powersurge cpu board can be used in the generation 278 * of powermacs that have a socket for an upgradeable cpu card, 279 * including the 7500, 8500, 9500, 9600. 280 * The device tree doesn't tell you if you have 2 cpus because 281 * OF doesn't know anything about the 2nd processor. 282 * Instead we look for magic bits in magic registers, 283 * in the hammerhead memory controller in the case of the 284 * dual-cpu powersurge board. -- paulus. 285 */ 286 dn = of_find_node_by_name(NULL, "hammerhead"); 287 if (dn == NULL) 288 return; 289 of_node_put(dn); 290 291 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 292 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 293 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 294 295 psurge_type = psurge_quad_probe(); 296 if (psurge_type != PSURGE_DUAL) { 297 psurge_quad_init(); 298 /* All released cards using this HW design have 4 CPUs */ 299 ncpus = 4; 300 /* No sure how timebase sync works on those, let's use SW */ 301 smp_ops->give_timebase = smp_generic_give_timebase; 302 smp_ops->take_timebase = smp_generic_take_timebase; 303 } else { 304 iounmap(quad_base); 305 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 306 /* not a dual-cpu card */ 307 iounmap(hhead_base); 308 psurge_type = PSURGE_NONE; 309 return; 310 } 311 ncpus = 2; 312 } 313 314 if (psurge_secondary_ipi_init()) 315 return; 316 317 psurge_start = ioremap(PSURGE_START, 4); 318 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 319 320 /* This is necessary because OF doesn't know about the 321 * secondary cpu(s), and thus there aren't nodes in the 322 * device tree for them, and smp_setup_cpu_maps hasn't 323 * set their bits in cpu_present_mask. 324 */ 325 if (ncpus > NR_CPUS) 326 ncpus = NR_CPUS; 327 for (i = 1; i < ncpus ; ++i) 328 set_cpu_present(i, true); 329 330 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 331 } 332 333 static int __init smp_psurge_kick_cpu(int nr) 334 { 335 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 336 unsigned long a, flags; 337 int i, j; 338 339 /* Defining this here is evil ... but I prefer hiding that 340 * crap to avoid giving people ideas that they can do the 341 * same. 342 */ 343 extern volatile unsigned int cpu_callin_map[NR_CPUS]; 344 345 /* may need to flush here if secondary bats aren't setup */ 346 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 347 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 348 asm volatile("sync"); 349 350 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 351 352 /* This is going to freeze the timeebase, we disable interrupts */ 353 local_irq_save(flags); 354 355 out_be32(psurge_start, start); 356 mb(); 357 358 psurge_set_ipi(nr); 359 360 /* 361 * We can't use udelay here because the timebase is now frozen. 362 */ 363 for (i = 0; i < 2000; ++i) 364 asm volatile("nop" : : : "memory"); 365 psurge_clr_ipi(nr); 366 367 /* 368 * Also, because the timebase is frozen, we must not return to the 369 * caller which will try to do udelay's etc... Instead, we wait -here- 370 * for the CPU to callin. 371 */ 372 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { 373 for (j = 1; j < 10000; j++) 374 asm volatile("nop" : : : "memory"); 375 asm volatile("sync" : : : "memory"); 376 } 377 if (!cpu_callin_map[nr]) 378 goto stuck; 379 380 /* And we do the TB sync here too for standard dual CPU cards */ 381 if (psurge_type == PSURGE_DUAL) { 382 while(!tb_req) 383 barrier(); 384 tb_req = 0; 385 mb(); 386 timebase = get_tb(); 387 mb(); 388 while (timebase) 389 barrier(); 390 mb(); 391 } 392 stuck: 393 /* now interrupt the secondary, restarting both TBs */ 394 if (psurge_type == PSURGE_DUAL) 395 psurge_set_ipi(1); 396 397 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 398 399 return 0; 400 } 401 402 static void __init smp_psurge_setup_cpu(int cpu_nr) 403 { 404 unsigned long flags = IRQF_PERCPU | IRQF_NO_THREAD; 405 int irq; 406 407 if (cpu_nr != 0 || !psurge_start) 408 return; 409 410 /* reset the entry point so if we get another intr we won't 411 * try to startup again */ 412 out_be32(psurge_start, 0x100); 413 irq = irq_create_mapping(NULL, 30); 414 if (request_irq(irq, psurge_ipi_intr, flags, "primary IPI", NULL)) 415 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 416 } 417 418 void __init smp_psurge_take_timebase(void) 419 { 420 if (psurge_type != PSURGE_DUAL) 421 return; 422 423 tb_req = 1; 424 mb(); 425 while (!timebase) 426 barrier(); 427 mb(); 428 set_tb(timebase >> 32, timebase & 0xffffffff); 429 timebase = 0; 430 mb(); 431 set_dec(tb_ticks_per_jiffy/2); 432 } 433 434 void __init smp_psurge_give_timebase(void) 435 { 436 /* Nothing to do here */ 437 } 438 439 /* PowerSurge-style Macs */ 440 struct smp_ops_t psurge_smp_ops = { 441 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ 442 .cause_ipi = smp_psurge_cause_ipi, 443 .cause_nmi_ipi = NULL, 444 .probe = smp_psurge_probe, 445 .kick_cpu = smp_psurge_kick_cpu, 446 .setup_cpu = smp_psurge_setup_cpu, 447 .give_timebase = smp_psurge_give_timebase, 448 .take_timebase = smp_psurge_take_timebase, 449 }; 450 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 451 452 /* 453 * Core 99 and later support 454 */ 455 456 457 static void smp_core99_give_timebase(void) 458 { 459 unsigned long flags; 460 461 local_irq_save(flags); 462 463 while(!tb_req) 464 barrier(); 465 tb_req = 0; 466 (*pmac_tb_freeze)(1); 467 mb(); 468 timebase = get_tb(); 469 mb(); 470 while (timebase) 471 barrier(); 472 mb(); 473 (*pmac_tb_freeze)(0); 474 mb(); 475 476 local_irq_restore(flags); 477 } 478 479 480 static void smp_core99_take_timebase(void) 481 { 482 unsigned long flags; 483 484 local_irq_save(flags); 485 486 tb_req = 1; 487 mb(); 488 while (!timebase) 489 barrier(); 490 mb(); 491 set_tb(timebase >> 32, timebase & 0xffffffff); 492 timebase = 0; 493 mb(); 494 495 local_irq_restore(flags); 496 } 497 498 #ifdef CONFIG_PPC64 499 /* 500 * G5s enable/disable the timebase via an i2c-connected clock chip. 501 */ 502 static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 503 static u8 pmac_tb_pulsar_addr; 504 505 static void smp_core99_cypress_tb_freeze(int freeze) 506 { 507 u8 data; 508 int rc; 509 510 /* Strangely, the device-tree says address is 0xd2, but darwin 511 * accesses 0xd0 ... 512 */ 513 pmac_i2c_setmode(pmac_tb_clock_chip_host, 514 pmac_i2c_mode_combined); 515 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 516 0xd0 | pmac_i2c_read, 517 1, 0x81, &data, 1); 518 if (rc != 0) 519 goto bail; 520 521 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 522 523 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 524 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 525 0xd0 | pmac_i2c_write, 526 1, 0x81, &data, 1); 527 528 bail: 529 if (rc != 0) { 530 printk("Cypress Timebase %s rc: %d\n", 531 freeze ? "freeze" : "unfreeze", rc); 532 panic("Timebase freeze failed !\n"); 533 } 534 } 535 536 537 static void smp_core99_pulsar_tb_freeze(int freeze) 538 { 539 u8 data; 540 int rc; 541 542 pmac_i2c_setmode(pmac_tb_clock_chip_host, 543 pmac_i2c_mode_combined); 544 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 545 pmac_tb_pulsar_addr | pmac_i2c_read, 546 1, 0x2e, &data, 1); 547 if (rc != 0) 548 goto bail; 549 550 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 551 552 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 553 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 554 pmac_tb_pulsar_addr | pmac_i2c_write, 555 1, 0x2e, &data, 1); 556 bail: 557 if (rc != 0) { 558 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 559 freeze ? "freeze" : "unfreeze", rc); 560 panic("Timebase freeze failed !\n"); 561 } 562 } 563 564 static void __init smp_core99_setup_i2c_hwsync(int ncpus) 565 { 566 struct device_node *cc = NULL; 567 struct device_node *p; 568 const char *name = NULL; 569 const u32 *reg; 570 int ok; 571 572 /* Look for the clock chip */ 573 for_each_node_by_name(cc, "i2c-hwclock") { 574 p = of_get_parent(cc); 575 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 576 of_node_put(p); 577 if (!ok) 578 continue; 579 580 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 581 if (pmac_tb_clock_chip_host == NULL) 582 continue; 583 reg = of_get_property(cc, "reg", NULL); 584 if (reg == NULL) 585 continue; 586 switch (*reg) { 587 case 0xd2: 588 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 589 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 590 pmac_tb_pulsar_addr = 0xd2; 591 name = "Pulsar"; 592 } else if (of_device_is_compatible(cc, "cy28508")) { 593 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 594 name = "Cypress"; 595 } 596 break; 597 case 0xd4: 598 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 599 pmac_tb_pulsar_addr = 0xd4; 600 name = "Pulsar"; 601 break; 602 } 603 if (pmac_tb_freeze != NULL) 604 break; 605 } 606 if (pmac_tb_freeze != NULL) { 607 /* Open i2c bus for synchronous access */ 608 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 609 printk(KERN_ERR "Failed top open i2c bus for clock" 610 " sync, fallback to software sync !\n"); 611 goto no_i2c_sync; 612 } 613 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 614 name); 615 return; 616 } 617 no_i2c_sync: 618 pmac_tb_freeze = NULL; 619 pmac_tb_clock_chip_host = NULL; 620 } 621 622 623 624 /* 625 * Newer G5s uses a platform function 626 */ 627 628 static void smp_core99_pfunc_tb_freeze(int freeze) 629 { 630 struct device_node *cpus; 631 struct pmf_args args; 632 633 cpus = of_find_node_by_path("/cpus"); 634 BUG_ON(cpus == NULL); 635 args.count = 1; 636 args.u[0].v = !freeze; 637 pmf_call_function(cpus, "cpu-timebase", &args); 638 of_node_put(cpus); 639 } 640 641 #else /* CONFIG_PPC64 */ 642 643 /* 644 * SMP G4 use a GPIO to enable/disable the timebase. 645 */ 646 647 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 648 649 static void smp_core99_gpio_tb_freeze(int freeze) 650 { 651 if (freeze) 652 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 653 else 654 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 655 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 656 } 657 658 659 #endif /* !CONFIG_PPC64 */ 660 661 static void core99_init_caches(int cpu) 662 { 663 #ifndef CONFIG_PPC64 664 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 665 static long int core99_l2_cache; 666 static long int core99_l3_cache; 667 668 if (!cpu_has_feature(CPU_FTR_L2CR)) 669 return; 670 671 if (cpu == 0) { 672 core99_l2_cache = _get_L2CR(); 673 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 674 } else { 675 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 676 _set_L2CR(0); 677 _set_L2CR(core99_l2_cache); 678 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 679 } 680 681 if (!cpu_has_feature(CPU_FTR_L3CR)) 682 return; 683 684 if (cpu == 0){ 685 core99_l3_cache = _get_L3CR(); 686 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 687 } else { 688 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 689 _set_L3CR(0); 690 _set_L3CR(core99_l3_cache); 691 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 692 } 693 #endif /* !CONFIG_PPC64 */ 694 } 695 696 static void __init smp_core99_setup(int ncpus) 697 { 698 #ifdef CONFIG_PPC64 699 700 /* i2c based HW sync on some G5s */ 701 if (of_machine_is_compatible("PowerMac7,2") || 702 of_machine_is_compatible("PowerMac7,3") || 703 of_machine_is_compatible("RackMac3,1")) 704 smp_core99_setup_i2c_hwsync(ncpus); 705 706 /* pfunc based HW sync on recent G5s */ 707 if (pmac_tb_freeze == NULL) { 708 struct device_node *cpus = 709 of_find_node_by_path("/cpus"); 710 if (cpus && 711 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 712 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 713 printk(KERN_INFO "Processor timebase sync using" 714 " platform function\n"); 715 } 716 } 717 718 #else /* CONFIG_PPC64 */ 719 720 /* GPIO based HW sync on ppc32 Core99 */ 721 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) { 722 struct device_node *cpu; 723 const u32 *tbprop = NULL; 724 725 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 726 cpu = of_find_node_by_type(NULL, "cpu"); 727 if (cpu != NULL) { 728 tbprop = of_get_property(cpu, "timebase-enable", NULL); 729 if (tbprop) 730 core99_tb_gpio = *tbprop; 731 of_node_put(cpu); 732 } 733 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 734 printk(KERN_INFO "Processor timebase sync using" 735 " GPIO 0x%02x\n", core99_tb_gpio); 736 } 737 738 #endif /* CONFIG_PPC64 */ 739 740 /* No timebase sync, fallback to software */ 741 if (pmac_tb_freeze == NULL) { 742 smp_ops->give_timebase = smp_generic_give_timebase; 743 smp_ops->take_timebase = smp_generic_take_timebase; 744 printk(KERN_INFO "Processor timebase sync using software\n"); 745 } 746 747 #ifndef CONFIG_PPC64 748 { 749 int i; 750 751 /* XXX should get this from reg properties */ 752 for (i = 1; i < ncpus; ++i) 753 set_hard_smp_processor_id(i, i); 754 } 755 #endif 756 757 /* 32 bits SMP can't NAP */ 758 if (!of_machine_is_compatible("MacRISC4")) 759 powersave_nap = 0; 760 } 761 762 static void __init smp_core99_probe(void) 763 { 764 struct device_node *cpus; 765 int ncpus = 0; 766 767 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 768 769 /* Count CPUs in the device-tree */ 770 for_each_node_by_type(cpus, "cpu") 771 ++ncpus; 772 773 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 774 775 /* Nothing more to do if less than 2 of them */ 776 if (ncpus <= 1) 777 return; 778 779 /* We need to perform some early initialisations before we can start 780 * setting up SMP as we are running before initcalls 781 */ 782 pmac_pfunc_base_install(); 783 pmac_i2c_init(); 784 785 /* Setup various bits like timebase sync method, ability to nap, ... */ 786 smp_core99_setup(ncpus); 787 788 /* Install IPIs */ 789 mpic_request_ipis(); 790 791 /* Collect l2cr and l3cr values from CPU 0 */ 792 core99_init_caches(0); 793 } 794 795 static int smp_core99_kick_cpu(int nr) 796 { 797 unsigned int save_vector; 798 unsigned long target, flags; 799 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); 800 801 if (nr < 0 || nr > 3) 802 return -ENOENT; 803 804 if (ppc_md.progress) 805 ppc_md.progress("smp_core99_kick_cpu", 0x346); 806 807 local_irq_save(flags); 808 809 /* Save reset vector */ 810 save_vector = *vector; 811 812 /* Setup fake reset vector that does 813 * b __secondary_start_pmac_0 + nr*8 814 */ 815 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 816 patch_branch(vector, target, BRANCH_SET_LINK); 817 818 /* Put some life in our friend */ 819 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 820 821 /* FIXME: We wait a bit for the CPU to take the exception, I should 822 * instead wait for the entry code to set something for me. Well, 823 * ideally, all that crap will be done in prom.c and the CPU left 824 * in a RAM-based wait loop like CHRP. 825 */ 826 mdelay(1); 827 828 /* Restore our exception vector */ 829 patch_instruction(vector, save_vector); 830 831 local_irq_restore(flags); 832 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 833 834 return 0; 835 } 836 837 static void smp_core99_setup_cpu(int cpu_nr) 838 { 839 /* Setup L2/L3 */ 840 if (cpu_nr != 0) 841 core99_init_caches(cpu_nr); 842 843 /* Setup openpic */ 844 mpic_setup_this_cpu(); 845 } 846 847 #ifdef CONFIG_PPC64 848 #ifdef CONFIG_HOTPLUG_CPU 849 static unsigned int smp_core99_host_open; 850 851 static int smp_core99_cpu_prepare(unsigned int cpu) 852 { 853 int rc; 854 855 /* Open i2c bus if it was used for tb sync */ 856 if (pmac_tb_clock_chip_host && !smp_core99_host_open) { 857 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); 858 if (rc) { 859 pr_err("Failed to open i2c bus for time sync\n"); 860 return notifier_from_errno(rc); 861 } 862 smp_core99_host_open = 1; 863 } 864 return 0; 865 } 866 867 static int smp_core99_cpu_online(unsigned int cpu) 868 { 869 /* Close i2c bus if it was used for tb sync */ 870 if (pmac_tb_clock_chip_host && smp_core99_host_open) { 871 pmac_i2c_close(pmac_tb_clock_chip_host); 872 smp_core99_host_open = 0; 873 } 874 return 0; 875 } 876 #endif /* CONFIG_HOTPLUG_CPU */ 877 878 static void __init smp_core99_bringup_done(void) 879 { 880 extern void g5_phy_disable_cpu1(void); 881 882 /* Close i2c bus if it was used for tb sync */ 883 if (pmac_tb_clock_chip_host) 884 pmac_i2c_close(pmac_tb_clock_chip_host); 885 886 /* If we didn't start the second CPU, we must take 887 * it off the bus. 888 */ 889 if (of_machine_is_compatible("MacRISC4") && 890 num_online_cpus() < 2) { 891 set_cpu_present(1, false); 892 g5_phy_disable_cpu1(); 893 } 894 #ifdef CONFIG_HOTPLUG_CPU 895 cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE, 896 "powerpc/pmac:prepare", smp_core99_cpu_prepare, 897 NULL); 898 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online", 899 smp_core99_cpu_online, NULL); 900 #endif 901 902 if (ppc_md.progress) 903 ppc_md.progress("smp_core99_bringup_done", 0x349); 904 } 905 #endif /* CONFIG_PPC64 */ 906 907 #ifdef CONFIG_HOTPLUG_CPU 908 909 static int smp_core99_cpu_disable(void) 910 { 911 int rc = generic_cpu_disable(); 912 if (rc) 913 return rc; 914 915 mpic_cpu_set_priority(0xf); 916 917 return 0; 918 } 919 920 #ifdef CONFIG_PPC32 921 922 static void pmac_cpu_die(void) 923 { 924 int cpu = smp_processor_id(); 925 926 local_irq_disable(); 927 idle_task_exit(); 928 pr_debug("CPU%d offline\n", cpu); 929 generic_set_cpu_dead(cpu); 930 smp_wmb(); 931 mb(); 932 low_cpu_die(); 933 } 934 935 #else /* CONFIG_PPC32 */ 936 937 static void pmac_cpu_die(void) 938 { 939 int cpu = smp_processor_id(); 940 941 local_irq_disable(); 942 idle_task_exit(); 943 944 /* 945 * turn off as much as possible, we'll be 946 * kicked out as this will only be invoked 947 * on core99 platforms for now ... 948 */ 949 950 printk(KERN_INFO "CPU#%d offline\n", cpu); 951 generic_set_cpu_dead(cpu); 952 smp_wmb(); 953 954 /* 955 * Re-enable interrupts. The NAP code needs to enable them 956 * anyways, do it now so we deal with the case where one already 957 * happened while soft-disabled. 958 * We shouldn't get any external interrupts, only decrementer, and the 959 * decrementer handler is safe for use on offline CPUs 960 */ 961 local_irq_enable(); 962 963 while (1) { 964 /* let's not take timer interrupts too often ... */ 965 set_dec(0x7fffffff); 966 967 /* Enter NAP mode */ 968 power4_idle(); 969 } 970 } 971 972 #endif /* else CONFIG_PPC32 */ 973 #endif /* CONFIG_HOTPLUG_CPU */ 974 975 /* Core99 Macs (dual G4s and G5s) */ 976 static struct smp_ops_t core99_smp_ops = { 977 .message_pass = smp_mpic_message_pass, 978 .probe = smp_core99_probe, 979 #ifdef CONFIG_PPC64 980 .bringup_done = smp_core99_bringup_done, 981 #endif 982 .kick_cpu = smp_core99_kick_cpu, 983 .setup_cpu = smp_core99_setup_cpu, 984 .give_timebase = smp_core99_give_timebase, 985 .take_timebase = smp_core99_take_timebase, 986 #if defined(CONFIG_HOTPLUG_CPU) 987 .cpu_disable = smp_core99_cpu_disable, 988 .cpu_die = generic_cpu_die, 989 #endif 990 }; 991 992 void __init pmac_setup_smp(void) 993 { 994 struct device_node *np; 995 996 /* Check for Core99 */ 997 np = of_find_node_by_name(NULL, "uni-n"); 998 if (!np) 999 np = of_find_node_by_name(NULL, "u3"); 1000 if (!np) 1001 np = of_find_node_by_name(NULL, "u4"); 1002 if (np) { 1003 of_node_put(np); 1004 smp_ops = &core99_smp_ops; 1005 } 1006 #ifdef CONFIG_PPC_PMAC32_PSURGE 1007 else { 1008 /* We have to set bits in cpu_possible_mask here since the 1009 * secondary CPU(s) aren't in the device tree. Various 1010 * things won't be initialized for CPUs not in the possible 1011 * map, so we really need to fix it up here. 1012 */ 1013 int cpu; 1014 1015 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) 1016 set_cpu_possible(cpu, true); 1017 smp_ops = &psurge_smp_ops; 1018 } 1019 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 1020 1021 #ifdef CONFIG_HOTPLUG_CPU 1022 ppc_md.cpu_die = pmac_cpu_die; 1023 #endif 1024 } 1025 1026 1027