1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
8
9description: |
10  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11  clock generators providing from 3 to 12 output clocks.
12
13  When referencing the provided clock in the DT using phandle and clock
14  specifier, the following mapping applies:
15
16  - 5P49V5923:
17    0 -- OUT0_SEL_I2CB
18    1 -- OUT1
19    2 -- OUT2
20
21  - 5P49V5933:
22    0 -- OUT0_SEL_I2CB
23    1 -- OUT1
24    2 -- OUT4
25
26  - other parts:
27    0 -- OUT0_SEL_I2CB
28    1 -- OUT1
29    2 -- OUT2
30    3 -- OUT3
31    4 -- OUT4
32
33maintainers:
34  - Luca Ceresoli <luca@lucaceresoli.net>
35
36properties:
37  compatible:
38    enum:
39      - idt,5p49v5923
40      - idt,5p49v5925
41      - idt,5p49v5933
42      - idt,5p49v5935
43      - idt,5p49v6901
44      - idt,5p49v6965
45
46  reg:
47    description: I2C device address
48    enum: [ 0x68, 0x6a ]
49
50  '#clock-cells':
51    const: 1
52
53patternProperties:
54  "^OUT[1-4]$":
55    type: object
56    description:
57      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
58      Configuration" in the Versaclock 5/6/6E Family Register Description
59      and Programming Guide.
60    properties:
61      idt,mode:
62        description:
63          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
64        $ref: /schemas/types.yaml#/definitions/uint32
65        minimum: 0
66        maximum: 6
67      idt,voltage-microvolt:
68        description: The output drive voltage.
69        enum: [ 1800000, 2500000, 3300000 ]
70      idt,slew-percent:
71        description: The Slew rate control for CMOS single-ended.
72        $ref: /schemas/types.yaml#/definitions/uint32
73        enum: [ 80, 85, 90, 100 ]
74
75required:
76  - compatible
77  - reg
78  - '#clock-cells'
79
80allOf:
81  - if:
82      properties:
83        compatible:
84          enum:
85            - idt,5p49v5933
86            - idt,5p49v5935
87    then:
88      # Devices with builtin crystal + optional external input
89      properties:
90        clock-names:
91          const: clkin
92        clocks:
93          maxItems: 1
94    else:
95      # Devices without builtin crystal
96      properties:
97        clock-names:
98          minItems: 1
99          maxItems: 2
100          items:
101            enum: [ xin, clkin ]
102        clocks:
103          minItems: 1
104          maxItems: 2
105      required:
106        - clock-names
107        - clocks
108
109examples:
110  - |
111    #include <dt-bindings/clk/versaclock.h>
112
113    /* 25MHz reference crystal */
114    ref25: ref25m {
115        compatible = "fixed-clock";
116        #clock-cells = <0>;
117        clock-frequency = <25000000>;
118    };
119
120    i2c@0 {
121        reg = <0x0 0x100>;
122        #address-cells = <1>;
123        #size-cells = <0>;
124
125        /* IDT 5P49V5923 I2C clock generator */
126        vc5: clock-generator@6a {
127            compatible = "idt,5p49v5923";
128            reg = <0x6a>;
129            #clock-cells = <1>;
130
131            /* Connect XIN input to 25MHz reference */
132            clocks = <&ref25m>;
133            clock-names = "xin";
134
135            OUT1 {
136                idt,drive-mode = <VC5_CMOSD>;
137                idt,voltage-microvolts = <1800000>;
138                idt,slew-percent = <80>;
139            };
140
141            OUT4 {
142                idt,drive-mode = <VC5_LVDS>;
143            };
144        };
145    };
146
147    /* Consumer referencing the 5P49V5923 pin OUT1 */
148    consumer {
149        /* ... */
150        clocks = <&vc5 1>;
151        /* ... */
152    };
153
154...
155