1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 346 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 347 * frames should be flooded or not. 348 */ 349 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 350 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 351 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 352 } 353 354 static void b53_enable_vlan(struct b53_device *dev, bool enable, 355 bool enable_filtering) 356 { 357 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 358 359 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 362 363 if (is5325(dev) || is5365(dev)) { 364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 366 } else if (is63xx(dev)) { 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 369 } else { 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 371 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 372 } 373 374 if (enable) { 375 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 376 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 377 vc4 &= ~VC4_ING_VID_CHECK_MASK; 378 if (enable_filtering) { 379 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 380 vc5 |= VC5_DROP_VTABLE_MISS; 381 } else { 382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 383 vc5 &= ~VC5_DROP_VTABLE_MISS; 384 } 385 386 if (is5325(dev)) 387 vc0 &= ~VC0_RESERVED_1; 388 389 if (is5325(dev) || is5365(dev)) 390 vc1 |= VC1_RX_MCST_TAG_EN; 391 392 } else { 393 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 394 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 395 vc4 &= ~VC4_ING_VID_CHECK_MASK; 396 vc5 &= ~VC5_DROP_VTABLE_MISS; 397 398 if (is5325(dev) || is5365(dev)) 399 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 400 else 401 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 402 403 if (is5325(dev) || is5365(dev)) 404 vc1 &= ~VC1_RX_MCST_TAG_EN; 405 } 406 407 if (!is5325(dev) && !is5365(dev)) 408 vc5 &= ~VC5_VID_FFF_EN; 409 410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 412 413 if (is5325(dev) || is5365(dev)) { 414 /* enable the high 8 bit vid check on 5325 */ 415 if (is5325(dev) && enable) 416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 417 VC3_HIGH_8BIT_EN); 418 else 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 420 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 423 } else if (is63xx(dev)) { 424 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 427 } else { 428 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 429 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 431 } 432 433 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 434 435 dev->vlan_enabled = enable; 436 } 437 438 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 439 { 440 u32 port_mask = 0; 441 u16 max_size = JMS_MIN_SIZE; 442 443 if (is5325(dev) || is5365(dev)) 444 return -EINVAL; 445 446 if (enable) { 447 port_mask = dev->enabled_ports; 448 max_size = JMS_MAX_SIZE; 449 if (allow_10_100) 450 port_mask |= JPM_10_100_JUMBO_EN; 451 } 452 453 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 454 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 455 } 456 457 static int b53_flush_arl(struct b53_device *dev, u8 mask) 458 { 459 unsigned int i; 460 461 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 462 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 463 464 for (i = 0; i < 10; i++) { 465 u8 fast_age_ctrl; 466 467 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 468 &fast_age_ctrl); 469 470 if (!(fast_age_ctrl & FAST_AGE_DONE)) 471 goto out; 472 473 msleep(1); 474 } 475 476 return -ETIMEDOUT; 477 out: 478 /* Only age dynamic entries (default behavior) */ 479 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 480 return 0; 481 } 482 483 static int b53_fast_age_port(struct b53_device *dev, int port) 484 { 485 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 486 487 return b53_flush_arl(dev, FAST_AGE_PORT); 488 } 489 490 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 491 { 492 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 493 494 return b53_flush_arl(dev, FAST_AGE_VLAN); 495 } 496 497 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 498 { 499 struct b53_device *dev = ds->priv; 500 unsigned int i; 501 u16 pvlan; 502 503 /* Enable the IMP port to be in the same VLAN as the other ports 504 * on a per-port basis such that we only have Port i and IMP in 505 * the same VLAN. 506 */ 507 b53_for_each_port(dev, i) { 508 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 509 pvlan |= BIT(cpu_port); 510 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 511 } 512 } 513 EXPORT_SYMBOL(b53_imp_vlan_setup); 514 515 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 516 { 517 struct b53_device *dev = ds->priv; 518 unsigned int cpu_port; 519 int ret = 0; 520 u16 pvlan; 521 522 if (!dsa_is_user_port(ds, port)) 523 return 0; 524 525 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 526 527 b53_br_egress_floods(ds, port, true, true); 528 529 if (dev->ops->irq_enable) 530 ret = dev->ops->irq_enable(dev, port); 531 if (ret) 532 return ret; 533 534 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 535 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 536 537 /* Set this port, and only this one to be in the default VLAN, 538 * if member of a bridge, restore its membership prior to 539 * bringing down this port. 540 */ 541 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 542 pvlan &= ~0x1ff; 543 pvlan |= BIT(port); 544 pvlan |= dev->ports[port].vlan_ctl_mask; 545 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 546 547 b53_imp_vlan_setup(ds, cpu_port); 548 549 /* If EEE was enabled, restore it */ 550 if (dev->ports[port].eee.eee_enabled) 551 b53_eee_enable_set(ds, port, true); 552 553 return 0; 554 } 555 EXPORT_SYMBOL(b53_enable_port); 556 557 void b53_disable_port(struct dsa_switch *ds, int port) 558 { 559 struct b53_device *dev = ds->priv; 560 u8 reg; 561 562 /* Disable Tx/Rx for the port */ 563 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 564 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 565 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 566 567 if (dev->ops->irq_disable) 568 dev->ops->irq_disable(dev, port); 569 } 570 EXPORT_SYMBOL(b53_disable_port); 571 572 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 573 { 574 struct b53_device *dev = ds->priv; 575 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 576 u8 hdr_ctl, val; 577 u16 reg; 578 579 /* Resolve which bit controls the Broadcom tag */ 580 switch (port) { 581 case 8: 582 val = BRCM_HDR_P8_EN; 583 break; 584 case 7: 585 val = BRCM_HDR_P7_EN; 586 break; 587 case 5: 588 val = BRCM_HDR_P5_EN; 589 break; 590 default: 591 val = 0; 592 break; 593 } 594 595 /* Enable management mode if tagging is requested */ 596 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 597 if (tag_en) 598 hdr_ctl |= SM_SW_FWD_MODE; 599 else 600 hdr_ctl &= ~SM_SW_FWD_MODE; 601 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 602 603 /* Configure the appropriate IMP port */ 604 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 605 if (port == 8) 606 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 607 else if (port == 5) 608 hdr_ctl |= GC_FRM_MGMT_PORT_M; 609 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 610 611 /* Enable Broadcom tags for IMP port */ 612 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 613 if (tag_en) 614 hdr_ctl |= val; 615 else 616 hdr_ctl &= ~val; 617 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 618 619 /* Registers below are only accessible on newer devices */ 620 if (!is58xx(dev)) 621 return; 622 623 /* Enable reception Broadcom tag for CPU TX (switch RX) to 624 * allow us to tag outgoing frames 625 */ 626 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 627 if (tag_en) 628 reg &= ~BIT(port); 629 else 630 reg |= BIT(port); 631 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 632 633 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 634 * allow delivering frames to the per-port net_devices 635 */ 636 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 637 if (tag_en) 638 reg &= ~BIT(port); 639 else 640 reg |= BIT(port); 641 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 642 } 643 EXPORT_SYMBOL(b53_brcm_hdr_setup); 644 645 static void b53_enable_cpu_port(struct b53_device *dev, int port) 646 { 647 u8 port_ctrl; 648 649 /* BCM5325 CPU port is at 8 */ 650 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 651 port = B53_CPU_PORT; 652 653 port_ctrl = PORT_CTRL_RX_BCST_EN | 654 PORT_CTRL_RX_MCST_EN | 655 PORT_CTRL_RX_UCST_EN; 656 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 657 658 b53_brcm_hdr_setup(dev->ds, port); 659 660 b53_br_egress_floods(dev->ds, port, true, true); 661 } 662 663 static void b53_enable_mib(struct b53_device *dev) 664 { 665 u8 gc; 666 667 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 668 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 669 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 670 } 671 672 static u16 b53_default_pvid(struct b53_device *dev) 673 { 674 if (is5325(dev) || is5365(dev)) 675 return 1; 676 else 677 return 0; 678 } 679 680 int b53_configure_vlan(struct dsa_switch *ds) 681 { 682 struct b53_device *dev = ds->priv; 683 struct b53_vlan vl = { 0 }; 684 struct b53_vlan *v; 685 int i, def_vid; 686 u16 vid; 687 688 def_vid = b53_default_pvid(dev); 689 690 /* clear all vlan entries */ 691 if (is5325(dev) || is5365(dev)) { 692 for (i = def_vid; i < dev->num_vlans; i++) 693 b53_set_vlan_entry(dev, i, &vl); 694 } else { 695 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 696 } 697 698 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); 699 700 b53_for_each_port(dev, i) 701 b53_write16(dev, B53_VLAN_PAGE, 702 B53_VLAN_PORT_DEF_TAG(i), def_vid); 703 704 /* Upon initial call we have not set-up any VLANs, but upon 705 * system resume, we need to restore all VLAN entries. 706 */ 707 for (vid = def_vid; vid < dev->num_vlans; vid++) { 708 v = &dev->vlans[vid]; 709 710 if (!v->members) 711 continue; 712 713 b53_set_vlan_entry(dev, vid, v); 714 b53_fast_age_vlan(dev, vid); 715 } 716 717 return 0; 718 } 719 EXPORT_SYMBOL(b53_configure_vlan); 720 721 static void b53_switch_reset_gpio(struct b53_device *dev) 722 { 723 int gpio = dev->reset_gpio; 724 725 if (gpio < 0) 726 return; 727 728 /* Reset sequence: RESET low(50ms)->high(20ms) 729 */ 730 gpio_set_value(gpio, 0); 731 mdelay(50); 732 733 gpio_set_value(gpio, 1); 734 mdelay(20); 735 736 dev->current_page = 0xff; 737 } 738 739 static int b53_switch_reset(struct b53_device *dev) 740 { 741 unsigned int timeout = 1000; 742 u8 mgmt, reg; 743 744 b53_switch_reset_gpio(dev); 745 746 if (is539x(dev)) { 747 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 748 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 749 } 750 751 /* This is specific to 58xx devices here, do not use is58xx() which 752 * covers the larger Starfigther 2 family, including 7445/7278 which 753 * still use this driver as a library and need to perform the reset 754 * earlier. 755 */ 756 if (dev->chip_id == BCM58XX_DEVICE_ID || 757 dev->chip_id == BCM583XX_DEVICE_ID) { 758 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 759 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 760 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 761 762 do { 763 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 764 if (!(reg & SW_RST)) 765 break; 766 767 usleep_range(1000, 2000); 768 } while (timeout-- > 0); 769 770 if (timeout == 0) 771 return -ETIMEDOUT; 772 } 773 774 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 775 776 if (!(mgmt & SM_SW_FWD_EN)) { 777 mgmt &= ~SM_SW_FWD_MODE; 778 mgmt |= SM_SW_FWD_EN; 779 780 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 781 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 782 783 if (!(mgmt & SM_SW_FWD_EN)) { 784 dev_err(dev->dev, "Failed to enable switch!\n"); 785 return -EINVAL; 786 } 787 } 788 789 b53_enable_mib(dev); 790 791 return b53_flush_arl(dev, FAST_AGE_STATIC); 792 } 793 794 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 795 { 796 struct b53_device *priv = ds->priv; 797 u16 value = 0; 798 int ret; 799 800 if (priv->ops->phy_read16) 801 ret = priv->ops->phy_read16(priv, addr, reg, &value); 802 else 803 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 804 reg * 2, &value); 805 806 return ret ? ret : value; 807 } 808 809 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 810 { 811 struct b53_device *priv = ds->priv; 812 813 if (priv->ops->phy_write16) 814 return priv->ops->phy_write16(priv, addr, reg, val); 815 816 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 817 } 818 819 static int b53_reset_switch(struct b53_device *priv) 820 { 821 /* reset vlans */ 822 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 823 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 824 825 priv->serdes_lane = B53_INVALID_LANE; 826 827 return b53_switch_reset(priv); 828 } 829 830 static int b53_apply_config(struct b53_device *priv) 831 { 832 /* disable switching */ 833 b53_set_forwarding(priv, 0); 834 835 b53_configure_vlan(priv->ds); 836 837 /* enable switching */ 838 b53_set_forwarding(priv, 1); 839 840 return 0; 841 } 842 843 static void b53_reset_mib(struct b53_device *priv) 844 { 845 u8 gc; 846 847 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 848 849 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 850 msleep(1); 851 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 852 msleep(1); 853 } 854 855 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 856 { 857 if (is5365(dev)) 858 return b53_mibs_65; 859 else if (is63xx(dev)) 860 return b53_mibs_63xx; 861 else if (is58xx(dev)) 862 return b53_mibs_58xx; 863 else 864 return b53_mibs; 865 } 866 867 static unsigned int b53_get_mib_size(struct b53_device *dev) 868 { 869 if (is5365(dev)) 870 return B53_MIBS_65_SIZE; 871 else if (is63xx(dev)) 872 return B53_MIBS_63XX_SIZE; 873 else if (is58xx(dev)) 874 return B53_MIBS_58XX_SIZE; 875 else 876 return B53_MIBS_SIZE; 877 } 878 879 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 880 { 881 /* These ports typically do not have built-in PHYs */ 882 switch (port) { 883 case B53_CPU_PORT_25: 884 case 7: 885 case B53_CPU_PORT: 886 return NULL; 887 } 888 889 return mdiobus_get_phy(ds->slave_mii_bus, port); 890 } 891 892 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 893 uint8_t *data) 894 { 895 struct b53_device *dev = ds->priv; 896 const struct b53_mib_desc *mibs = b53_get_mib(dev); 897 unsigned int mib_size = b53_get_mib_size(dev); 898 struct phy_device *phydev; 899 unsigned int i; 900 901 if (stringset == ETH_SS_STATS) { 902 for (i = 0; i < mib_size; i++) 903 strlcpy(data + i * ETH_GSTRING_LEN, 904 mibs[i].name, ETH_GSTRING_LEN); 905 } else if (stringset == ETH_SS_PHY_STATS) { 906 phydev = b53_get_phy_device(ds, port); 907 if (!phydev) 908 return; 909 910 phy_ethtool_get_strings(phydev, data); 911 } 912 } 913 EXPORT_SYMBOL(b53_get_strings); 914 915 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 916 { 917 struct b53_device *dev = ds->priv; 918 const struct b53_mib_desc *mibs = b53_get_mib(dev); 919 unsigned int mib_size = b53_get_mib_size(dev); 920 const struct b53_mib_desc *s; 921 unsigned int i; 922 u64 val = 0; 923 924 if (is5365(dev) && port == 5) 925 port = 8; 926 927 mutex_lock(&dev->stats_mutex); 928 929 for (i = 0; i < mib_size; i++) { 930 s = &mibs[i]; 931 932 if (s->size == 8) { 933 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 934 } else { 935 u32 val32; 936 937 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 938 &val32); 939 val = val32; 940 } 941 data[i] = (u64)val; 942 } 943 944 mutex_unlock(&dev->stats_mutex); 945 } 946 EXPORT_SYMBOL(b53_get_ethtool_stats); 947 948 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 949 { 950 struct phy_device *phydev; 951 952 phydev = b53_get_phy_device(ds, port); 953 if (!phydev) 954 return; 955 956 phy_ethtool_get_stats(phydev, NULL, data); 957 } 958 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 959 960 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 961 { 962 struct b53_device *dev = ds->priv; 963 struct phy_device *phydev; 964 965 if (sset == ETH_SS_STATS) { 966 return b53_get_mib_size(dev); 967 } else if (sset == ETH_SS_PHY_STATS) { 968 phydev = b53_get_phy_device(ds, port); 969 if (!phydev) 970 return 0; 971 972 return phy_ethtool_get_sset_count(phydev); 973 } 974 975 return 0; 976 } 977 EXPORT_SYMBOL(b53_get_sset_count); 978 979 static int b53_setup(struct dsa_switch *ds) 980 { 981 struct b53_device *dev = ds->priv; 982 unsigned int port; 983 int ret; 984 985 ret = b53_reset_switch(dev); 986 if (ret) { 987 dev_err(ds->dev, "failed to reset switch\n"); 988 return ret; 989 } 990 991 b53_reset_mib(dev); 992 993 ret = b53_apply_config(dev); 994 if (ret) 995 dev_err(ds->dev, "failed to apply configuration\n"); 996 997 /* Configure IMP/CPU port, disable all other ports. Enabled 998 * ports will be configured with .port_enable 999 */ 1000 for (port = 0; port < dev->num_ports; port++) { 1001 if (dsa_is_cpu_port(ds, port)) 1002 b53_enable_cpu_port(dev, port); 1003 else 1004 b53_disable_port(ds, port); 1005 } 1006 1007 /* Let DSA handle the case were multiple bridges span the same switch 1008 * device and different VLAN awareness settings are requested, which 1009 * would be breaking filtering semantics for any of the other bridge 1010 * devices. (not hardware supported) 1011 */ 1012 ds->vlan_filtering_is_global = true; 1013 1014 return ret; 1015 } 1016 1017 static void b53_force_link(struct b53_device *dev, int port, int link) 1018 { 1019 u8 reg, val, off; 1020 1021 /* Override the port settings */ 1022 if (port == dev->cpu_port) { 1023 off = B53_PORT_OVERRIDE_CTRL; 1024 val = PORT_OVERRIDE_EN; 1025 } else { 1026 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1027 val = GMII_PO_EN; 1028 } 1029 1030 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1031 reg |= val; 1032 if (link) 1033 reg |= PORT_OVERRIDE_LINK; 1034 else 1035 reg &= ~PORT_OVERRIDE_LINK; 1036 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1037 } 1038 1039 static void b53_force_port_config(struct b53_device *dev, int port, 1040 int speed, int duplex, 1041 bool tx_pause, bool rx_pause) 1042 { 1043 u8 reg, val, off; 1044 1045 /* Override the port settings */ 1046 if (port == dev->cpu_port) { 1047 off = B53_PORT_OVERRIDE_CTRL; 1048 val = PORT_OVERRIDE_EN; 1049 } else { 1050 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1051 val = GMII_PO_EN; 1052 } 1053 1054 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1055 reg |= val; 1056 if (duplex == DUPLEX_FULL) 1057 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1058 else 1059 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1060 1061 switch (speed) { 1062 case 2000: 1063 reg |= PORT_OVERRIDE_SPEED_2000M; 1064 /* fallthrough */ 1065 case SPEED_1000: 1066 reg |= PORT_OVERRIDE_SPEED_1000M; 1067 break; 1068 case SPEED_100: 1069 reg |= PORT_OVERRIDE_SPEED_100M; 1070 break; 1071 case SPEED_10: 1072 reg |= PORT_OVERRIDE_SPEED_10M; 1073 break; 1074 default: 1075 dev_err(dev->dev, "unknown speed: %d\n", speed); 1076 return; 1077 } 1078 1079 if (rx_pause) 1080 reg |= PORT_OVERRIDE_RX_FLOW; 1081 if (tx_pause) 1082 reg |= PORT_OVERRIDE_TX_FLOW; 1083 1084 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1085 } 1086 1087 static void b53_adjust_link(struct dsa_switch *ds, int port, 1088 struct phy_device *phydev) 1089 { 1090 struct b53_device *dev = ds->priv; 1091 struct ethtool_eee *p = &dev->ports[port].eee; 1092 u8 rgmii_ctrl = 0, reg = 0, off; 1093 bool tx_pause = false; 1094 bool rx_pause = false; 1095 1096 if (!phy_is_pseudo_fixed_link(phydev)) 1097 return; 1098 1099 /* Enable flow control on BCM5301x's CPU port */ 1100 if (is5301x(dev) && port == dev->cpu_port) 1101 tx_pause = rx_pause = true; 1102 1103 if (phydev->pause) { 1104 if (phydev->asym_pause) 1105 tx_pause = true; 1106 rx_pause = true; 1107 } 1108 1109 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1110 tx_pause, rx_pause); 1111 b53_force_link(dev, port, phydev->link); 1112 1113 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1114 if (port == 8) 1115 off = B53_RGMII_CTRL_IMP; 1116 else 1117 off = B53_RGMII_CTRL_P(port); 1118 1119 /* Configure the port RGMII clock delay by DLL disabled and 1120 * tx_clk aligned timing (restoring to reset defaults) 1121 */ 1122 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1123 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1124 RGMII_CTRL_TIMING_SEL); 1125 1126 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1127 * sure that we enable the port TX clock internal delay to 1128 * account for this internal delay that is inserted, otherwise 1129 * the switch won't be able to receive correctly. 1130 * 1131 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1132 * any delay neither on transmission nor reception, so the 1133 * BCM53125 must also be configured accordingly to account for 1134 * the lack of delay and introduce 1135 * 1136 * The BCM53125 switch has its RX clock and TX clock control 1137 * swapped, hence the reason why we modify the TX clock path in 1138 * the "RGMII" case 1139 */ 1140 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1141 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1142 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1143 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1144 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1145 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1146 1147 dev_info(ds->dev, "Configured port %d for %s\n", port, 1148 phy_modes(phydev->interface)); 1149 } 1150 1151 /* configure MII port if necessary */ 1152 if (is5325(dev)) { 1153 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1154 ®); 1155 1156 /* reverse mii needs to be enabled */ 1157 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1158 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1159 reg | PORT_OVERRIDE_RV_MII_25); 1160 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1161 ®); 1162 1163 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1164 dev_err(ds->dev, 1165 "Failed to enable reverse MII mode\n"); 1166 return; 1167 } 1168 } 1169 } else if (is5301x(dev)) { 1170 if (port != dev->cpu_port) { 1171 b53_force_port_config(dev, dev->cpu_port, 2000, 1172 DUPLEX_FULL, true, true); 1173 b53_force_link(dev, dev->cpu_port, 1); 1174 } 1175 } 1176 1177 /* Re-negotiate EEE if it was enabled already */ 1178 p->eee_enabled = b53_eee_init(ds, port, phydev); 1179 } 1180 1181 void b53_port_event(struct dsa_switch *ds, int port) 1182 { 1183 struct b53_device *dev = ds->priv; 1184 bool link; 1185 u16 sts; 1186 1187 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1188 link = !!(sts & BIT(port)); 1189 dsa_port_phylink_mac_change(ds, port, link); 1190 } 1191 EXPORT_SYMBOL(b53_port_event); 1192 1193 void b53_phylink_validate(struct dsa_switch *ds, int port, 1194 unsigned long *supported, 1195 struct phylink_link_state *state) 1196 { 1197 struct b53_device *dev = ds->priv; 1198 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1199 1200 if (dev->ops->serdes_phylink_validate) 1201 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1202 1203 /* Allow all the expected bits */ 1204 phylink_set(mask, Autoneg); 1205 phylink_set_port_modes(mask); 1206 phylink_set(mask, Pause); 1207 phylink_set(mask, Asym_Pause); 1208 1209 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1210 * support Gigabit, including Half duplex. 1211 */ 1212 if (state->interface != PHY_INTERFACE_MODE_MII && 1213 state->interface != PHY_INTERFACE_MODE_REVMII && 1214 !phy_interface_mode_is_8023z(state->interface) && 1215 !(is5325(dev) || is5365(dev))) { 1216 phylink_set(mask, 1000baseT_Full); 1217 phylink_set(mask, 1000baseT_Half); 1218 } 1219 1220 if (!phy_interface_mode_is_8023z(state->interface)) { 1221 phylink_set(mask, 10baseT_Half); 1222 phylink_set(mask, 10baseT_Full); 1223 phylink_set(mask, 100baseT_Half); 1224 phylink_set(mask, 100baseT_Full); 1225 } 1226 1227 bitmap_and(supported, supported, mask, 1228 __ETHTOOL_LINK_MODE_MASK_NBITS); 1229 bitmap_and(state->advertising, state->advertising, mask, 1230 __ETHTOOL_LINK_MODE_MASK_NBITS); 1231 1232 phylink_helper_basex_speed(state); 1233 } 1234 EXPORT_SYMBOL(b53_phylink_validate); 1235 1236 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1237 struct phylink_link_state *state) 1238 { 1239 struct b53_device *dev = ds->priv; 1240 int ret = -EOPNOTSUPP; 1241 1242 if ((phy_interface_mode_is_8023z(state->interface) || 1243 state->interface == PHY_INTERFACE_MODE_SGMII) && 1244 dev->ops->serdes_link_state) 1245 ret = dev->ops->serdes_link_state(dev, port, state); 1246 1247 return ret; 1248 } 1249 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1250 1251 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1252 unsigned int mode, 1253 const struct phylink_link_state *state) 1254 { 1255 struct b53_device *dev = ds->priv; 1256 1257 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1258 return; 1259 1260 if ((phy_interface_mode_is_8023z(state->interface) || 1261 state->interface == PHY_INTERFACE_MODE_SGMII) && 1262 dev->ops->serdes_config) 1263 dev->ops->serdes_config(dev, port, mode, state); 1264 } 1265 EXPORT_SYMBOL(b53_phylink_mac_config); 1266 1267 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1268 { 1269 struct b53_device *dev = ds->priv; 1270 1271 if (dev->ops->serdes_an_restart) 1272 dev->ops->serdes_an_restart(dev, port); 1273 } 1274 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1275 1276 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1277 unsigned int mode, 1278 phy_interface_t interface) 1279 { 1280 struct b53_device *dev = ds->priv; 1281 1282 if (mode == MLO_AN_PHY) 1283 return; 1284 1285 if (mode == MLO_AN_FIXED) { 1286 b53_force_link(dev, port, false); 1287 return; 1288 } 1289 1290 if (phy_interface_mode_is_8023z(interface) && 1291 dev->ops->serdes_link_set) 1292 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1293 } 1294 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1295 1296 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1297 unsigned int mode, 1298 phy_interface_t interface, 1299 struct phy_device *phydev, 1300 int speed, int duplex, 1301 bool tx_pause, bool rx_pause) 1302 { 1303 struct b53_device *dev = ds->priv; 1304 1305 if (mode == MLO_AN_PHY) 1306 return; 1307 1308 if (mode == MLO_AN_FIXED) { 1309 b53_force_port_config(dev, port, speed, duplex, 1310 tx_pause, rx_pause); 1311 b53_force_link(dev, port, true); 1312 return; 1313 } 1314 1315 if (phy_interface_mode_is_8023z(interface) && 1316 dev->ops->serdes_link_set) 1317 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1318 } 1319 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1320 1321 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1322 { 1323 struct b53_device *dev = ds->priv; 1324 u16 pvid, new_pvid; 1325 1326 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1327 if (!vlan_filtering) { 1328 /* Filtering is currently enabled, use the default PVID since 1329 * the bridge does not expect tagging anymore 1330 */ 1331 dev->ports[port].pvid = pvid; 1332 new_pvid = b53_default_pvid(dev); 1333 } else { 1334 /* Filtering is currently disabled, restore the previous PVID */ 1335 new_pvid = dev->ports[port].pvid; 1336 } 1337 1338 if (pvid != new_pvid) 1339 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1340 new_pvid); 1341 1342 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1343 1344 return 0; 1345 } 1346 EXPORT_SYMBOL(b53_vlan_filtering); 1347 1348 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1349 const struct switchdev_obj_port_vlan *vlan) 1350 { 1351 struct b53_device *dev = ds->priv; 1352 1353 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1354 return -EOPNOTSUPP; 1355 1356 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1357 * receiving VLAN tagged frames at all, we can still allow the port to 1358 * be configured for egress untagged. 1359 */ 1360 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1361 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1362 return -EINVAL; 1363 1364 if (vlan->vid_end > dev->num_vlans) 1365 return -ERANGE; 1366 1367 b53_enable_vlan(dev, true, ds->vlan_filtering); 1368 1369 return 0; 1370 } 1371 EXPORT_SYMBOL(b53_vlan_prepare); 1372 1373 void b53_vlan_add(struct dsa_switch *ds, int port, 1374 const struct switchdev_obj_port_vlan *vlan) 1375 { 1376 struct b53_device *dev = ds->priv; 1377 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1378 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1379 struct b53_vlan *vl; 1380 u16 vid; 1381 1382 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1383 vl = &dev->vlans[vid]; 1384 1385 b53_get_vlan_entry(dev, vid, vl); 1386 1387 if (vid == 0 && vid == b53_default_pvid(dev)) 1388 untagged = true; 1389 1390 vl->members |= BIT(port); 1391 if (untagged && !dsa_is_cpu_port(ds, port)) 1392 vl->untag |= BIT(port); 1393 else 1394 vl->untag &= ~BIT(port); 1395 1396 b53_set_vlan_entry(dev, vid, vl); 1397 b53_fast_age_vlan(dev, vid); 1398 } 1399 1400 if (pvid && !dsa_is_cpu_port(ds, port)) { 1401 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1402 vlan->vid_end); 1403 b53_fast_age_vlan(dev, vid); 1404 } 1405 } 1406 EXPORT_SYMBOL(b53_vlan_add); 1407 1408 int b53_vlan_del(struct dsa_switch *ds, int port, 1409 const struct switchdev_obj_port_vlan *vlan) 1410 { 1411 struct b53_device *dev = ds->priv; 1412 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1413 struct b53_vlan *vl; 1414 u16 vid; 1415 u16 pvid; 1416 1417 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1418 1419 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1420 vl = &dev->vlans[vid]; 1421 1422 b53_get_vlan_entry(dev, vid, vl); 1423 1424 vl->members &= ~BIT(port); 1425 1426 if (pvid == vid) 1427 pvid = b53_default_pvid(dev); 1428 1429 if (untagged && !dsa_is_cpu_port(ds, port)) 1430 vl->untag &= ~(BIT(port)); 1431 1432 b53_set_vlan_entry(dev, vid, vl); 1433 b53_fast_age_vlan(dev, vid); 1434 } 1435 1436 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1437 b53_fast_age_vlan(dev, pvid); 1438 1439 return 0; 1440 } 1441 EXPORT_SYMBOL(b53_vlan_del); 1442 1443 /* Address Resolution Logic routines */ 1444 static int b53_arl_op_wait(struct b53_device *dev) 1445 { 1446 unsigned int timeout = 10; 1447 u8 reg; 1448 1449 do { 1450 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1451 if (!(reg & ARLTBL_START_DONE)) 1452 return 0; 1453 1454 usleep_range(1000, 2000); 1455 } while (timeout--); 1456 1457 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1458 1459 return -ETIMEDOUT; 1460 } 1461 1462 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1463 { 1464 u8 reg; 1465 1466 if (op > ARLTBL_RW) 1467 return -EINVAL; 1468 1469 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1470 reg |= ARLTBL_START_DONE; 1471 if (op) 1472 reg |= ARLTBL_RW; 1473 else 1474 reg &= ~ARLTBL_RW; 1475 if (dev->vlan_enabled) 1476 reg &= ~ARLTBL_IVL_SVL_SELECT; 1477 else 1478 reg |= ARLTBL_IVL_SVL_SELECT; 1479 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1480 1481 return b53_arl_op_wait(dev); 1482 } 1483 1484 static int b53_arl_read(struct b53_device *dev, u64 mac, 1485 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1486 { 1487 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1488 unsigned int i; 1489 int ret; 1490 1491 ret = b53_arl_op_wait(dev); 1492 if (ret) 1493 return ret; 1494 1495 bitmap_zero(free_bins, dev->num_arl_bins); 1496 1497 /* Read the bins */ 1498 for (i = 0; i < dev->num_arl_bins; i++) { 1499 u64 mac_vid; 1500 u32 fwd_entry; 1501 1502 b53_read64(dev, B53_ARLIO_PAGE, 1503 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1504 b53_read32(dev, B53_ARLIO_PAGE, 1505 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1506 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1507 1508 if (!(fwd_entry & ARLTBL_VALID)) { 1509 set_bit(i, free_bins); 1510 continue; 1511 } 1512 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1513 continue; 1514 if (dev->vlan_enabled && 1515 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1516 continue; 1517 *idx = i; 1518 return 0; 1519 } 1520 1521 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1522 return -ENOSPC; 1523 1524 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1525 1526 return -ENOENT; 1527 } 1528 1529 static int b53_arl_op(struct b53_device *dev, int op, int port, 1530 const unsigned char *addr, u16 vid, bool is_valid) 1531 { 1532 struct b53_arl_entry ent; 1533 u32 fwd_entry; 1534 u64 mac, mac_vid = 0; 1535 u8 idx = 0; 1536 int ret; 1537 1538 /* Convert the array into a 64-bit MAC */ 1539 mac = ether_addr_to_u64(addr); 1540 1541 /* Perform a read for the given MAC and VID */ 1542 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1543 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1544 1545 /* Issue a read operation for this MAC */ 1546 ret = b53_arl_rw_op(dev, 1); 1547 if (ret) 1548 return ret; 1549 1550 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1551 1552 /* If this is a read, just finish now */ 1553 if (op) 1554 return ret; 1555 1556 switch (ret) { 1557 case -ENOSPC: 1558 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1559 addr, vid); 1560 return is_valid ? ret : 0; 1561 case -ENOENT: 1562 /* We could not find a matching MAC, so reset to a new entry */ 1563 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1564 addr, vid, idx); 1565 fwd_entry = 0; 1566 break; 1567 default: 1568 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1569 addr, vid, idx); 1570 break; 1571 } 1572 1573 /* For multicast address, the port is a bitmask and the validity 1574 * is determined by having at least one port being still active 1575 */ 1576 if (!is_multicast_ether_addr(addr)) { 1577 ent.port = port; 1578 ent.is_valid = is_valid; 1579 } else { 1580 if (is_valid) 1581 ent.port |= BIT(port); 1582 else 1583 ent.port &= ~BIT(port); 1584 1585 ent.is_valid = !!(ent.port); 1586 } 1587 1588 ent.vid = vid; 1589 ent.is_static = true; 1590 ent.is_age = false; 1591 memcpy(ent.mac, addr, ETH_ALEN); 1592 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1593 1594 b53_write64(dev, B53_ARLIO_PAGE, 1595 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1596 b53_write32(dev, B53_ARLIO_PAGE, 1597 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1598 1599 return b53_arl_rw_op(dev, 0); 1600 } 1601 1602 int b53_fdb_add(struct dsa_switch *ds, int port, 1603 const unsigned char *addr, u16 vid) 1604 { 1605 struct b53_device *priv = ds->priv; 1606 1607 /* 5325 and 5365 require some more massaging, but could 1608 * be supported eventually 1609 */ 1610 if (is5325(priv) || is5365(priv)) 1611 return -EOPNOTSUPP; 1612 1613 return b53_arl_op(priv, 0, port, addr, vid, true); 1614 } 1615 EXPORT_SYMBOL(b53_fdb_add); 1616 1617 int b53_fdb_del(struct dsa_switch *ds, int port, 1618 const unsigned char *addr, u16 vid) 1619 { 1620 struct b53_device *priv = ds->priv; 1621 1622 return b53_arl_op(priv, 0, port, addr, vid, false); 1623 } 1624 EXPORT_SYMBOL(b53_fdb_del); 1625 1626 static int b53_arl_search_wait(struct b53_device *dev) 1627 { 1628 unsigned int timeout = 1000; 1629 u8 reg; 1630 1631 do { 1632 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1633 if (!(reg & ARL_SRCH_STDN)) 1634 return 0; 1635 1636 if (reg & ARL_SRCH_VLID) 1637 return 0; 1638 1639 usleep_range(1000, 2000); 1640 } while (timeout--); 1641 1642 return -ETIMEDOUT; 1643 } 1644 1645 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1646 struct b53_arl_entry *ent) 1647 { 1648 u64 mac_vid; 1649 u32 fwd_entry; 1650 1651 b53_read64(dev, B53_ARLIO_PAGE, 1652 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1653 b53_read32(dev, B53_ARLIO_PAGE, 1654 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1655 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1656 } 1657 1658 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1659 dsa_fdb_dump_cb_t *cb, void *data) 1660 { 1661 if (!ent->is_valid) 1662 return 0; 1663 1664 if (port != ent->port) 1665 return 0; 1666 1667 return cb(ent->mac, ent->vid, ent->is_static, data); 1668 } 1669 1670 int b53_fdb_dump(struct dsa_switch *ds, int port, 1671 dsa_fdb_dump_cb_t *cb, void *data) 1672 { 1673 struct b53_device *priv = ds->priv; 1674 struct b53_arl_entry results[2]; 1675 unsigned int count = 0; 1676 int ret; 1677 u8 reg; 1678 1679 /* Start search operation */ 1680 reg = ARL_SRCH_STDN; 1681 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1682 1683 do { 1684 ret = b53_arl_search_wait(priv); 1685 if (ret) 1686 return ret; 1687 1688 b53_arl_search_rd(priv, 0, &results[0]); 1689 ret = b53_fdb_copy(port, &results[0], cb, data); 1690 if (ret) 1691 return ret; 1692 1693 if (priv->num_arl_bins > 2) { 1694 b53_arl_search_rd(priv, 1, &results[1]); 1695 ret = b53_fdb_copy(port, &results[1], cb, data); 1696 if (ret) 1697 return ret; 1698 1699 if (!results[0].is_valid && !results[1].is_valid) 1700 break; 1701 } 1702 1703 } while (count++ < b53_max_arl_entries(priv) / 2); 1704 1705 return 0; 1706 } 1707 EXPORT_SYMBOL(b53_fdb_dump); 1708 1709 int b53_mdb_prepare(struct dsa_switch *ds, int port, 1710 const struct switchdev_obj_port_mdb *mdb) 1711 { 1712 struct b53_device *priv = ds->priv; 1713 1714 /* 5325 and 5365 require some more massaging, but could 1715 * be supported eventually 1716 */ 1717 if (is5325(priv) || is5365(priv)) 1718 return -EOPNOTSUPP; 1719 1720 return 0; 1721 } 1722 EXPORT_SYMBOL(b53_mdb_prepare); 1723 1724 void b53_mdb_add(struct dsa_switch *ds, int port, 1725 const struct switchdev_obj_port_mdb *mdb) 1726 { 1727 struct b53_device *priv = ds->priv; 1728 int ret; 1729 1730 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1731 if (ret) 1732 dev_err(ds->dev, "failed to add MDB entry\n"); 1733 } 1734 EXPORT_SYMBOL(b53_mdb_add); 1735 1736 int b53_mdb_del(struct dsa_switch *ds, int port, 1737 const struct switchdev_obj_port_mdb *mdb) 1738 { 1739 struct b53_device *priv = ds->priv; 1740 int ret; 1741 1742 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1743 if (ret) 1744 dev_err(ds->dev, "failed to delete MDB entry\n"); 1745 1746 return ret; 1747 } 1748 EXPORT_SYMBOL(b53_mdb_del); 1749 1750 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1751 { 1752 struct b53_device *dev = ds->priv; 1753 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1754 u16 pvlan, reg; 1755 unsigned int i; 1756 1757 /* On 7278, port 7 which connects to the ASP should only receive 1758 * traffic from matching CFP rules. 1759 */ 1760 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1761 return -EINVAL; 1762 1763 /* Make this port leave the all VLANs join since we will have proper 1764 * VLAN entries from now on 1765 */ 1766 if (is58xx(dev)) { 1767 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1768 reg &= ~BIT(port); 1769 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1770 reg &= ~BIT(cpu_port); 1771 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1772 } 1773 1774 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1775 1776 b53_for_each_port(dev, i) { 1777 if (dsa_to_port(ds, i)->bridge_dev != br) 1778 continue; 1779 1780 /* Add this local port to the remote port VLAN control 1781 * membership and update the remote port bitmask 1782 */ 1783 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1784 reg |= BIT(port); 1785 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1786 dev->ports[i].vlan_ctl_mask = reg; 1787 1788 pvlan |= BIT(i); 1789 } 1790 1791 /* Configure the local port VLAN control membership to include 1792 * remote ports and update the local port bitmask 1793 */ 1794 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1795 dev->ports[port].vlan_ctl_mask = pvlan; 1796 1797 return 0; 1798 } 1799 EXPORT_SYMBOL(b53_br_join); 1800 1801 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1802 { 1803 struct b53_device *dev = ds->priv; 1804 struct b53_vlan *vl = &dev->vlans[0]; 1805 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1806 unsigned int i; 1807 u16 pvlan, reg, pvid; 1808 1809 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1810 1811 b53_for_each_port(dev, i) { 1812 /* Don't touch the remaining ports */ 1813 if (dsa_to_port(ds, i)->bridge_dev != br) 1814 continue; 1815 1816 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1817 reg &= ~BIT(port); 1818 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1819 dev->ports[port].vlan_ctl_mask = reg; 1820 1821 /* Prevent self removal to preserve isolation */ 1822 if (port != i) 1823 pvlan &= ~BIT(i); 1824 } 1825 1826 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1827 dev->ports[port].vlan_ctl_mask = pvlan; 1828 1829 pvid = b53_default_pvid(dev); 1830 1831 /* Make this port join all VLANs without VLAN entries */ 1832 if (is58xx(dev)) { 1833 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1834 reg |= BIT(port); 1835 if (!(reg & BIT(cpu_port))) 1836 reg |= BIT(cpu_port); 1837 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1838 } else { 1839 b53_get_vlan_entry(dev, pvid, vl); 1840 vl->members |= BIT(port) | BIT(cpu_port); 1841 vl->untag |= BIT(port) | BIT(cpu_port); 1842 b53_set_vlan_entry(dev, pvid, vl); 1843 } 1844 } 1845 EXPORT_SYMBOL(b53_br_leave); 1846 1847 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1848 { 1849 struct b53_device *dev = ds->priv; 1850 u8 hw_state; 1851 u8 reg; 1852 1853 switch (state) { 1854 case BR_STATE_DISABLED: 1855 hw_state = PORT_CTRL_DIS_STATE; 1856 break; 1857 case BR_STATE_LISTENING: 1858 hw_state = PORT_CTRL_LISTEN_STATE; 1859 break; 1860 case BR_STATE_LEARNING: 1861 hw_state = PORT_CTRL_LEARN_STATE; 1862 break; 1863 case BR_STATE_FORWARDING: 1864 hw_state = PORT_CTRL_FWD_STATE; 1865 break; 1866 case BR_STATE_BLOCKING: 1867 hw_state = PORT_CTRL_BLOCK_STATE; 1868 break; 1869 default: 1870 dev_err(ds->dev, "invalid STP state: %d\n", state); 1871 return; 1872 } 1873 1874 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1875 reg &= ~PORT_CTRL_STP_STATE_MASK; 1876 reg |= hw_state; 1877 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1878 } 1879 EXPORT_SYMBOL(b53_br_set_stp_state); 1880 1881 void b53_br_fast_age(struct dsa_switch *ds, int port) 1882 { 1883 struct b53_device *dev = ds->priv; 1884 1885 if (b53_fast_age_port(dev, port)) 1886 dev_err(ds->dev, "fast ageing failed\n"); 1887 } 1888 EXPORT_SYMBOL(b53_br_fast_age); 1889 1890 int b53_br_egress_floods(struct dsa_switch *ds, int port, 1891 bool unicast, bool multicast) 1892 { 1893 struct b53_device *dev = ds->priv; 1894 u16 uc, mc; 1895 1896 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 1897 if (unicast) 1898 uc |= BIT(port); 1899 else 1900 uc &= ~BIT(port); 1901 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 1902 1903 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 1904 if (multicast) 1905 mc |= BIT(port); 1906 else 1907 mc &= ~BIT(port); 1908 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 1909 1910 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 1911 if (multicast) 1912 mc |= BIT(port); 1913 else 1914 mc &= ~BIT(port); 1915 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 1916 1917 return 0; 1918 1919 } 1920 EXPORT_SYMBOL(b53_br_egress_floods); 1921 1922 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1923 { 1924 /* Broadcom switches will accept enabling Broadcom tags on the 1925 * following ports: 5, 7 and 8, any other port is not supported 1926 */ 1927 switch (port) { 1928 case B53_CPU_PORT_25: 1929 case 7: 1930 case B53_CPU_PORT: 1931 return true; 1932 } 1933 1934 return false; 1935 } 1936 1937 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 1938 enum dsa_tag_protocol tag_protocol) 1939 { 1940 bool ret = b53_possible_cpu_port(ds, port); 1941 1942 if (!ret) { 1943 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1944 port); 1945 return ret; 1946 } 1947 1948 switch (tag_protocol) { 1949 case DSA_TAG_PROTO_BRCM: 1950 case DSA_TAG_PROTO_BRCM_PREPEND: 1951 dev_warn(ds->dev, 1952 "Port %d is stacked to Broadcom tag switch\n", port); 1953 ret = false; 1954 break; 1955 default: 1956 ret = true; 1957 break; 1958 } 1959 1960 return ret; 1961 } 1962 1963 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 1964 enum dsa_tag_protocol mprot) 1965 { 1966 struct b53_device *dev = ds->priv; 1967 1968 /* Older models (5325, 5365) support a different tag format that we do 1969 * not support in net/dsa/tag_brcm.c yet. 1970 */ 1971 if (is5325(dev) || is5365(dev) || 1972 !b53_can_enable_brcm_tags(ds, port, mprot)) { 1973 dev->tag_protocol = DSA_TAG_PROTO_NONE; 1974 goto out; 1975 } 1976 1977 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1978 * which requires us to use the prepended Broadcom tag type 1979 */ 1980 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 1981 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 1982 goto out; 1983 } 1984 1985 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 1986 out: 1987 return dev->tag_protocol; 1988 } 1989 EXPORT_SYMBOL(b53_get_tag_protocol); 1990 1991 int b53_mirror_add(struct dsa_switch *ds, int port, 1992 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1993 { 1994 struct b53_device *dev = ds->priv; 1995 u16 reg, loc; 1996 1997 if (ingress) 1998 loc = B53_IG_MIR_CTL; 1999 else 2000 loc = B53_EG_MIR_CTL; 2001 2002 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2003 reg |= BIT(port); 2004 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2005 2006 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2007 reg &= ~CAP_PORT_MASK; 2008 reg |= mirror->to_local_port; 2009 reg |= MIRROR_EN; 2010 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2011 2012 return 0; 2013 } 2014 EXPORT_SYMBOL(b53_mirror_add); 2015 2016 void b53_mirror_del(struct dsa_switch *ds, int port, 2017 struct dsa_mall_mirror_tc_entry *mirror) 2018 { 2019 struct b53_device *dev = ds->priv; 2020 bool loc_disable = false, other_loc_disable = false; 2021 u16 reg, loc; 2022 2023 if (mirror->ingress) 2024 loc = B53_IG_MIR_CTL; 2025 else 2026 loc = B53_EG_MIR_CTL; 2027 2028 /* Update the desired ingress/egress register */ 2029 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2030 reg &= ~BIT(port); 2031 if (!(reg & MIRROR_MASK)) 2032 loc_disable = true; 2033 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2034 2035 /* Now look at the other one to know if we can disable mirroring 2036 * entirely 2037 */ 2038 if (mirror->ingress) 2039 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2040 else 2041 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2042 if (!(reg & MIRROR_MASK)) 2043 other_loc_disable = true; 2044 2045 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2046 /* Both no longer have ports, let's disable mirroring */ 2047 if (loc_disable && other_loc_disable) { 2048 reg &= ~MIRROR_EN; 2049 reg &= ~mirror->to_local_port; 2050 } 2051 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2052 } 2053 EXPORT_SYMBOL(b53_mirror_del); 2054 2055 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2056 { 2057 struct b53_device *dev = ds->priv; 2058 u16 reg; 2059 2060 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2061 if (enable) 2062 reg |= BIT(port); 2063 else 2064 reg &= ~BIT(port); 2065 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2066 } 2067 EXPORT_SYMBOL(b53_eee_enable_set); 2068 2069 2070 /* Returns 0 if EEE was not enabled, or 1 otherwise 2071 */ 2072 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2073 { 2074 int ret; 2075 2076 ret = phy_init_eee(phy, 0); 2077 if (ret) 2078 return 0; 2079 2080 b53_eee_enable_set(ds, port, true); 2081 2082 return 1; 2083 } 2084 EXPORT_SYMBOL(b53_eee_init); 2085 2086 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2087 { 2088 struct b53_device *dev = ds->priv; 2089 struct ethtool_eee *p = &dev->ports[port].eee; 2090 u16 reg; 2091 2092 if (is5325(dev) || is5365(dev)) 2093 return -EOPNOTSUPP; 2094 2095 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2096 e->eee_enabled = p->eee_enabled; 2097 e->eee_active = !!(reg & BIT(port)); 2098 2099 return 0; 2100 } 2101 EXPORT_SYMBOL(b53_get_mac_eee); 2102 2103 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2104 { 2105 struct b53_device *dev = ds->priv; 2106 struct ethtool_eee *p = &dev->ports[port].eee; 2107 2108 if (is5325(dev) || is5365(dev)) 2109 return -EOPNOTSUPP; 2110 2111 p->eee_enabled = e->eee_enabled; 2112 b53_eee_enable_set(ds, port, e->eee_enabled); 2113 2114 return 0; 2115 } 2116 EXPORT_SYMBOL(b53_set_mac_eee); 2117 2118 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2119 { 2120 struct b53_device *dev = ds->priv; 2121 bool enable_jumbo; 2122 bool allow_10_100; 2123 2124 if (is5325(dev) || is5365(dev)) 2125 return -EOPNOTSUPP; 2126 2127 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2128 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2129 2130 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2131 } 2132 2133 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2134 { 2135 return JMS_MAX_SIZE; 2136 } 2137 2138 static const struct dsa_switch_ops b53_switch_ops = { 2139 .get_tag_protocol = b53_get_tag_protocol, 2140 .setup = b53_setup, 2141 .get_strings = b53_get_strings, 2142 .get_ethtool_stats = b53_get_ethtool_stats, 2143 .get_sset_count = b53_get_sset_count, 2144 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2145 .phy_read = b53_phy_read16, 2146 .phy_write = b53_phy_write16, 2147 .adjust_link = b53_adjust_link, 2148 .phylink_validate = b53_phylink_validate, 2149 .phylink_mac_link_state = b53_phylink_mac_link_state, 2150 .phylink_mac_config = b53_phylink_mac_config, 2151 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2152 .phylink_mac_link_down = b53_phylink_mac_link_down, 2153 .phylink_mac_link_up = b53_phylink_mac_link_up, 2154 .port_enable = b53_enable_port, 2155 .port_disable = b53_disable_port, 2156 .get_mac_eee = b53_get_mac_eee, 2157 .set_mac_eee = b53_set_mac_eee, 2158 .port_bridge_join = b53_br_join, 2159 .port_bridge_leave = b53_br_leave, 2160 .port_stp_state_set = b53_br_set_stp_state, 2161 .port_fast_age = b53_br_fast_age, 2162 .port_egress_floods = b53_br_egress_floods, 2163 .port_vlan_filtering = b53_vlan_filtering, 2164 .port_vlan_prepare = b53_vlan_prepare, 2165 .port_vlan_add = b53_vlan_add, 2166 .port_vlan_del = b53_vlan_del, 2167 .port_fdb_dump = b53_fdb_dump, 2168 .port_fdb_add = b53_fdb_add, 2169 .port_fdb_del = b53_fdb_del, 2170 .port_mirror_add = b53_mirror_add, 2171 .port_mirror_del = b53_mirror_del, 2172 .port_mdb_prepare = b53_mdb_prepare, 2173 .port_mdb_add = b53_mdb_add, 2174 .port_mdb_del = b53_mdb_del, 2175 .port_max_mtu = b53_get_max_mtu, 2176 .port_change_mtu = b53_change_mtu, 2177 }; 2178 2179 struct b53_chip_data { 2180 u32 chip_id; 2181 const char *dev_name; 2182 u16 vlans; 2183 u16 enabled_ports; 2184 u8 cpu_port; 2185 u8 vta_regs[3]; 2186 u8 arl_bins; 2187 u16 arl_buckets; 2188 u8 duplex_reg; 2189 u8 jumbo_pm_reg; 2190 u8 jumbo_size_reg; 2191 }; 2192 2193 #define B53_VTA_REGS \ 2194 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2195 #define B53_VTA_REGS_9798 \ 2196 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2197 #define B53_VTA_REGS_63XX \ 2198 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2199 2200 static const struct b53_chip_data b53_switch_chips[] = { 2201 { 2202 .chip_id = BCM5325_DEVICE_ID, 2203 .dev_name = "BCM5325", 2204 .vlans = 16, 2205 .enabled_ports = 0x1f, 2206 .arl_bins = 2, 2207 .arl_buckets = 1024, 2208 .cpu_port = B53_CPU_PORT_25, 2209 .duplex_reg = B53_DUPLEX_STAT_FE, 2210 }, 2211 { 2212 .chip_id = BCM5365_DEVICE_ID, 2213 .dev_name = "BCM5365", 2214 .vlans = 256, 2215 .enabled_ports = 0x1f, 2216 .arl_bins = 2, 2217 .arl_buckets = 1024, 2218 .cpu_port = B53_CPU_PORT_25, 2219 .duplex_reg = B53_DUPLEX_STAT_FE, 2220 }, 2221 { 2222 .chip_id = BCM5389_DEVICE_ID, 2223 .dev_name = "BCM5389", 2224 .vlans = 4096, 2225 .enabled_ports = 0x1f, 2226 .arl_bins = 4, 2227 .arl_buckets = 1024, 2228 .cpu_port = B53_CPU_PORT, 2229 .vta_regs = B53_VTA_REGS, 2230 .duplex_reg = B53_DUPLEX_STAT_GE, 2231 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2232 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2233 }, 2234 { 2235 .chip_id = BCM5395_DEVICE_ID, 2236 .dev_name = "BCM5395", 2237 .vlans = 4096, 2238 .enabled_ports = 0x1f, 2239 .arl_bins = 4, 2240 .arl_buckets = 1024, 2241 .cpu_port = B53_CPU_PORT, 2242 .vta_regs = B53_VTA_REGS, 2243 .duplex_reg = B53_DUPLEX_STAT_GE, 2244 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2245 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2246 }, 2247 { 2248 .chip_id = BCM5397_DEVICE_ID, 2249 .dev_name = "BCM5397", 2250 .vlans = 4096, 2251 .enabled_ports = 0x1f, 2252 .arl_bins = 4, 2253 .arl_buckets = 1024, 2254 .cpu_port = B53_CPU_PORT, 2255 .vta_regs = B53_VTA_REGS_9798, 2256 .duplex_reg = B53_DUPLEX_STAT_GE, 2257 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2258 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2259 }, 2260 { 2261 .chip_id = BCM5398_DEVICE_ID, 2262 .dev_name = "BCM5398", 2263 .vlans = 4096, 2264 .enabled_ports = 0x7f, 2265 .arl_bins = 4, 2266 .arl_buckets = 1024, 2267 .cpu_port = B53_CPU_PORT, 2268 .vta_regs = B53_VTA_REGS_9798, 2269 .duplex_reg = B53_DUPLEX_STAT_GE, 2270 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2271 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2272 }, 2273 { 2274 .chip_id = BCM53115_DEVICE_ID, 2275 .dev_name = "BCM53115", 2276 .vlans = 4096, 2277 .enabled_ports = 0x1f, 2278 .arl_bins = 4, 2279 .arl_buckets = 1024, 2280 .vta_regs = B53_VTA_REGS, 2281 .cpu_port = B53_CPU_PORT, 2282 .duplex_reg = B53_DUPLEX_STAT_GE, 2283 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2284 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2285 }, 2286 { 2287 .chip_id = BCM53125_DEVICE_ID, 2288 .dev_name = "BCM53125", 2289 .vlans = 4096, 2290 .enabled_ports = 0xff, 2291 .arl_bins = 4, 2292 .arl_buckets = 1024, 2293 .cpu_port = B53_CPU_PORT, 2294 .vta_regs = B53_VTA_REGS, 2295 .duplex_reg = B53_DUPLEX_STAT_GE, 2296 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2297 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2298 }, 2299 { 2300 .chip_id = BCM53128_DEVICE_ID, 2301 .dev_name = "BCM53128", 2302 .vlans = 4096, 2303 .enabled_ports = 0x1ff, 2304 .arl_bins = 4, 2305 .arl_buckets = 1024, 2306 .cpu_port = B53_CPU_PORT, 2307 .vta_regs = B53_VTA_REGS, 2308 .duplex_reg = B53_DUPLEX_STAT_GE, 2309 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2310 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2311 }, 2312 { 2313 .chip_id = BCM63XX_DEVICE_ID, 2314 .dev_name = "BCM63xx", 2315 .vlans = 4096, 2316 .enabled_ports = 0, /* pdata must provide them */ 2317 .arl_bins = 4, 2318 .arl_buckets = 1024, 2319 .cpu_port = B53_CPU_PORT, 2320 .vta_regs = B53_VTA_REGS_63XX, 2321 .duplex_reg = B53_DUPLEX_STAT_63XX, 2322 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2323 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2324 }, 2325 { 2326 .chip_id = BCM53010_DEVICE_ID, 2327 .dev_name = "BCM53010", 2328 .vlans = 4096, 2329 .enabled_ports = 0x1f, 2330 .arl_bins = 4, 2331 .arl_buckets = 1024, 2332 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2333 .vta_regs = B53_VTA_REGS, 2334 .duplex_reg = B53_DUPLEX_STAT_GE, 2335 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2336 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2337 }, 2338 { 2339 .chip_id = BCM53011_DEVICE_ID, 2340 .dev_name = "BCM53011", 2341 .vlans = 4096, 2342 .enabled_ports = 0x1bf, 2343 .arl_bins = 4, 2344 .arl_buckets = 1024, 2345 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2346 .vta_regs = B53_VTA_REGS, 2347 .duplex_reg = B53_DUPLEX_STAT_GE, 2348 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2349 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2350 }, 2351 { 2352 .chip_id = BCM53012_DEVICE_ID, 2353 .dev_name = "BCM53012", 2354 .vlans = 4096, 2355 .enabled_ports = 0x1bf, 2356 .arl_bins = 4, 2357 .arl_buckets = 1024, 2358 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2359 .vta_regs = B53_VTA_REGS, 2360 .duplex_reg = B53_DUPLEX_STAT_GE, 2361 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2362 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2363 }, 2364 { 2365 .chip_id = BCM53018_DEVICE_ID, 2366 .dev_name = "BCM53018", 2367 .vlans = 4096, 2368 .enabled_ports = 0x1f, 2369 .arl_bins = 4, 2370 .arl_buckets = 1024, 2371 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2372 .vta_regs = B53_VTA_REGS, 2373 .duplex_reg = B53_DUPLEX_STAT_GE, 2374 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2375 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2376 }, 2377 { 2378 .chip_id = BCM53019_DEVICE_ID, 2379 .dev_name = "BCM53019", 2380 .vlans = 4096, 2381 .enabled_ports = 0x1f, 2382 .arl_bins = 4, 2383 .arl_buckets = 1024, 2384 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2385 .vta_regs = B53_VTA_REGS, 2386 .duplex_reg = B53_DUPLEX_STAT_GE, 2387 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2388 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2389 }, 2390 { 2391 .chip_id = BCM58XX_DEVICE_ID, 2392 .dev_name = "BCM585xx/586xx/88312", 2393 .vlans = 4096, 2394 .enabled_ports = 0x1ff, 2395 .arl_bins = 4, 2396 .arl_buckets = 1024, 2397 .cpu_port = B53_CPU_PORT, 2398 .vta_regs = B53_VTA_REGS, 2399 .duplex_reg = B53_DUPLEX_STAT_GE, 2400 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2401 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2402 }, 2403 { 2404 .chip_id = BCM583XX_DEVICE_ID, 2405 .dev_name = "BCM583xx/11360", 2406 .vlans = 4096, 2407 .enabled_ports = 0x103, 2408 .arl_bins = 4, 2409 .arl_buckets = 1024, 2410 .cpu_port = B53_CPU_PORT, 2411 .vta_regs = B53_VTA_REGS, 2412 .duplex_reg = B53_DUPLEX_STAT_GE, 2413 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2414 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2415 }, 2416 { 2417 .chip_id = BCM7445_DEVICE_ID, 2418 .dev_name = "BCM7445", 2419 .vlans = 4096, 2420 .enabled_ports = 0x1ff, 2421 .arl_bins = 4, 2422 .arl_buckets = 1024, 2423 .cpu_port = B53_CPU_PORT, 2424 .vta_regs = B53_VTA_REGS, 2425 .duplex_reg = B53_DUPLEX_STAT_GE, 2426 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2427 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2428 }, 2429 { 2430 .chip_id = BCM7278_DEVICE_ID, 2431 .dev_name = "BCM7278", 2432 .vlans = 4096, 2433 .enabled_ports = 0x1ff, 2434 .arl_bins = 4, 2435 .arl_buckets = 256, 2436 .cpu_port = B53_CPU_PORT, 2437 .vta_regs = B53_VTA_REGS, 2438 .duplex_reg = B53_DUPLEX_STAT_GE, 2439 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2440 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2441 }, 2442 }; 2443 2444 static int b53_switch_init(struct b53_device *dev) 2445 { 2446 unsigned int i; 2447 int ret; 2448 2449 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2450 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2451 2452 if (chip->chip_id == dev->chip_id) { 2453 if (!dev->enabled_ports) 2454 dev->enabled_ports = chip->enabled_ports; 2455 dev->name = chip->dev_name; 2456 dev->duplex_reg = chip->duplex_reg; 2457 dev->vta_regs[0] = chip->vta_regs[0]; 2458 dev->vta_regs[1] = chip->vta_regs[1]; 2459 dev->vta_regs[2] = chip->vta_regs[2]; 2460 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2461 dev->cpu_port = chip->cpu_port; 2462 dev->num_vlans = chip->vlans; 2463 dev->num_arl_bins = chip->arl_bins; 2464 dev->num_arl_buckets = chip->arl_buckets; 2465 break; 2466 } 2467 } 2468 2469 /* check which BCM5325x version we have */ 2470 if (is5325(dev)) { 2471 u8 vc4; 2472 2473 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2474 2475 /* check reserved bits */ 2476 switch (vc4 & 3) { 2477 case 1: 2478 /* BCM5325E */ 2479 break; 2480 case 3: 2481 /* BCM5325F - do not use port 4 */ 2482 dev->enabled_ports &= ~BIT(4); 2483 break; 2484 default: 2485 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2486 #ifndef CONFIG_BCM47XX 2487 /* BCM5325M */ 2488 return -EINVAL; 2489 #else 2490 break; 2491 #endif 2492 } 2493 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2494 u64 strap_value; 2495 2496 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2497 /* use second IMP port if GMII is enabled */ 2498 if (strap_value & SV_GMII_CTRL_115) 2499 dev->cpu_port = 5; 2500 } 2501 2502 /* cpu port is always last */ 2503 dev->num_ports = dev->cpu_port + 1; 2504 dev->enabled_ports |= BIT(dev->cpu_port); 2505 2506 /* Include non standard CPU port built-in PHYs to be probed */ 2507 if (is539x(dev) || is531x5(dev)) { 2508 for (i = 0; i < dev->num_ports; i++) { 2509 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2510 !b53_possible_cpu_port(dev->ds, i)) 2511 dev->ds->phys_mii_mask |= BIT(i); 2512 } 2513 } 2514 2515 dev->ports = devm_kcalloc(dev->dev, 2516 dev->num_ports, sizeof(struct b53_port), 2517 GFP_KERNEL); 2518 if (!dev->ports) 2519 return -ENOMEM; 2520 2521 dev->vlans = devm_kcalloc(dev->dev, 2522 dev->num_vlans, sizeof(struct b53_vlan), 2523 GFP_KERNEL); 2524 if (!dev->vlans) 2525 return -ENOMEM; 2526 2527 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2528 if (dev->reset_gpio >= 0) { 2529 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2530 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2531 if (ret) 2532 return ret; 2533 } 2534 2535 return 0; 2536 } 2537 2538 struct b53_device *b53_switch_alloc(struct device *base, 2539 const struct b53_io_ops *ops, 2540 void *priv) 2541 { 2542 struct dsa_switch *ds; 2543 struct b53_device *dev; 2544 2545 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2546 if (!ds) 2547 return NULL; 2548 2549 ds->dev = base; 2550 ds->num_ports = DSA_MAX_PORTS; 2551 2552 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2553 if (!dev) 2554 return NULL; 2555 2556 ds->priv = dev; 2557 dev->dev = base; 2558 2559 dev->ds = ds; 2560 dev->priv = priv; 2561 dev->ops = ops; 2562 ds->ops = &b53_switch_ops; 2563 mutex_init(&dev->reg_mutex); 2564 mutex_init(&dev->stats_mutex); 2565 2566 return dev; 2567 } 2568 EXPORT_SYMBOL(b53_switch_alloc); 2569 2570 int b53_switch_detect(struct b53_device *dev) 2571 { 2572 u32 id32; 2573 u16 tmp; 2574 u8 id8; 2575 int ret; 2576 2577 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2578 if (ret) 2579 return ret; 2580 2581 switch (id8) { 2582 case 0: 2583 /* BCM5325 and BCM5365 do not have this register so reads 2584 * return 0. But the read operation did succeed, so assume this 2585 * is one of them. 2586 * 2587 * Next check if we can write to the 5325's VTA register; for 2588 * 5365 it is read only. 2589 */ 2590 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2591 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2592 2593 if (tmp == 0xf) 2594 dev->chip_id = BCM5325_DEVICE_ID; 2595 else 2596 dev->chip_id = BCM5365_DEVICE_ID; 2597 break; 2598 case BCM5389_DEVICE_ID: 2599 case BCM5395_DEVICE_ID: 2600 case BCM5397_DEVICE_ID: 2601 case BCM5398_DEVICE_ID: 2602 dev->chip_id = id8; 2603 break; 2604 default: 2605 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2606 if (ret) 2607 return ret; 2608 2609 switch (id32) { 2610 case BCM53115_DEVICE_ID: 2611 case BCM53125_DEVICE_ID: 2612 case BCM53128_DEVICE_ID: 2613 case BCM53010_DEVICE_ID: 2614 case BCM53011_DEVICE_ID: 2615 case BCM53012_DEVICE_ID: 2616 case BCM53018_DEVICE_ID: 2617 case BCM53019_DEVICE_ID: 2618 dev->chip_id = id32; 2619 break; 2620 default: 2621 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2622 id8, id32); 2623 return -ENODEV; 2624 } 2625 } 2626 2627 if (dev->chip_id == BCM5325_DEVICE_ID) 2628 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2629 &dev->core_rev); 2630 else 2631 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2632 &dev->core_rev); 2633 } 2634 EXPORT_SYMBOL(b53_switch_detect); 2635 2636 int b53_switch_register(struct b53_device *dev) 2637 { 2638 int ret; 2639 2640 if (dev->pdata) { 2641 dev->chip_id = dev->pdata->chip_id; 2642 dev->enabled_ports = dev->pdata->enabled_ports; 2643 } 2644 2645 if (!dev->chip_id && b53_switch_detect(dev)) 2646 return -EINVAL; 2647 2648 ret = b53_switch_init(dev); 2649 if (ret) 2650 return ret; 2651 2652 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2653 2654 return dsa_register_switch(dev->ds); 2655 } 2656 EXPORT_SYMBOL(b53_switch_register); 2657 2658 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2659 MODULE_DESCRIPTION("B53 switch library"); 2660 MODULE_LICENSE("Dual BSD/GPL"); 2661