1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/platform_device.h> 25 #include <linux/scatterlist.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 29 #define I2C_RS_TRANSFER (1 << 4) 30 #define I2C_ARB_LOST (1 << 3) 31 #define I2C_HS_NACKERR (1 << 2) 32 #define I2C_ACKERR (1 << 1) 33 #define I2C_TRANSAC_COMP (1 << 0) 34 #define I2C_TRANSAC_START (1 << 0) 35 #define I2C_RS_MUL_CNFG (1 << 15) 36 #define I2C_RS_MUL_TRIG (1 << 14) 37 #define I2C_DCM_DISABLE 0x0000 38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40 #define I2C_SOFT_RST 0x0001 41 #define I2C_FIFO_ADDR_CLR 0x0001 42 #define I2C_DELAY_LEN 0x0002 43 #define I2C_ST_START_CON 0x8001 44 #define I2C_FS_START_CON 0x1800 45 #define I2C_TIME_CLR_VALUE 0x0000 46 #define I2C_TIME_DEFAULT_VALUE 0x0003 47 #define I2C_WRRD_TRANAC_VALUE 0x0002 48 #define I2C_RD_TRANAC_VALUE 0x0001 49 50 #define I2C_DMA_CON_TX 0x0000 51 #define I2C_DMA_CON_RX 0x0001 52 #define I2C_DMA_START_EN 0x0001 53 #define I2C_DMA_INT_FLAG_NONE 0x0000 54 #define I2C_DMA_CLR_FLAG 0x0000 55 #define I2C_DMA_HARD_RST 0x0002 56 #define I2C_DMA_4G_MODE 0x0001 57 58 #define I2C_DEFAULT_CLK_DIV 5 59 #define MAX_SAMPLE_CNT_DIV 8 60 #define MAX_STEP_CNT_DIV 64 61 #define MAX_HS_STEP_CNT_DIV 8 62 63 #define I2C_CONTROL_RS (0x1 << 1) 64 #define I2C_CONTROL_DMA_EN (0x1 << 2) 65 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 66 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 67 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 68 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 69 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 70 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 71 #define I2C_CONTROL_WRAPPER (0x1 << 0) 72 73 #define I2C_DRV_NAME "i2c-mt65xx" 74 75 enum DMA_REGS_OFFSET { 76 OFFSET_INT_FLAG = 0x0, 77 OFFSET_INT_EN = 0x04, 78 OFFSET_EN = 0x08, 79 OFFSET_RST = 0x0c, 80 OFFSET_CON = 0x18, 81 OFFSET_TX_MEM_ADDR = 0x1c, 82 OFFSET_RX_MEM_ADDR = 0x20, 83 OFFSET_TX_LEN = 0x24, 84 OFFSET_RX_LEN = 0x28, 85 OFFSET_TX_4G_MODE = 0x54, 86 OFFSET_RX_4G_MODE = 0x58, 87 }; 88 89 enum i2c_trans_st_rs { 90 I2C_TRANS_STOP = 0, 91 I2C_TRANS_REPEATED_START, 92 }; 93 94 enum mtk_trans_op { 95 I2C_MASTER_WR = 1, 96 I2C_MASTER_RD, 97 I2C_MASTER_WRRD, 98 }; 99 100 enum I2C_REGS_OFFSET { 101 OFFSET_DATA_PORT, 102 OFFSET_SLAVE_ADDR, 103 OFFSET_INTR_MASK, 104 OFFSET_INTR_STAT, 105 OFFSET_CONTROL, 106 OFFSET_TRANSFER_LEN, 107 OFFSET_TRANSAC_LEN, 108 OFFSET_DELAY_LEN, 109 OFFSET_TIMING, 110 OFFSET_START, 111 OFFSET_EXT_CONF, 112 OFFSET_FIFO_STAT, 113 OFFSET_FIFO_THRESH, 114 OFFSET_FIFO_ADDR_CLR, 115 OFFSET_IO_CONFIG, 116 OFFSET_RSV_DEBUG, 117 OFFSET_HS, 118 OFFSET_SOFTRESET, 119 OFFSET_DCM_EN, 120 OFFSET_PATH_DIR, 121 OFFSET_DEBUGSTAT, 122 OFFSET_DEBUGCTRL, 123 OFFSET_TRANSFER_LEN_AUX, 124 OFFSET_CLOCK_DIV, 125 OFFSET_LTIMING, 126 }; 127 128 static const u16 mt_i2c_regs_v1[] = { 129 [OFFSET_DATA_PORT] = 0x0, 130 [OFFSET_SLAVE_ADDR] = 0x4, 131 [OFFSET_INTR_MASK] = 0x8, 132 [OFFSET_INTR_STAT] = 0xc, 133 [OFFSET_CONTROL] = 0x10, 134 [OFFSET_TRANSFER_LEN] = 0x14, 135 [OFFSET_TRANSAC_LEN] = 0x18, 136 [OFFSET_DELAY_LEN] = 0x1c, 137 [OFFSET_TIMING] = 0x20, 138 [OFFSET_START] = 0x24, 139 [OFFSET_EXT_CONF] = 0x28, 140 [OFFSET_FIFO_STAT] = 0x30, 141 [OFFSET_FIFO_THRESH] = 0x34, 142 [OFFSET_FIFO_ADDR_CLR] = 0x38, 143 [OFFSET_IO_CONFIG] = 0x40, 144 [OFFSET_RSV_DEBUG] = 0x44, 145 [OFFSET_HS] = 0x48, 146 [OFFSET_SOFTRESET] = 0x50, 147 [OFFSET_DCM_EN] = 0x54, 148 [OFFSET_PATH_DIR] = 0x60, 149 [OFFSET_DEBUGSTAT] = 0x64, 150 [OFFSET_DEBUGCTRL] = 0x68, 151 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 152 [OFFSET_CLOCK_DIV] = 0x70, 153 }; 154 155 static const u16 mt_i2c_regs_v2[] = { 156 [OFFSET_DATA_PORT] = 0x0, 157 [OFFSET_SLAVE_ADDR] = 0x4, 158 [OFFSET_INTR_MASK] = 0x8, 159 [OFFSET_INTR_STAT] = 0xc, 160 [OFFSET_CONTROL] = 0x10, 161 [OFFSET_TRANSFER_LEN] = 0x14, 162 [OFFSET_TRANSAC_LEN] = 0x18, 163 [OFFSET_DELAY_LEN] = 0x1c, 164 [OFFSET_TIMING] = 0x20, 165 [OFFSET_START] = 0x24, 166 [OFFSET_EXT_CONF] = 0x28, 167 [OFFSET_LTIMING] = 0x2c, 168 [OFFSET_HS] = 0x30, 169 [OFFSET_IO_CONFIG] = 0x34, 170 [OFFSET_FIFO_ADDR_CLR] = 0x38, 171 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 172 [OFFSET_CLOCK_DIV] = 0x48, 173 [OFFSET_SOFTRESET] = 0x50, 174 [OFFSET_DEBUGSTAT] = 0xe0, 175 [OFFSET_DEBUGCTRL] = 0xe8, 176 [OFFSET_FIFO_STAT] = 0xf4, 177 [OFFSET_FIFO_THRESH] = 0xf8, 178 [OFFSET_DCM_EN] = 0xf88, 179 }; 180 181 struct mtk_i2c_compatible { 182 const struct i2c_adapter_quirks *quirks; 183 const u16 *regs; 184 unsigned char pmic_i2c: 1; 185 unsigned char dcm: 1; 186 unsigned char auto_restart: 1; 187 unsigned char aux_len_reg: 1; 188 unsigned char support_33bits: 1; 189 unsigned char timing_adjust: 1; 190 unsigned char dma_sync: 1; 191 unsigned char ltiming_adjust: 1; 192 }; 193 194 struct mtk_i2c { 195 struct i2c_adapter adap; /* i2c host adapter */ 196 struct device *dev; 197 struct completion msg_complete; 198 199 /* set in i2c probe */ 200 void __iomem *base; /* i2c base addr */ 201 void __iomem *pdmabase; /* dma base address*/ 202 struct clk *clk_main; /* main clock for i2c bus */ 203 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 204 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 205 struct clk *clk_arb; /* Arbitrator clock for i2c */ 206 bool have_pmic; /* can use i2c pins from PMIC */ 207 bool use_push_pull; /* IO config push-pull mode */ 208 209 u16 irq_stat; /* interrupt status */ 210 unsigned int clk_src_div; 211 unsigned int speed_hz; /* The speed in transfer */ 212 enum mtk_trans_op op; 213 u16 timing_reg; 214 u16 high_speed_reg; 215 u16 ltiming_reg; 216 unsigned char auto_restart; 217 bool ignore_restart_irq; 218 const struct mtk_i2c_compatible *dev_comp; 219 }; 220 221 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 222 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 223 .max_num_msgs = 1, 224 .max_write_len = 255, 225 .max_read_len = 255, 226 .max_comb_1st_msg_len = 255, 227 .max_comb_2nd_msg_len = 31, 228 }; 229 230 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 231 .max_num_msgs = 255, 232 }; 233 234 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 235 .flags = I2C_AQ_NO_ZERO_LEN, 236 }; 237 238 static const struct mtk_i2c_compatible mt2712_compat = { 239 .regs = mt_i2c_regs_v1, 240 .pmic_i2c = 0, 241 .dcm = 1, 242 .auto_restart = 1, 243 .aux_len_reg = 1, 244 .support_33bits = 1, 245 .timing_adjust = 1, 246 .dma_sync = 0, 247 .ltiming_adjust = 0, 248 }; 249 250 static const struct mtk_i2c_compatible mt6577_compat = { 251 .quirks = &mt6577_i2c_quirks, 252 .regs = mt_i2c_regs_v1, 253 .pmic_i2c = 0, 254 .dcm = 1, 255 .auto_restart = 0, 256 .aux_len_reg = 0, 257 .support_33bits = 0, 258 .timing_adjust = 0, 259 .dma_sync = 0, 260 .ltiming_adjust = 0, 261 }; 262 263 static const struct mtk_i2c_compatible mt6589_compat = { 264 .quirks = &mt6577_i2c_quirks, 265 .regs = mt_i2c_regs_v1, 266 .pmic_i2c = 1, 267 .dcm = 0, 268 .auto_restart = 0, 269 .aux_len_reg = 0, 270 .support_33bits = 0, 271 .timing_adjust = 0, 272 .dma_sync = 0, 273 .ltiming_adjust = 0, 274 }; 275 276 static const struct mtk_i2c_compatible mt7622_compat = { 277 .quirks = &mt7622_i2c_quirks, 278 .regs = mt_i2c_regs_v1, 279 .pmic_i2c = 0, 280 .dcm = 1, 281 .auto_restart = 1, 282 .aux_len_reg = 1, 283 .support_33bits = 0, 284 .timing_adjust = 0, 285 .dma_sync = 0, 286 .ltiming_adjust = 0, 287 }; 288 289 static const struct mtk_i2c_compatible mt8173_compat = { 290 .regs = mt_i2c_regs_v1, 291 .pmic_i2c = 0, 292 .dcm = 1, 293 .auto_restart = 1, 294 .aux_len_reg = 1, 295 .support_33bits = 1, 296 .timing_adjust = 0, 297 .dma_sync = 0, 298 .ltiming_adjust = 0, 299 }; 300 301 static const struct mtk_i2c_compatible mt8183_compat = { 302 .quirks = &mt8183_i2c_quirks, 303 .regs = mt_i2c_regs_v2, 304 .pmic_i2c = 0, 305 .dcm = 0, 306 .auto_restart = 1, 307 .aux_len_reg = 1, 308 .support_33bits = 1, 309 .timing_adjust = 1, 310 .dma_sync = 1, 311 .ltiming_adjust = 1, 312 }; 313 314 static const struct of_device_id mtk_i2c_of_match[] = { 315 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 316 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 317 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 318 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 319 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 320 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 321 {} 322 }; 323 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 324 325 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 326 { 327 return readw(i2c->base + i2c->dev_comp->regs[reg]); 328 } 329 330 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 331 enum I2C_REGS_OFFSET reg) 332 { 333 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 334 } 335 336 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 337 { 338 int ret; 339 340 ret = clk_prepare_enable(i2c->clk_dma); 341 if (ret) 342 return ret; 343 344 ret = clk_prepare_enable(i2c->clk_main); 345 if (ret) 346 goto err_main; 347 348 if (i2c->have_pmic) { 349 ret = clk_prepare_enable(i2c->clk_pmic); 350 if (ret) 351 goto err_pmic; 352 } 353 354 if (i2c->clk_arb) { 355 ret = clk_prepare_enable(i2c->clk_arb); 356 if (ret) 357 goto err_arb; 358 } 359 360 return 0; 361 362 err_arb: 363 if (i2c->have_pmic) 364 clk_disable_unprepare(i2c->clk_pmic); 365 err_pmic: 366 clk_disable_unprepare(i2c->clk_main); 367 err_main: 368 clk_disable_unprepare(i2c->clk_dma); 369 370 return ret; 371 } 372 373 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 374 { 375 if (i2c->clk_arb) 376 clk_disable_unprepare(i2c->clk_arb); 377 378 if (i2c->have_pmic) 379 clk_disable_unprepare(i2c->clk_pmic); 380 381 clk_disable_unprepare(i2c->clk_main); 382 clk_disable_unprepare(i2c->clk_dma); 383 } 384 385 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 386 { 387 u16 control_reg; 388 389 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 390 391 /* Set ioconfig */ 392 if (i2c->use_push_pull) 393 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 394 else 395 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 396 397 if (i2c->dev_comp->dcm) 398 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 399 400 if (i2c->dev_comp->timing_adjust) 401 mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV); 402 403 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 404 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 405 if (i2c->dev_comp->ltiming_adjust) 406 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 407 408 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 409 if (i2c->have_pmic) 410 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 411 412 control_reg = I2C_CONTROL_ACKERR_DET_EN | 413 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 414 if (i2c->dev_comp->dma_sync) 415 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 416 417 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 418 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 419 420 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 421 udelay(50); 422 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 423 } 424 425 /* 426 * Calculate i2c port speed 427 * 428 * Hardware design: 429 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 430 * clock_div: fixed in hardware, but may be various in different SoCs 431 * 432 * The calculation want to pick the highest bus frequency that is still 433 * less than or equal to i2c->speed_hz. The calculation try to get 434 * sample_cnt and step_cn 435 */ 436 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 437 unsigned int target_speed, 438 unsigned int *timing_step_cnt, 439 unsigned int *timing_sample_cnt) 440 { 441 unsigned int step_cnt; 442 unsigned int sample_cnt; 443 unsigned int max_step_cnt; 444 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 445 unsigned int base_step_cnt; 446 unsigned int opt_div; 447 unsigned int best_mul; 448 unsigned int cnt_mul; 449 450 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 451 target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ; 452 453 if (target_speed > I2C_MAX_FAST_MODE_FREQ) 454 max_step_cnt = MAX_HS_STEP_CNT_DIV; 455 else 456 max_step_cnt = MAX_STEP_CNT_DIV; 457 458 base_step_cnt = max_step_cnt; 459 /* Find the best combination */ 460 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 461 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 462 463 /* Search for the best pair (sample_cnt, step_cnt) with 464 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 465 * 0 < step_cnt < max_step_cnt 466 * sample_cnt * step_cnt >= opt_div 467 * optimizing for sample_cnt * step_cnt being minimal 468 */ 469 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 470 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 471 cnt_mul = step_cnt * sample_cnt; 472 if (step_cnt > max_step_cnt) 473 continue; 474 475 if (cnt_mul < best_mul) { 476 best_mul = cnt_mul; 477 base_sample_cnt = sample_cnt; 478 base_step_cnt = step_cnt; 479 if (best_mul == opt_div) 480 break; 481 } 482 } 483 484 sample_cnt = base_sample_cnt; 485 step_cnt = base_step_cnt; 486 487 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 488 /* In this case, hardware can't support such 489 * low i2c_bus_freq 490 */ 491 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 492 return -EINVAL; 493 } 494 495 *timing_step_cnt = step_cnt - 1; 496 *timing_sample_cnt = sample_cnt - 1; 497 498 return 0; 499 } 500 501 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 502 { 503 unsigned int clk_src; 504 unsigned int step_cnt; 505 unsigned int sample_cnt; 506 unsigned int l_step_cnt; 507 unsigned int l_sample_cnt; 508 unsigned int target_speed; 509 int ret; 510 511 clk_src = parent_clk / i2c->clk_src_div; 512 target_speed = i2c->speed_hz; 513 514 if (target_speed > I2C_MAX_FAST_MODE_FREQ) { 515 /* Set master code speed register */ 516 ret = mtk_i2c_calculate_speed(i2c, clk_src, I2C_MAX_FAST_MODE_FREQ, 517 &l_step_cnt, &l_sample_cnt); 518 if (ret < 0) 519 return ret; 520 521 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 522 523 /* Set the high speed mode register */ 524 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 525 &step_cnt, &sample_cnt); 526 if (ret < 0) 527 return ret; 528 529 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 530 (sample_cnt << 12) | (step_cnt << 8); 531 532 if (i2c->dev_comp->ltiming_adjust) 533 i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt | 534 (sample_cnt << 12) | (step_cnt << 9); 535 } else { 536 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 537 &step_cnt, &sample_cnt); 538 if (ret < 0) 539 return ret; 540 541 i2c->timing_reg = (sample_cnt << 8) | step_cnt; 542 543 /* Disable the high speed transaction */ 544 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 545 546 if (i2c->dev_comp->ltiming_adjust) 547 i2c->ltiming_reg = (sample_cnt << 6) | step_cnt; 548 } 549 550 return 0; 551 } 552 553 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr) 554 { 555 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG; 556 } 557 558 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 559 int num, int left_num) 560 { 561 u16 addr_reg; 562 u16 start_reg; 563 u16 control_reg; 564 u16 restart_flag = 0; 565 u32 reg_4g_mode; 566 u8 *dma_rd_buf = NULL; 567 u8 *dma_wr_buf = NULL; 568 dma_addr_t rpaddr = 0; 569 dma_addr_t wpaddr = 0; 570 int ret; 571 572 i2c->irq_stat = 0; 573 574 if (i2c->auto_restart) 575 restart_flag = I2C_RS_TRANSFER; 576 577 reinit_completion(&i2c->msg_complete); 578 579 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 580 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 581 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) || (left_num >= 1)) 582 control_reg |= I2C_CONTROL_RS; 583 584 if (i2c->op == I2C_MASTER_WRRD) 585 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 586 587 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 588 589 /* set start condition */ 590 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) 591 mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF); 592 else 593 mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF); 594 595 addr_reg = i2c_8bit_addr_from_msg(msgs); 596 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 597 598 /* Clear interrupt status */ 599 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 600 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 601 602 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 603 604 /* Enable interrupt */ 605 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 606 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 607 608 /* Set transfer and transaction len */ 609 if (i2c->op == I2C_MASTER_WRRD) { 610 if (i2c->dev_comp->aux_len_reg) { 611 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 612 mtk_i2c_writew(i2c, (msgs + 1)->len, 613 OFFSET_TRANSFER_LEN_AUX); 614 } else { 615 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 616 OFFSET_TRANSFER_LEN); 617 } 618 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 619 } else { 620 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 621 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 622 } 623 624 /* Prepare buffer data to start transfer */ 625 if (i2c->op == I2C_MASTER_RD) { 626 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 627 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON); 628 629 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 630 if (!dma_rd_buf) 631 return -ENOMEM; 632 633 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 634 msgs->len, DMA_FROM_DEVICE); 635 if (dma_mapping_error(i2c->dev, rpaddr)) { 636 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 637 638 return -ENOMEM; 639 } 640 641 if (i2c->dev_comp->support_33bits) { 642 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 643 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 644 } 645 646 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 647 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 648 } else if (i2c->op == I2C_MASTER_WR) { 649 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 650 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); 651 652 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 653 if (!dma_wr_buf) 654 return -ENOMEM; 655 656 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 657 msgs->len, DMA_TO_DEVICE); 658 if (dma_mapping_error(i2c->dev, wpaddr)) { 659 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 660 661 return -ENOMEM; 662 } 663 664 if (i2c->dev_comp->support_33bits) { 665 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 666 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 667 } 668 669 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 670 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 671 } else { 672 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 673 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON); 674 675 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 676 if (!dma_wr_buf) 677 return -ENOMEM; 678 679 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 680 msgs->len, DMA_TO_DEVICE); 681 if (dma_mapping_error(i2c->dev, wpaddr)) { 682 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 683 684 return -ENOMEM; 685 } 686 687 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 688 if (!dma_rd_buf) { 689 dma_unmap_single(i2c->dev, wpaddr, 690 msgs->len, DMA_TO_DEVICE); 691 692 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 693 694 return -ENOMEM; 695 } 696 697 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 698 (msgs + 1)->len, 699 DMA_FROM_DEVICE); 700 if (dma_mapping_error(i2c->dev, rpaddr)) { 701 dma_unmap_single(i2c->dev, wpaddr, 702 msgs->len, DMA_TO_DEVICE); 703 704 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 705 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 706 707 return -ENOMEM; 708 } 709 710 if (i2c->dev_comp->support_33bits) { 711 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 712 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 713 714 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 715 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 716 } 717 718 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 719 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 720 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 721 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 722 } 723 724 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 725 726 if (!i2c->auto_restart) { 727 start_reg = I2C_TRANSAC_START; 728 } else { 729 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 730 if (left_num >= 1) 731 start_reg |= I2C_RS_MUL_CNFG; 732 } 733 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 734 735 ret = wait_for_completion_timeout(&i2c->msg_complete, 736 i2c->adap.timeout); 737 738 /* Clear interrupt mask */ 739 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 740 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 741 742 if (i2c->op == I2C_MASTER_WR) { 743 dma_unmap_single(i2c->dev, wpaddr, 744 msgs->len, DMA_TO_DEVICE); 745 746 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 747 } else if (i2c->op == I2C_MASTER_RD) { 748 dma_unmap_single(i2c->dev, rpaddr, 749 msgs->len, DMA_FROM_DEVICE); 750 751 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 752 } else { 753 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 754 DMA_TO_DEVICE); 755 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 756 DMA_FROM_DEVICE); 757 758 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 759 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 760 } 761 762 if (ret == 0) { 763 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 764 mtk_i2c_init_hw(i2c); 765 return -ETIMEDOUT; 766 } 767 768 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 769 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 770 mtk_i2c_init_hw(i2c); 771 return -ENXIO; 772 } 773 774 return 0; 775 } 776 777 static int mtk_i2c_transfer(struct i2c_adapter *adap, 778 struct i2c_msg msgs[], int num) 779 { 780 int ret; 781 int left_num = num; 782 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 783 784 ret = mtk_i2c_clock_enable(i2c); 785 if (ret) 786 return ret; 787 788 i2c->auto_restart = i2c->dev_comp->auto_restart; 789 790 /* checking if we can skip restart and optimize using WRRD mode */ 791 if (i2c->auto_restart && num == 2) { 792 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 793 msgs[0].addr == msgs[1].addr) { 794 i2c->auto_restart = 0; 795 } 796 } 797 798 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) 799 /* ignore the first restart irq after the master code, 800 * otherwise the first transfer will be discarded. 801 */ 802 i2c->ignore_restart_irq = true; 803 else 804 i2c->ignore_restart_irq = false; 805 806 while (left_num--) { 807 if (!msgs->buf) { 808 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 809 ret = -EINVAL; 810 goto err_exit; 811 } 812 813 if (msgs->flags & I2C_M_RD) 814 i2c->op = I2C_MASTER_RD; 815 else 816 i2c->op = I2C_MASTER_WR; 817 818 if (!i2c->auto_restart) { 819 if (num > 1) { 820 /* combined two messages into one transaction */ 821 i2c->op = I2C_MASTER_WRRD; 822 left_num--; 823 } 824 } 825 826 /* always use DMA mode. */ 827 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 828 if (ret < 0) 829 goto err_exit; 830 831 msgs++; 832 } 833 /* the return value is number of executed messages */ 834 ret = num; 835 836 err_exit: 837 mtk_i2c_clock_disable(i2c); 838 return ret; 839 } 840 841 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 842 { 843 struct mtk_i2c *i2c = dev_id; 844 u16 restart_flag = 0; 845 u16 intr_stat; 846 847 if (i2c->auto_restart) 848 restart_flag = I2C_RS_TRANSFER; 849 850 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 851 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 852 853 /* 854 * when occurs ack error, i2c controller generate two interrupts 855 * first is the ack error interrupt, then the complete interrupt 856 * i2c->irq_stat need keep the two interrupt value. 857 */ 858 i2c->irq_stat |= intr_stat; 859 860 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 861 i2c->ignore_restart_irq = false; 862 i2c->irq_stat = 0; 863 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 864 I2C_TRANSAC_START, OFFSET_START); 865 } else { 866 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 867 complete(&i2c->msg_complete); 868 } 869 870 return IRQ_HANDLED; 871 } 872 873 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 874 { 875 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 876 return I2C_FUNC_I2C | 877 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 878 else 879 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 880 } 881 882 static const struct i2c_algorithm mtk_i2c_algorithm = { 883 .master_xfer = mtk_i2c_transfer, 884 .functionality = mtk_i2c_functionality, 885 }; 886 887 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 888 { 889 int ret; 890 891 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 892 if (ret < 0) 893 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 894 895 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 896 if (ret < 0) 897 return ret; 898 899 if (i2c->clk_src_div == 0) 900 return -EINVAL; 901 902 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 903 i2c->use_push_pull = 904 of_property_read_bool(np, "mediatek,use-push-pull"); 905 906 return 0; 907 } 908 909 static int mtk_i2c_probe(struct platform_device *pdev) 910 { 911 int ret = 0; 912 struct mtk_i2c *i2c; 913 struct clk *clk; 914 struct resource *res; 915 int irq; 916 917 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 918 if (!i2c) 919 return -ENOMEM; 920 921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 922 i2c->base = devm_ioremap_resource(&pdev->dev, res); 923 if (IS_ERR(i2c->base)) 924 return PTR_ERR(i2c->base); 925 926 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 927 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 928 if (IS_ERR(i2c->pdmabase)) 929 return PTR_ERR(i2c->pdmabase); 930 931 irq = platform_get_irq(pdev, 0); 932 if (irq <= 0) 933 return irq; 934 935 init_completion(&i2c->msg_complete); 936 937 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 938 i2c->adap.dev.of_node = pdev->dev.of_node; 939 i2c->dev = &pdev->dev; 940 i2c->adap.dev.parent = &pdev->dev; 941 i2c->adap.owner = THIS_MODULE; 942 i2c->adap.algo = &mtk_i2c_algorithm; 943 i2c->adap.quirks = i2c->dev_comp->quirks; 944 i2c->adap.timeout = 2 * HZ; 945 i2c->adap.retries = 1; 946 947 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 948 if (ret) 949 return -EINVAL; 950 951 if (i2c->dev_comp->timing_adjust) 952 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV; 953 954 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 955 return -EINVAL; 956 957 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 958 if (IS_ERR(i2c->clk_main)) { 959 dev_err(&pdev->dev, "cannot get main clock\n"); 960 return PTR_ERR(i2c->clk_main); 961 } 962 963 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 964 if (IS_ERR(i2c->clk_dma)) { 965 dev_err(&pdev->dev, "cannot get dma clock\n"); 966 return PTR_ERR(i2c->clk_dma); 967 } 968 969 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 970 if (IS_ERR(i2c->clk_arb)) 971 i2c->clk_arb = NULL; 972 973 clk = i2c->clk_main; 974 if (i2c->have_pmic) { 975 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 976 if (IS_ERR(i2c->clk_pmic)) { 977 dev_err(&pdev->dev, "cannot get pmic clock\n"); 978 return PTR_ERR(i2c->clk_pmic); 979 } 980 clk = i2c->clk_pmic; 981 } 982 983 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 984 985 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 986 if (ret) { 987 dev_err(&pdev->dev, "Failed to set the speed.\n"); 988 return -EINVAL; 989 } 990 991 if (i2c->dev_comp->support_33bits) { 992 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33)); 993 if (ret) { 994 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 995 return ret; 996 } 997 } 998 999 ret = mtk_i2c_clock_enable(i2c); 1000 if (ret) { 1001 dev_err(&pdev->dev, "clock enable failed!\n"); 1002 return ret; 1003 } 1004 mtk_i2c_init_hw(i2c); 1005 mtk_i2c_clock_disable(i2c); 1006 1007 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1008 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); 1009 if (ret < 0) { 1010 dev_err(&pdev->dev, 1011 "Request I2C IRQ %d fail\n", irq); 1012 return ret; 1013 } 1014 1015 i2c_set_adapdata(&i2c->adap, i2c); 1016 ret = i2c_add_adapter(&i2c->adap); 1017 if (ret) 1018 return ret; 1019 1020 platform_set_drvdata(pdev, i2c); 1021 1022 return 0; 1023 } 1024 1025 static int mtk_i2c_remove(struct platform_device *pdev) 1026 { 1027 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1028 1029 i2c_del_adapter(&i2c->adap); 1030 1031 return 0; 1032 } 1033 1034 #ifdef CONFIG_PM_SLEEP 1035 static int mtk_i2c_resume(struct device *dev) 1036 { 1037 int ret; 1038 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1039 1040 ret = mtk_i2c_clock_enable(i2c); 1041 if (ret) { 1042 dev_err(dev, "clock enable failed!\n"); 1043 return ret; 1044 } 1045 1046 mtk_i2c_init_hw(i2c); 1047 1048 mtk_i2c_clock_disable(i2c); 1049 1050 return 0; 1051 } 1052 #endif 1053 1054 static const struct dev_pm_ops mtk_i2c_pm = { 1055 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume) 1056 }; 1057 1058 static struct platform_driver mtk_i2c_driver = { 1059 .probe = mtk_i2c_probe, 1060 .remove = mtk_i2c_remove, 1061 .driver = { 1062 .name = I2C_DRV_NAME, 1063 .pm = &mtk_i2c_pm, 1064 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1065 }, 1066 }; 1067 1068 module_platform_driver(mtk_i2c_driver); 1069 1070 MODULE_LICENSE("GPL v2"); 1071 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1072 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1073