1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/drm_scdc_helper.h> 36 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 #include "dw-hdmi.h" 40 41 #define DDC_CI_ADDR 0x37 42 #define DDC_SEGMENT_ADDR 0x30 43 44 #define HDMI_EDID_LEN 512 45 46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 47 #define SCDC_MIN_SOURCE_VERSION 0x1 48 49 #define HDMI14_MAX_TMDSCLK 340000000 50 51 enum hdmi_datamap { 52 RGB444_8B = 0x01, 53 RGB444_10B = 0x03, 54 RGB444_12B = 0x05, 55 RGB444_16B = 0x07, 56 YCbCr444_8B = 0x09, 57 YCbCr444_10B = 0x0B, 58 YCbCr444_12B = 0x0D, 59 YCbCr444_16B = 0x0F, 60 YCbCr422_8B = 0x16, 61 YCbCr422_10B = 0x14, 62 YCbCr422_12B = 0x12, 63 }; 64 65 static const u16 csc_coeff_default[3][4] = { 66 { 0x2000, 0x0000, 0x0000, 0x0000 }, 67 { 0x0000, 0x2000, 0x0000, 0x0000 }, 68 { 0x0000, 0x0000, 0x2000, 0x0000 } 69 }; 70 71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 72 { 0x2000, 0x6926, 0x74fd, 0x010e }, 73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 74 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 75 }; 76 77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 78 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 79 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 80 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 81 }; 82 83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 84 { 0x2591, 0x1322, 0x074b, 0x0000 }, 85 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 86 { 0x6acd, 0x7534, 0x2000, 0x0200 } 87 }; 88 89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 91 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 92 { 0x6756, 0x78ab, 0x2000, 0x0200 } 93 }; 94 95 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 96 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 97 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 98 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 99 }; 100 101 struct hdmi_vmode { 102 bool mdataenablepolarity; 103 104 unsigned int mpixelclock; 105 unsigned int mpixelrepetitioninput; 106 unsigned int mpixelrepetitionoutput; 107 unsigned int mtmdsclock; 108 }; 109 110 struct hdmi_data_info { 111 unsigned int enc_in_bus_format; 112 unsigned int enc_out_bus_format; 113 unsigned int enc_in_encoding; 114 unsigned int enc_out_encoding; 115 unsigned int pix_repet_factor; 116 unsigned int hdcp_enable; 117 struct hdmi_vmode video_mode; 118 bool rgb_limited_range; 119 }; 120 121 struct dw_hdmi_i2c { 122 struct i2c_adapter adap; 123 124 struct mutex lock; /* used to serialize data transfers */ 125 struct completion cmp; 126 u8 stat; 127 128 u8 slave_reg; 129 bool is_regaddr; 130 bool is_segment; 131 }; 132 133 struct dw_hdmi_phy_data { 134 enum dw_hdmi_phy_type type; 135 const char *name; 136 unsigned int gen; 137 bool has_svsret; 138 int (*configure)(struct dw_hdmi *hdmi, 139 const struct dw_hdmi_plat_data *pdata, 140 unsigned long mpixelclock); 141 }; 142 143 struct dw_hdmi { 144 struct drm_connector connector; 145 struct drm_bridge bridge; 146 147 unsigned int version; 148 149 struct platform_device *audio; 150 struct platform_device *cec; 151 struct device *dev; 152 struct clk *isfr_clk; 153 struct clk *iahb_clk; 154 struct clk *cec_clk; 155 struct dw_hdmi_i2c *i2c; 156 157 struct hdmi_data_info hdmi_data; 158 const struct dw_hdmi_plat_data *plat_data; 159 160 int vic; 161 162 u8 edid[HDMI_EDID_LEN]; 163 164 struct { 165 const struct dw_hdmi_phy_ops *ops; 166 const char *name; 167 void *data; 168 bool enabled; 169 } phy; 170 171 struct drm_display_mode previous_mode; 172 173 struct i2c_adapter *ddc; 174 void __iomem *regs; 175 bool sink_is_hdmi; 176 bool sink_has_audio; 177 178 struct pinctrl *pinctrl; 179 struct pinctrl_state *default_state; 180 struct pinctrl_state *unwedge_state; 181 182 struct mutex mutex; /* for state below and previous_mode */ 183 enum drm_connector_force force; /* mutex-protected force state */ 184 bool disabled; /* DRM has disabled our bridge */ 185 bool bridge_is_on; /* indicates the bridge is on */ 186 bool rxsense; /* rxsense state */ 187 u8 phy_mask; /* desired phy int mask settings */ 188 u8 mc_clkdis; /* clock disable register */ 189 190 spinlock_t audio_lock; 191 struct mutex audio_mutex; 192 unsigned int sample_rate; 193 unsigned int audio_cts; 194 unsigned int audio_n; 195 bool audio_enable; 196 197 unsigned int reg_shift; 198 struct regmap *regm; 199 void (*enable_audio)(struct dw_hdmi *hdmi); 200 void (*disable_audio)(struct dw_hdmi *hdmi); 201 202 struct mutex cec_notifier_mutex; 203 struct cec_notifier *cec_notifier; 204 205 hdmi_codec_plugged_cb plugged_cb; 206 struct device *codec_dev; 207 enum drm_connector_status last_connector_result; 208 }; 209 210 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 211 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 212 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 213 214 #define HDMI_PHY_RX_SENSE \ 215 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 216 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 217 218 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 219 { 220 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 221 } 222 223 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 224 { 225 unsigned int val = 0; 226 227 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 228 229 return val; 230 } 231 232 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 233 { 234 if (hdmi->plugged_cb && hdmi->codec_dev) 235 hdmi->plugged_cb(hdmi->codec_dev, plugged); 236 } 237 238 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 239 struct device *codec_dev) 240 { 241 bool plugged; 242 243 mutex_lock(&hdmi->mutex); 244 hdmi->plugged_cb = fn; 245 hdmi->codec_dev = codec_dev; 246 plugged = hdmi->last_connector_result == connector_status_connected; 247 handle_plugged_change(hdmi, plugged); 248 mutex_unlock(&hdmi->mutex); 249 250 return 0; 251 } 252 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 253 254 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 255 { 256 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 257 } 258 259 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 260 u8 shift, u8 mask) 261 { 262 hdmi_modb(hdmi, data << shift, mask, reg); 263 } 264 265 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 266 { 267 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 268 HDMI_PHY_I2CM_INT_ADDR); 269 270 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 271 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 272 HDMI_PHY_I2CM_CTLINT_ADDR); 273 274 /* Software reset */ 275 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 276 277 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 278 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 279 280 /* Set done, not acknowledged and arbitration interrupt polarities */ 281 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 282 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 283 HDMI_I2CM_CTLINT); 284 285 /* Clear DONE and ERROR interrupts */ 286 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 287 HDMI_IH_I2CM_STAT0); 288 289 /* Mute DONE and ERROR interrupts */ 290 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 291 HDMI_IH_MUTE_I2CM_STAT0); 292 } 293 294 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 295 { 296 /* If no unwedge state then give up */ 297 if (!hdmi->unwedge_state) 298 return false; 299 300 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 301 302 /* 303 * This is a huge hack to workaround a problem where the dw_hdmi i2c 304 * bus could sometimes get wedged. Once wedged there doesn't appear 305 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 306 * other than pulsing the SDA line. 307 * 308 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 309 * by: 310 * 1. Remux the pin as a GPIO output, driven low. 311 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 312 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 313 * 314 * At the moment of remuxing, the line will still be low due to its 315 * recent stint as an output, but then it will be pulled high by the 316 * (presumed) external pullup. dw_hdmi seems to see this as a rising 317 * edge and that seems to get it out of its jam. 318 * 319 * This wedging was only ever seen on one TV, and only on one of 320 * its HDMI ports. It happened when the TV was powered on while the 321 * device was plugged in. A scope trace shows the TV bringing both SDA 322 * and SCL low, then bringing them both back up at roughly the same 323 * time. Presumably this confuses dw_hdmi because it saw activity but 324 * no real STOP (maybe it thinks there's another master on the bus?). 325 * Giving it a clean rising edge of SDA while SCL is already high 326 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 327 * of its stupor. 328 * 329 * Note that after coming back alive, transfers seem to immediately 330 * resume, so if we unwedge due to a timeout we should wait a little 331 * longer for our transfer to finish, since it might have just started 332 * now. 333 */ 334 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 335 msleep(10); 336 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 337 338 return true; 339 } 340 341 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 342 { 343 struct dw_hdmi_i2c *i2c = hdmi->i2c; 344 int stat; 345 346 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 347 if (!stat) { 348 /* If we can't unwedge, return timeout */ 349 if (!dw_hdmi_i2c_unwedge(hdmi)) 350 return -EAGAIN; 351 352 /* We tried to unwedge; give it another chance */ 353 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 354 if (!stat) 355 return -EAGAIN; 356 } 357 358 /* Check for error condition on the bus */ 359 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 360 return -EIO; 361 362 return 0; 363 } 364 365 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 366 unsigned char *buf, unsigned int length) 367 { 368 struct dw_hdmi_i2c *i2c = hdmi->i2c; 369 int ret; 370 371 if (!i2c->is_regaddr) { 372 dev_dbg(hdmi->dev, "set read register address to 0\n"); 373 i2c->slave_reg = 0x00; 374 i2c->is_regaddr = true; 375 } 376 377 while (length--) { 378 reinit_completion(&i2c->cmp); 379 380 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 381 if (i2c->is_segment) 382 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 383 HDMI_I2CM_OPERATION); 384 else 385 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 386 HDMI_I2CM_OPERATION); 387 388 ret = dw_hdmi_i2c_wait(hdmi); 389 if (ret) 390 return ret; 391 392 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 393 } 394 i2c->is_segment = false; 395 396 return 0; 397 } 398 399 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 400 unsigned char *buf, unsigned int length) 401 { 402 struct dw_hdmi_i2c *i2c = hdmi->i2c; 403 int ret; 404 405 if (!i2c->is_regaddr) { 406 /* Use the first write byte as register address */ 407 i2c->slave_reg = buf[0]; 408 length--; 409 buf++; 410 i2c->is_regaddr = true; 411 } 412 413 while (length--) { 414 reinit_completion(&i2c->cmp); 415 416 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 417 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 418 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 419 HDMI_I2CM_OPERATION); 420 421 ret = dw_hdmi_i2c_wait(hdmi); 422 if (ret) 423 return ret; 424 } 425 426 return 0; 427 } 428 429 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 430 struct i2c_msg *msgs, int num) 431 { 432 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 433 struct dw_hdmi_i2c *i2c = hdmi->i2c; 434 u8 addr = msgs[0].addr; 435 int i, ret = 0; 436 437 if (addr == DDC_CI_ADDR) 438 /* 439 * The internal I2C controller does not support the multi-byte 440 * read and write operations needed for DDC/CI. 441 * TOFIX: Blacklist the DDC/CI address until we filter out 442 * unsupported I2C operations. 443 */ 444 return -EOPNOTSUPP; 445 446 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 447 448 for (i = 0; i < num; i++) { 449 if (msgs[i].len == 0) { 450 dev_dbg(hdmi->dev, 451 "unsupported transfer %d/%d, no data\n", 452 i + 1, num); 453 return -EOPNOTSUPP; 454 } 455 } 456 457 mutex_lock(&i2c->lock); 458 459 /* Unmute DONE and ERROR interrupts */ 460 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 461 462 /* Set slave device address taken from the first I2C message */ 463 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 464 465 /* Set slave device register address on transfer */ 466 i2c->is_regaddr = false; 467 468 /* Set segment pointer for I2C extended read mode operation */ 469 i2c->is_segment = false; 470 471 for (i = 0; i < num; i++) { 472 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 473 i + 1, num, msgs[i].len, msgs[i].flags); 474 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 475 i2c->is_segment = true; 476 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 477 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 478 } else { 479 if (msgs[i].flags & I2C_M_RD) 480 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 481 msgs[i].len); 482 else 483 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 484 msgs[i].len); 485 } 486 if (ret < 0) 487 break; 488 } 489 490 if (!ret) 491 ret = num; 492 493 /* Mute DONE and ERROR interrupts */ 494 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 495 HDMI_IH_MUTE_I2CM_STAT0); 496 497 mutex_unlock(&i2c->lock); 498 499 return ret; 500 } 501 502 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 503 { 504 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 505 } 506 507 static const struct i2c_algorithm dw_hdmi_algorithm = { 508 .master_xfer = dw_hdmi_i2c_xfer, 509 .functionality = dw_hdmi_i2c_func, 510 }; 511 512 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 513 { 514 struct i2c_adapter *adap; 515 struct dw_hdmi_i2c *i2c; 516 int ret; 517 518 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 519 if (!i2c) 520 return ERR_PTR(-ENOMEM); 521 522 mutex_init(&i2c->lock); 523 init_completion(&i2c->cmp); 524 525 adap = &i2c->adap; 526 adap->class = I2C_CLASS_DDC; 527 adap->owner = THIS_MODULE; 528 adap->dev.parent = hdmi->dev; 529 adap->algo = &dw_hdmi_algorithm; 530 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 531 i2c_set_adapdata(adap, hdmi); 532 533 ret = i2c_add_adapter(adap); 534 if (ret) { 535 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 536 devm_kfree(hdmi->dev, i2c); 537 return ERR_PTR(ret); 538 } 539 540 hdmi->i2c = i2c; 541 542 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 543 544 return adap; 545 } 546 547 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 548 unsigned int n) 549 { 550 /* Must be set/cleared first */ 551 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 552 553 /* nshift factor = 0 */ 554 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 555 556 /* Use automatic CTS generation mode when CTS is not set */ 557 if (cts) 558 hdmi_writeb(hdmi, ((cts >> 16) & 559 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 560 HDMI_AUD_CTS3_CTS_MANUAL, 561 HDMI_AUD_CTS3); 562 else 563 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 564 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 565 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 566 567 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 568 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 569 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 570 } 571 572 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 573 { 574 unsigned int n = (128 * freq) / 1000; 575 unsigned int mult = 1; 576 577 while (freq > 48000) { 578 mult *= 2; 579 freq /= 2; 580 } 581 582 switch (freq) { 583 case 32000: 584 if (pixel_clk == 25175000) 585 n = 4576; 586 else if (pixel_clk == 27027000) 587 n = 4096; 588 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 589 n = 11648; 590 else 591 n = 4096; 592 n *= mult; 593 break; 594 595 case 44100: 596 if (pixel_clk == 25175000) 597 n = 7007; 598 else if (pixel_clk == 74176000) 599 n = 17836; 600 else if (pixel_clk == 148352000) 601 n = 8918; 602 else 603 n = 6272; 604 n *= mult; 605 break; 606 607 case 48000: 608 if (pixel_clk == 25175000) 609 n = 6864; 610 else if (pixel_clk == 27027000) 611 n = 6144; 612 else if (pixel_clk == 74176000) 613 n = 11648; 614 else if (pixel_clk == 148352000) 615 n = 5824; 616 else 617 n = 6144; 618 n *= mult; 619 break; 620 621 default: 622 break; 623 } 624 625 return n; 626 } 627 628 /* 629 * When transmitting IEC60958 linear PCM audio, these registers allow to 630 * configure the channel status information of all the channel status 631 * bits in the IEC60958 frame. For the moment this configuration is only 632 * used when the I2S audio interface, General Purpose Audio (GPA), 633 * or AHB audio DMA (AHBAUDDMA) interface is active 634 * (for S/PDIF interface this information comes from the stream). 635 */ 636 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 637 u8 *channel_status) 638 { 639 /* 640 * Set channel status register for frequency and word length. 641 * Use default values for other registers. 642 */ 643 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 644 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 645 } 646 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 647 648 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 649 unsigned long pixel_clk, unsigned int sample_rate) 650 { 651 unsigned long ftdms = pixel_clk; 652 unsigned int n, cts; 653 u8 config3; 654 u64 tmp; 655 656 n = hdmi_compute_n(sample_rate, pixel_clk); 657 658 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 659 660 /* Only compute CTS when using internal AHB audio */ 661 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 662 /* 663 * Compute the CTS value from the N value. Note that CTS and N 664 * can be up to 20 bits in total, so we need 64-bit math. Also 665 * note that our TDMS clock is not fully accurate; it is 666 * accurate to kHz. This can introduce an unnecessary remainder 667 * in the calculation below, so we don't try to warn about that. 668 */ 669 tmp = (u64)ftdms * n; 670 do_div(tmp, 128 * sample_rate); 671 cts = tmp; 672 673 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 674 __func__, sample_rate, 675 ftdms / 1000000, (ftdms / 1000) % 1000, 676 n, cts); 677 } else { 678 cts = 0; 679 } 680 681 spin_lock_irq(&hdmi->audio_lock); 682 hdmi->audio_n = n; 683 hdmi->audio_cts = cts; 684 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 685 spin_unlock_irq(&hdmi->audio_lock); 686 } 687 688 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 689 { 690 mutex_lock(&hdmi->audio_mutex); 691 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 692 mutex_unlock(&hdmi->audio_mutex); 693 } 694 695 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 696 { 697 mutex_lock(&hdmi->audio_mutex); 698 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 699 hdmi->sample_rate); 700 mutex_unlock(&hdmi->audio_mutex); 701 } 702 703 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 704 { 705 mutex_lock(&hdmi->audio_mutex); 706 hdmi->sample_rate = rate; 707 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 708 hdmi->sample_rate); 709 mutex_unlock(&hdmi->audio_mutex); 710 } 711 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 712 713 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 714 { 715 u8 layout; 716 717 mutex_lock(&hdmi->audio_mutex); 718 719 /* 720 * For >2 channel PCM audio, we need to select layout 1 721 * and set an appropriate channel map. 722 */ 723 if (cnt > 2) 724 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 725 else 726 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 727 728 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 729 HDMI_FC_AUDSCONF); 730 731 /* Set the audio infoframes channel count */ 732 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 733 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 734 735 mutex_unlock(&hdmi->audio_mutex); 736 } 737 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 738 739 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 740 { 741 mutex_lock(&hdmi->audio_mutex); 742 743 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 744 745 mutex_unlock(&hdmi->audio_mutex); 746 } 747 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 748 749 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 750 { 751 if (enable) 752 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 753 else 754 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 755 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 756 } 757 758 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 759 { 760 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 761 } 762 763 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 764 { 765 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 766 } 767 768 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 769 { 770 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 771 hdmi_enable_audio_clk(hdmi, true); 772 } 773 774 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 775 { 776 hdmi_enable_audio_clk(hdmi, false); 777 } 778 779 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 780 { 781 unsigned long flags; 782 783 spin_lock_irqsave(&hdmi->audio_lock, flags); 784 hdmi->audio_enable = true; 785 if (hdmi->enable_audio) 786 hdmi->enable_audio(hdmi); 787 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 788 } 789 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 790 791 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 792 { 793 unsigned long flags; 794 795 spin_lock_irqsave(&hdmi->audio_lock, flags); 796 hdmi->audio_enable = false; 797 if (hdmi->disable_audio) 798 hdmi->disable_audio(hdmi); 799 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 800 } 801 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 802 803 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 804 { 805 switch (bus_format) { 806 case MEDIA_BUS_FMT_RGB888_1X24: 807 case MEDIA_BUS_FMT_RGB101010_1X30: 808 case MEDIA_BUS_FMT_RGB121212_1X36: 809 case MEDIA_BUS_FMT_RGB161616_1X48: 810 return true; 811 812 default: 813 return false; 814 } 815 } 816 817 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 818 { 819 switch (bus_format) { 820 case MEDIA_BUS_FMT_YUV8_1X24: 821 case MEDIA_BUS_FMT_YUV10_1X30: 822 case MEDIA_BUS_FMT_YUV12_1X36: 823 case MEDIA_BUS_FMT_YUV16_1X48: 824 return true; 825 826 default: 827 return false; 828 } 829 } 830 831 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 832 { 833 switch (bus_format) { 834 case MEDIA_BUS_FMT_UYVY8_1X16: 835 case MEDIA_BUS_FMT_UYVY10_1X20: 836 case MEDIA_BUS_FMT_UYVY12_1X24: 837 return true; 838 839 default: 840 return false; 841 } 842 } 843 844 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 845 { 846 switch (bus_format) { 847 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 848 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 849 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 850 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 851 return true; 852 853 default: 854 return false; 855 } 856 } 857 858 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 859 { 860 switch (bus_format) { 861 case MEDIA_BUS_FMT_RGB888_1X24: 862 case MEDIA_BUS_FMT_YUV8_1X24: 863 case MEDIA_BUS_FMT_UYVY8_1X16: 864 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 865 return 8; 866 867 case MEDIA_BUS_FMT_RGB101010_1X30: 868 case MEDIA_BUS_FMT_YUV10_1X30: 869 case MEDIA_BUS_FMT_UYVY10_1X20: 870 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 871 return 10; 872 873 case MEDIA_BUS_FMT_RGB121212_1X36: 874 case MEDIA_BUS_FMT_YUV12_1X36: 875 case MEDIA_BUS_FMT_UYVY12_1X24: 876 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 877 return 12; 878 879 case MEDIA_BUS_FMT_RGB161616_1X48: 880 case MEDIA_BUS_FMT_YUV16_1X48: 881 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 882 return 16; 883 884 default: 885 return 0; 886 } 887 } 888 889 /* 890 * this submodule is responsible for the video data synchronization. 891 * for example, for RGB 4:4:4 input, the data map is defined as 892 * pin{47~40} <==> R[7:0] 893 * pin{31~24} <==> G[7:0] 894 * pin{15~8} <==> B[7:0] 895 */ 896 static void hdmi_video_sample(struct dw_hdmi *hdmi) 897 { 898 int color_format = 0; 899 u8 val; 900 901 switch (hdmi->hdmi_data.enc_in_bus_format) { 902 case MEDIA_BUS_FMT_RGB888_1X24: 903 color_format = 0x01; 904 break; 905 case MEDIA_BUS_FMT_RGB101010_1X30: 906 color_format = 0x03; 907 break; 908 case MEDIA_BUS_FMT_RGB121212_1X36: 909 color_format = 0x05; 910 break; 911 case MEDIA_BUS_FMT_RGB161616_1X48: 912 color_format = 0x07; 913 break; 914 915 case MEDIA_BUS_FMT_YUV8_1X24: 916 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 917 color_format = 0x09; 918 break; 919 case MEDIA_BUS_FMT_YUV10_1X30: 920 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 921 color_format = 0x0B; 922 break; 923 case MEDIA_BUS_FMT_YUV12_1X36: 924 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 925 color_format = 0x0D; 926 break; 927 case MEDIA_BUS_FMT_YUV16_1X48: 928 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 929 color_format = 0x0F; 930 break; 931 932 case MEDIA_BUS_FMT_UYVY8_1X16: 933 color_format = 0x16; 934 break; 935 case MEDIA_BUS_FMT_UYVY10_1X20: 936 color_format = 0x14; 937 break; 938 case MEDIA_BUS_FMT_UYVY12_1X24: 939 color_format = 0x12; 940 break; 941 942 default: 943 return; 944 } 945 946 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 947 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 948 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 949 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 950 951 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 952 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 953 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 954 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 955 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 956 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 957 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 958 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 959 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 960 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 961 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 962 } 963 964 static int is_color_space_conversion(struct dw_hdmi *hdmi) 965 { 966 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 967 bool is_input_rgb, is_output_rgb; 968 969 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 970 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 971 972 return (is_input_rgb != is_output_rgb) || 973 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 974 } 975 976 static int is_color_space_decimation(struct dw_hdmi *hdmi) 977 { 978 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 979 return 0; 980 981 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 982 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 983 return 1; 984 985 return 0; 986 } 987 988 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 989 { 990 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 991 return 0; 992 993 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 994 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 995 return 1; 996 997 return 0; 998 } 999 1000 static bool is_csc_needed(struct dw_hdmi *hdmi) 1001 { 1002 return is_color_space_conversion(hdmi) || 1003 is_color_space_decimation(hdmi) || 1004 is_color_space_interpolation(hdmi); 1005 } 1006 1007 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1008 { 1009 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1010 bool is_input_rgb, is_output_rgb; 1011 unsigned i; 1012 u32 csc_scale = 1; 1013 1014 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1015 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1016 1017 if (!is_input_rgb && is_output_rgb) { 1018 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1019 csc_coeff = &csc_coeff_rgb_out_eitu601; 1020 else 1021 csc_coeff = &csc_coeff_rgb_out_eitu709; 1022 } else if (is_input_rgb && !is_output_rgb) { 1023 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1024 csc_coeff = &csc_coeff_rgb_in_eitu601; 1025 else 1026 csc_coeff = &csc_coeff_rgb_in_eitu709; 1027 csc_scale = 0; 1028 } else if (is_input_rgb && is_output_rgb && 1029 hdmi->hdmi_data.rgb_limited_range) { 1030 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1031 } 1032 1033 /* The CSC registers are sequential, alternating MSB then LSB */ 1034 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1035 u16 coeff_a = (*csc_coeff)[0][i]; 1036 u16 coeff_b = (*csc_coeff)[1][i]; 1037 u16 coeff_c = (*csc_coeff)[2][i]; 1038 1039 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1040 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1041 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1042 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1043 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1044 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1045 } 1046 1047 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1048 HDMI_CSC_SCALE); 1049 } 1050 1051 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1052 { 1053 int color_depth = 0; 1054 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1055 int decimation = 0; 1056 1057 /* YCC422 interpolation to 444 mode */ 1058 if (is_color_space_interpolation(hdmi)) 1059 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1060 else if (is_color_space_decimation(hdmi)) 1061 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1062 1063 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1064 case 8: 1065 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1066 break; 1067 case 10: 1068 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1069 break; 1070 case 12: 1071 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1072 break; 1073 case 16: 1074 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1075 break; 1076 1077 default: 1078 return; 1079 } 1080 1081 /* Configure the CSC registers */ 1082 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1083 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1084 HDMI_CSC_SCALE); 1085 1086 dw_hdmi_update_csc_coeffs(hdmi); 1087 } 1088 1089 /* 1090 * HDMI video packetizer is used to packetize the data. 1091 * for example, if input is YCC422 mode or repeater is used, 1092 * data should be repacked this module can be bypassed. 1093 */ 1094 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1095 { 1096 unsigned int color_depth = 0; 1097 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1098 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1099 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1100 u8 val, vp_conf; 1101 1102 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1103 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1104 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1105 switch (hdmi_bus_fmt_color_depth( 1106 hdmi->hdmi_data.enc_out_bus_format)) { 1107 case 8: 1108 color_depth = 4; 1109 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1110 break; 1111 case 10: 1112 color_depth = 5; 1113 break; 1114 case 12: 1115 color_depth = 6; 1116 break; 1117 case 16: 1118 color_depth = 7; 1119 break; 1120 default: 1121 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1122 } 1123 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1124 switch (hdmi_bus_fmt_color_depth( 1125 hdmi->hdmi_data.enc_out_bus_format)) { 1126 case 0: 1127 case 8: 1128 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1129 break; 1130 case 10: 1131 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1132 break; 1133 case 12: 1134 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1135 break; 1136 1137 default: 1138 return; 1139 } 1140 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1141 } else { 1142 return; 1143 } 1144 1145 /* set the packetizer registers */ 1146 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1147 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1148 ((hdmi_data->pix_repet_factor << 1149 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1150 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1151 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1152 1153 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1154 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1155 1156 /* Data from pixel repeater block */ 1157 if (hdmi_data->pix_repet_factor > 1) { 1158 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1159 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1160 } else { /* data from packetizer block */ 1161 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1162 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1163 } 1164 1165 hdmi_modb(hdmi, vp_conf, 1166 HDMI_VP_CONF_PR_EN_MASK | 1167 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1168 1169 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1170 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1171 1172 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1173 1174 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1175 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1176 HDMI_VP_CONF_PP_EN_ENABLE | 1177 HDMI_VP_CONF_YCC422_EN_DISABLE; 1178 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1179 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1180 HDMI_VP_CONF_PP_EN_DISABLE | 1181 HDMI_VP_CONF_YCC422_EN_ENABLE; 1182 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1183 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1184 HDMI_VP_CONF_PP_EN_DISABLE | 1185 HDMI_VP_CONF_YCC422_EN_DISABLE; 1186 } else { 1187 return; 1188 } 1189 1190 hdmi_modb(hdmi, vp_conf, 1191 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1192 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1193 1194 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1195 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1196 HDMI_VP_STUFF_PP_STUFFING_MASK | 1197 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1198 1199 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1200 HDMI_VP_CONF); 1201 } 1202 1203 /* ----------------------------------------------------------------------------- 1204 * Synopsys PHY Handling 1205 */ 1206 1207 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1208 unsigned char bit) 1209 { 1210 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1211 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1212 } 1213 1214 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1215 { 1216 u32 val; 1217 1218 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1219 if (msec-- == 0) 1220 return false; 1221 udelay(1000); 1222 } 1223 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1224 1225 return true; 1226 } 1227 1228 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1229 unsigned char addr) 1230 { 1231 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1232 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1233 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1234 HDMI_PHY_I2CM_DATAO_1_ADDR); 1235 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1236 HDMI_PHY_I2CM_DATAO_0_ADDR); 1237 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1238 HDMI_PHY_I2CM_OPERATION_ADDR); 1239 hdmi_phy_wait_i2c_done(hdmi, 1000); 1240 } 1241 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1242 1243 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1244 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1245 { 1246 struct drm_display_info *display = &hdmi->connector.display_info; 1247 1248 /* Completely disable SCDC support for older controllers */ 1249 if (hdmi->version < 0x200a) 1250 return false; 1251 1252 /* Disable if no DDC bus */ 1253 if (!hdmi->ddc) 1254 return false; 1255 1256 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1257 if (!display->hdmi.scdc.supported || 1258 !display->hdmi.scdc.scrambling.supported) 1259 return false; 1260 1261 /* 1262 * Disable if display only support low TMDS rates and scrambling 1263 * for low rates is not supported either 1264 */ 1265 if (!display->hdmi.scdc.scrambling.low_rates && 1266 display->max_tmds_clock <= 340000) 1267 return false; 1268 1269 return true; 1270 } 1271 1272 /* 1273 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1274 * - The Source shall suspend transmission of the TMDS clock and data 1275 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1276 * from a 0 to a 1 or from a 1 to a 0 1277 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1278 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1279 * transmission of TMDS clock and data 1280 * 1281 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1282 * helper should called right before enabling the TMDS Clock and Data in 1283 * the PHY configuration callback. 1284 */ 1285 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1286 { 1287 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1288 1289 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1290 if (dw_hdmi_support_scdc(hdmi)) { 1291 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1292 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1293 else 1294 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1295 } 1296 } 1297 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1298 1299 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1300 { 1301 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1302 HDMI_PHY_CONF0_PDZ_OFFSET, 1303 HDMI_PHY_CONF0_PDZ_MASK); 1304 } 1305 1306 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1307 { 1308 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1309 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1310 HDMI_PHY_CONF0_ENTMDS_MASK); 1311 } 1312 1313 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1314 { 1315 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1316 HDMI_PHY_CONF0_SVSRET_OFFSET, 1317 HDMI_PHY_CONF0_SVSRET_MASK); 1318 } 1319 1320 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1321 { 1322 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1323 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1324 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1325 } 1326 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1327 1328 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1329 { 1330 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1331 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1332 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1333 } 1334 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1335 1336 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1337 { 1338 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1339 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1340 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1341 } 1342 1343 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1344 { 1345 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1346 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1347 HDMI_PHY_CONF0_SELDIPIF_MASK); 1348 } 1349 1350 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1351 { 1352 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1353 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1354 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1355 } 1356 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1357 1358 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1359 { 1360 hdmi_phy_test_clear(hdmi, 1); 1361 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1362 hdmi_phy_test_clear(hdmi, 0); 1363 } 1364 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1365 1366 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1367 { 1368 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1369 unsigned int i; 1370 u16 val; 1371 1372 if (phy->gen == 1) { 1373 dw_hdmi_phy_enable_tmds(hdmi, 0); 1374 dw_hdmi_phy_enable_powerdown(hdmi, true); 1375 return; 1376 } 1377 1378 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1379 1380 /* 1381 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1382 * to low power mode. 1383 */ 1384 for (i = 0; i < 5; ++i) { 1385 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1386 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1387 break; 1388 1389 usleep_range(1000, 2000); 1390 } 1391 1392 if (val & HDMI_PHY_TX_PHY_LOCK) 1393 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1394 else 1395 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1396 1397 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1398 } 1399 1400 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1401 { 1402 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1403 unsigned int i; 1404 u8 val; 1405 1406 if (phy->gen == 1) { 1407 dw_hdmi_phy_enable_powerdown(hdmi, false); 1408 1409 /* Toggle TMDS enable. */ 1410 dw_hdmi_phy_enable_tmds(hdmi, 0); 1411 dw_hdmi_phy_enable_tmds(hdmi, 1); 1412 return 0; 1413 } 1414 1415 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1416 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1417 1418 /* Wait for PHY PLL lock */ 1419 for (i = 0; i < 5; ++i) { 1420 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1421 if (val) 1422 break; 1423 1424 usleep_range(1000, 2000); 1425 } 1426 1427 if (!val) { 1428 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1429 return -ETIMEDOUT; 1430 } 1431 1432 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1433 return 0; 1434 } 1435 1436 /* 1437 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1438 * information the DWC MHL PHY has the same register layout and is thus also 1439 * supported by this function. 1440 */ 1441 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1442 const struct dw_hdmi_plat_data *pdata, 1443 unsigned long mpixelclock) 1444 { 1445 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1446 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1447 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1448 1449 /* TOFIX Will need 420 specific PHY configuration tables */ 1450 1451 /* PLL/MPLL Cfg - always match on final entry */ 1452 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1453 if (mpixelclock <= mpll_config->mpixelclock) 1454 break; 1455 1456 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1457 if (mpixelclock <= curr_ctrl->mpixelclock) 1458 break; 1459 1460 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1461 if (mpixelclock <= phy_config->mpixelclock) 1462 break; 1463 1464 if (mpll_config->mpixelclock == ~0UL || 1465 curr_ctrl->mpixelclock == ~0UL || 1466 phy_config->mpixelclock == ~0UL) 1467 return -EINVAL; 1468 1469 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1470 HDMI_3D_TX_PHY_CPCE_CTRL); 1471 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1472 HDMI_3D_TX_PHY_GMPCTRL); 1473 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1474 HDMI_3D_TX_PHY_CURRCTRL); 1475 1476 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1477 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1478 HDMI_3D_TX_PHY_MSM_CTRL); 1479 1480 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1481 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1482 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1483 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1484 HDMI_3D_TX_PHY_VLEVCTRL); 1485 1486 /* Override and disable clock termination. */ 1487 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1488 HDMI_3D_TX_PHY_CKCALCTRL); 1489 1490 return 0; 1491 } 1492 1493 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1494 { 1495 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1496 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1497 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1498 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1499 int ret; 1500 1501 dw_hdmi_phy_power_off(hdmi); 1502 1503 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1504 1505 /* Leave low power consumption mode by asserting SVSRET. */ 1506 if (phy->has_svsret) 1507 dw_hdmi_phy_enable_svsret(hdmi, 1); 1508 1509 dw_hdmi_phy_reset(hdmi); 1510 1511 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1512 1513 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1514 1515 /* Write to the PHY as configured by the platform */ 1516 if (pdata->configure_phy) 1517 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1518 else 1519 ret = phy->configure(hdmi, pdata, mpixelclock); 1520 if (ret) { 1521 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1522 mpixelclock); 1523 return ret; 1524 } 1525 1526 /* Wait for resuming transmission of TMDS clock and data */ 1527 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1528 msleep(100); 1529 1530 return dw_hdmi_phy_power_on(hdmi); 1531 } 1532 1533 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1534 struct drm_display_mode *mode) 1535 { 1536 int i, ret; 1537 1538 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1539 for (i = 0; i < 2; i++) { 1540 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1541 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1542 1543 ret = hdmi_phy_configure(hdmi); 1544 if (ret) 1545 return ret; 1546 } 1547 1548 return 0; 1549 } 1550 1551 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1552 { 1553 dw_hdmi_phy_power_off(hdmi); 1554 } 1555 1556 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1557 void *data) 1558 { 1559 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1560 connector_status_connected : connector_status_disconnected; 1561 } 1562 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1563 1564 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1565 bool force, bool disabled, bool rxsense) 1566 { 1567 u8 old_mask = hdmi->phy_mask; 1568 1569 if (force || disabled || !rxsense) 1570 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1571 else 1572 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1573 1574 if (old_mask != hdmi->phy_mask) 1575 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1576 } 1577 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1578 1579 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1580 { 1581 /* 1582 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1583 * any pending interrupt. 1584 */ 1585 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1586 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1587 HDMI_IH_PHY_STAT0); 1588 1589 /* Enable cable hot plug irq. */ 1590 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1591 1592 /* Clear and unmute interrupts. */ 1593 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1594 HDMI_IH_PHY_STAT0); 1595 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1596 HDMI_IH_MUTE_PHY_STAT0); 1597 } 1598 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1599 1600 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1601 .init = dw_hdmi_phy_init, 1602 .disable = dw_hdmi_phy_disable, 1603 .read_hpd = dw_hdmi_phy_read_hpd, 1604 .update_hpd = dw_hdmi_phy_update_hpd, 1605 .setup_hpd = dw_hdmi_phy_setup_hpd, 1606 }; 1607 1608 /* ----------------------------------------------------------------------------- 1609 * HDMI TX Setup 1610 */ 1611 1612 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1613 { 1614 u8 de; 1615 1616 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1617 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1618 else 1619 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1620 1621 /* disable rx detect */ 1622 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1623 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1624 1625 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1626 1627 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1628 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1629 } 1630 1631 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1632 { 1633 struct hdmi_avi_infoframe frame; 1634 u8 val; 1635 1636 /* Initialise info frame from DRM mode */ 1637 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1638 &hdmi->connector, mode); 1639 1640 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1641 drm_hdmi_avi_infoframe_quant_range(&frame, &hdmi->connector, 1642 mode, 1643 hdmi->hdmi_data.rgb_limited_range ? 1644 HDMI_QUANTIZATION_RANGE_LIMITED : 1645 HDMI_QUANTIZATION_RANGE_FULL); 1646 } else { 1647 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1648 frame.ycc_quantization_range = 1649 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1650 } 1651 1652 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1653 frame.colorspace = HDMI_COLORSPACE_YUV444; 1654 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1655 frame.colorspace = HDMI_COLORSPACE_YUV422; 1656 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1657 frame.colorspace = HDMI_COLORSPACE_YUV420; 1658 else 1659 frame.colorspace = HDMI_COLORSPACE_RGB; 1660 1661 /* Set up colorimetry */ 1662 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1663 switch (hdmi->hdmi_data.enc_out_encoding) { 1664 case V4L2_YCBCR_ENC_601: 1665 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1666 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1667 else 1668 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1669 frame.extended_colorimetry = 1670 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1671 break; 1672 case V4L2_YCBCR_ENC_709: 1673 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1674 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1675 else 1676 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1677 frame.extended_colorimetry = 1678 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1679 break; 1680 default: /* Carries no data */ 1681 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1682 frame.extended_colorimetry = 1683 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1684 break; 1685 } 1686 } else { 1687 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1688 frame.extended_colorimetry = 1689 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1690 } 1691 1692 /* 1693 * The Designware IP uses a different byte format from standard 1694 * AVI info frames, though generally the bits are in the correct 1695 * bytes. 1696 */ 1697 1698 /* 1699 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1700 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1701 * bit 6 rather than 4. 1702 */ 1703 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1704 if (frame.active_aspect & 15) 1705 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1706 if (frame.top_bar || frame.bottom_bar) 1707 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1708 if (frame.left_bar || frame.right_bar) 1709 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1710 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1711 1712 /* AVI data byte 2 differences: none */ 1713 val = ((frame.colorimetry & 0x3) << 6) | 1714 ((frame.picture_aspect & 0x3) << 4) | 1715 (frame.active_aspect & 0xf); 1716 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1717 1718 /* AVI data byte 3 differences: none */ 1719 val = ((frame.extended_colorimetry & 0x7) << 4) | 1720 ((frame.quantization_range & 0x3) << 2) | 1721 (frame.nups & 0x3); 1722 if (frame.itc) 1723 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1724 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1725 1726 /* AVI data byte 4 differences: none */ 1727 val = frame.video_code & 0x7f; 1728 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1729 1730 /* AVI Data Byte 5- set up input and output pixel repetition */ 1731 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1732 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1733 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1734 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1735 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1736 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1737 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1738 1739 /* 1740 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1741 * ycc range in bits 2,3 rather than 6,7 1742 */ 1743 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1744 (frame.content_type & 0x3); 1745 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1746 1747 /* AVI Data Bytes 6-13 */ 1748 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1749 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1750 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1751 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1752 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1753 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1754 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1755 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1756 } 1757 1758 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1759 struct drm_display_mode *mode) 1760 { 1761 struct hdmi_vendor_infoframe frame; 1762 u8 buffer[10]; 1763 ssize_t err; 1764 1765 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1766 &hdmi->connector, 1767 mode); 1768 if (err < 0) 1769 /* 1770 * Going into that statement does not means vendor infoframe 1771 * fails. It just informed us that vendor infoframe is not 1772 * needed for the selected mode. Only 4k or stereoscopic 3D 1773 * mode requires vendor infoframe. So just simply return. 1774 */ 1775 return; 1776 1777 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1778 if (err < 0) { 1779 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1780 err); 1781 return; 1782 } 1783 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1784 HDMI_FC_DATAUTO0_VSD_MASK); 1785 1786 /* Set the length of HDMI vendor specific InfoFrame payload */ 1787 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1788 1789 /* Set 24bit IEEE Registration Identifier */ 1790 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1791 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1792 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1793 1794 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1795 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1796 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1797 1798 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1799 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1800 1801 /* Packet frame interpolation */ 1802 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1803 1804 /* Auto packets per frame and line spacing */ 1805 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1806 1807 /* Configures the Frame Composer On RDRB mode */ 1808 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1809 HDMI_FC_DATAUTO0_VSD_MASK); 1810 } 1811 1812 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi) 1813 { 1814 const struct drm_connector_state *conn_state = hdmi->connector.state; 1815 struct hdmi_drm_infoframe frame; 1816 u8 buffer[30]; 1817 ssize_t err; 1818 int i; 1819 1820 if (!hdmi->plat_data->use_drm_infoframe) 1821 return; 1822 1823 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1824 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1825 1826 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1827 if (err < 0) 1828 return; 1829 1830 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1831 if (err < 0) { 1832 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1833 return; 1834 } 1835 1836 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1837 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1838 1839 for (i = 0; i < frame.length; i++) 1840 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1841 1842 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1843 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1844 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1845 } 1846 1847 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1848 const struct drm_display_mode *mode) 1849 { 1850 u8 inv_val, bytes; 1851 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1852 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1853 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1854 unsigned int vdisplay, hdisplay; 1855 1856 vmode->mpixelclock = mode->clock * 1000; 1857 1858 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1859 1860 vmode->mtmdsclock = vmode->mpixelclock; 1861 1862 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1863 switch (hdmi_bus_fmt_color_depth( 1864 hdmi->hdmi_data.enc_out_bus_format)) { 1865 case 16: 1866 vmode->mtmdsclock = vmode->mpixelclock * 2; 1867 break; 1868 case 12: 1869 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 1870 break; 1871 case 10: 1872 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 1873 break; 1874 } 1875 } 1876 1877 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1878 vmode->mtmdsclock /= 2; 1879 1880 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 1881 1882 /* Set up HDMI_FC_INVIDCONF */ 1883 inv_val = (hdmi->hdmi_data.hdcp_enable || 1884 (dw_hdmi_support_scdc(hdmi) && 1885 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1886 hdmi_info->scdc.scrambling.low_rates)) ? 1887 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1888 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1889 1890 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1891 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1892 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1893 1894 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1895 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1896 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1897 1898 inv_val |= (vmode->mdataenablepolarity ? 1899 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1900 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1901 1902 if (hdmi->vic == 39) 1903 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1904 else 1905 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1906 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1907 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1908 1909 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1910 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1911 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1912 1913 inv_val |= hdmi->sink_is_hdmi ? 1914 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1915 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1916 1917 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1918 1919 hdisplay = mode->hdisplay; 1920 hblank = mode->htotal - mode->hdisplay; 1921 h_de_hs = mode->hsync_start - mode->hdisplay; 1922 hsync_len = mode->hsync_end - mode->hsync_start; 1923 1924 /* 1925 * When we're setting a YCbCr420 mode, we need 1926 * to adjust the horizontal timing to suit. 1927 */ 1928 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1929 hdisplay /= 2; 1930 hblank /= 2; 1931 h_de_hs /= 2; 1932 hsync_len /= 2; 1933 } 1934 1935 vdisplay = mode->vdisplay; 1936 vblank = mode->vtotal - mode->vdisplay; 1937 v_de_vs = mode->vsync_start - mode->vdisplay; 1938 vsync_len = mode->vsync_end - mode->vsync_start; 1939 1940 /* 1941 * When we're setting an interlaced mode, we need 1942 * to adjust the vertical timing to suit. 1943 */ 1944 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1945 vdisplay /= 2; 1946 vblank /= 2; 1947 v_de_vs /= 2; 1948 vsync_len /= 2; 1949 } 1950 1951 /* Scrambling Control */ 1952 if (dw_hdmi_support_scdc(hdmi)) { 1953 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1954 hdmi_info->scdc.scrambling.low_rates) { 1955 /* 1956 * HDMI2.0 Specifies the following procedure: 1957 * After the Source Device has determined that 1958 * SCDC_Present is set (=1), the Source Device should 1959 * write the accurate Version of the Source Device 1960 * to the Source Version field in the SCDCS. 1961 * Source Devices compliant shall set the 1962 * Source Version = 1. 1963 */ 1964 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1965 &bytes); 1966 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1967 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1968 1969 /* Enabled Scrambling in the Sink */ 1970 drm_scdc_set_scrambling(hdmi->ddc, 1); 1971 1972 /* 1973 * To activate the scrambler feature, you must ensure 1974 * that the quasi-static configuration bit 1975 * fc_invidconf.HDCP_keepout is set at configuration 1976 * time, before the required mc_swrstzreq.tmdsswrst_req 1977 * reset request is issued. 1978 */ 1979 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1980 HDMI_MC_SWRSTZ); 1981 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1982 } else { 1983 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1984 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1985 HDMI_MC_SWRSTZ); 1986 drm_scdc_set_scrambling(hdmi->ddc, 0); 1987 } 1988 } 1989 1990 /* Set up horizontal active pixel width */ 1991 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1992 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1993 1994 /* Set up vertical active lines */ 1995 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1996 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1997 1998 /* Set up horizontal blanking pixel region width */ 1999 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2000 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2001 2002 /* Set up vertical blanking pixel region width */ 2003 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2004 2005 /* Set up HSYNC active edge delay width (in pixel clks) */ 2006 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2007 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2008 2009 /* Set up VSYNC active edge delay (in lines) */ 2010 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2011 2012 /* Set up HSYNC active pulse width (in pixel clks) */ 2013 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2014 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2015 2016 /* Set up VSYNC active edge delay (in lines) */ 2017 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2018 } 2019 2020 /* HDMI Initialization Step B.4 */ 2021 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2022 { 2023 /* control period minimum duration */ 2024 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2025 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2026 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2027 2028 /* Set to fill TMDS data channels */ 2029 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2030 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2031 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2032 2033 /* Enable pixel clock and tmds data path */ 2034 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2035 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2036 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2037 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2038 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2039 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2040 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2041 2042 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2043 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2044 2045 /* Enable csc path */ 2046 if (is_csc_needed(hdmi)) { 2047 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2048 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2049 2050 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2051 HDMI_MC_FLOWCTRL); 2052 } else { 2053 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2054 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2055 2056 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2057 HDMI_MC_FLOWCTRL); 2058 } 2059 } 2060 2061 /* Workaround to clear the overflow condition */ 2062 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2063 { 2064 unsigned int count; 2065 unsigned int i; 2066 u8 val; 2067 2068 /* 2069 * Under some circumstances the Frame Composer arithmetic unit can miss 2070 * an FC register write due to being busy processing the previous one. 2071 * The issue can be worked around by issuing a TMDS software reset and 2072 * then write one of the FC registers several times. 2073 * 2074 * The number of iterations matters and depends on the HDMI TX revision 2075 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 2076 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 2077 * as needing the workaround, with 4 iterations for v1.30a and 1 2078 * iteration for others. 2079 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 2080 * the workaround with a single iteration. 2081 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 2082 * been identified as needing the workaround with a single iteration. 2083 */ 2084 2085 switch (hdmi->version) { 2086 case 0x130a: 2087 count = 4; 2088 break; 2089 case 0x131a: 2090 case 0x132a: 2091 case 0x200a: 2092 case 0x201a: 2093 case 0x211a: 2094 case 0x212a: 2095 count = 1; 2096 break; 2097 default: 2098 return; 2099 } 2100 2101 /* TMDS software reset */ 2102 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2103 2104 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2105 for (i = 0; i < count; i++) 2106 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2107 } 2108 2109 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2110 { 2111 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2112 HDMI_IH_MUTE_FC_STAT2); 2113 } 2114 2115 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 2116 { 2117 int ret; 2118 2119 hdmi_disable_overflow_interrupts(hdmi); 2120 2121 hdmi->vic = drm_match_cea_mode(mode); 2122 2123 if (!hdmi->vic) { 2124 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2125 } else { 2126 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2127 } 2128 2129 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2130 (hdmi->vic == 21) || (hdmi->vic == 22) || 2131 (hdmi->vic == 2) || (hdmi->vic == 3) || 2132 (hdmi->vic == 17) || (hdmi->vic == 18)) 2133 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2134 else 2135 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2136 2137 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2138 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2139 2140 if (hdmi->plat_data->input_bus_format) 2141 hdmi->hdmi_data.enc_in_bus_format = 2142 hdmi->plat_data->input_bus_format; 2143 else if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2144 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2145 2146 /* TOFIX: Get input encoding from plat data or fallback to none */ 2147 if (hdmi->plat_data->input_bus_encoding) 2148 hdmi->hdmi_data.enc_in_encoding = 2149 hdmi->plat_data->input_bus_encoding; 2150 else 2151 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2152 2153 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2154 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2155 2156 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2157 drm_default_rgb_quant_range(mode) == 2158 HDMI_QUANTIZATION_RANGE_LIMITED; 2159 2160 hdmi->hdmi_data.pix_repet_factor = 0; 2161 hdmi->hdmi_data.hdcp_enable = 0; 2162 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2163 2164 /* HDMI Initialization Step B.1 */ 2165 hdmi_av_composer(hdmi, mode); 2166 2167 /* HDMI Initializateion Step B.2 */ 2168 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 2169 if (ret) 2170 return ret; 2171 hdmi->phy.enabled = true; 2172 2173 /* HDMI Initialization Step B.3 */ 2174 dw_hdmi_enable_video_path(hdmi); 2175 2176 if (hdmi->sink_has_audio) { 2177 dev_dbg(hdmi->dev, "sink has audio support\n"); 2178 2179 /* HDMI Initialization Step E - Configure audio */ 2180 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2181 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2182 } 2183 2184 /* not for DVI mode */ 2185 if (hdmi->sink_is_hdmi) { 2186 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2187 2188 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2189 hdmi_config_AVI(hdmi, mode); 2190 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2191 hdmi_config_drm_infoframe(hdmi); 2192 } else { 2193 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2194 } 2195 2196 hdmi_video_packetize(hdmi); 2197 hdmi_video_csc(hdmi); 2198 hdmi_video_sample(hdmi); 2199 hdmi_tx_hdcp_config(hdmi); 2200 2201 dw_hdmi_clear_overflow(hdmi); 2202 2203 return 0; 2204 } 2205 2206 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2207 { 2208 u8 ih_mute; 2209 2210 /* 2211 * Boot up defaults are: 2212 * HDMI_IH_MUTE = 0x03 (disabled) 2213 * HDMI_IH_MUTE_* = 0x00 (enabled) 2214 * 2215 * Disable top level interrupt bits in HDMI block 2216 */ 2217 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2218 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2219 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2220 2221 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2222 2223 /* by default mask all interrupts */ 2224 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2225 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2226 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2227 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2228 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2229 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2230 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2231 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2232 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2233 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2234 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2235 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2236 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2237 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2238 2239 /* Disable interrupts in the IH_MUTE_* registers */ 2240 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2241 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2242 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2243 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2244 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2245 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2246 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2247 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2248 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2249 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2250 2251 /* Enable top level interrupt bits in HDMI block */ 2252 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2253 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2254 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2255 } 2256 2257 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2258 { 2259 hdmi->bridge_is_on = true; 2260 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2261 } 2262 2263 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2264 { 2265 if (hdmi->phy.enabled) { 2266 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2267 hdmi->phy.enabled = false; 2268 } 2269 2270 hdmi->bridge_is_on = false; 2271 } 2272 2273 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2274 { 2275 int force = hdmi->force; 2276 2277 if (hdmi->disabled) { 2278 force = DRM_FORCE_OFF; 2279 } else if (force == DRM_FORCE_UNSPECIFIED) { 2280 if (hdmi->rxsense) 2281 force = DRM_FORCE_ON; 2282 else 2283 force = DRM_FORCE_OFF; 2284 } 2285 2286 if (force == DRM_FORCE_OFF) { 2287 if (hdmi->bridge_is_on) 2288 dw_hdmi_poweroff(hdmi); 2289 } else { 2290 if (!hdmi->bridge_is_on) 2291 dw_hdmi_poweron(hdmi); 2292 } 2293 } 2294 2295 /* 2296 * Adjust the detection of RXSENSE according to whether we have a forced 2297 * connection mode enabled, or whether we have been disabled. There is 2298 * no point processing RXSENSE interrupts if we have a forced connection 2299 * state, or DRM has us disabled. 2300 * 2301 * We also disable rxsense interrupts when we think we're disconnected 2302 * to avoid floating TDMS signals giving false rxsense interrupts. 2303 * 2304 * Note: we still need to listen for HPD interrupts even when DRM has us 2305 * disabled so that we can detect a connect event. 2306 */ 2307 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2308 { 2309 if (hdmi->phy.ops->update_hpd) 2310 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2311 hdmi->force, hdmi->disabled, 2312 hdmi->rxsense); 2313 } 2314 2315 static enum drm_connector_status 2316 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2317 { 2318 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2319 connector); 2320 enum drm_connector_status result; 2321 2322 mutex_lock(&hdmi->mutex); 2323 hdmi->force = DRM_FORCE_UNSPECIFIED; 2324 dw_hdmi_update_power(hdmi); 2325 dw_hdmi_update_phy_mask(hdmi); 2326 mutex_unlock(&hdmi->mutex); 2327 2328 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2329 2330 mutex_lock(&hdmi->mutex); 2331 if (result != hdmi->last_connector_result) { 2332 dev_dbg(hdmi->dev, "read_hpd result: %d", result); 2333 handle_plugged_change(hdmi, 2334 result == connector_status_connected); 2335 hdmi->last_connector_result = result; 2336 } 2337 mutex_unlock(&hdmi->mutex); 2338 2339 return result; 2340 } 2341 2342 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2343 { 2344 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2345 connector); 2346 struct edid *edid; 2347 int ret = 0; 2348 2349 if (!hdmi->ddc) 2350 return 0; 2351 2352 edid = drm_get_edid(connector, hdmi->ddc); 2353 if (edid) { 2354 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2355 edid->width_cm, edid->height_cm); 2356 2357 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2358 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2359 drm_connector_update_edid_property(connector, edid); 2360 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2361 ret = drm_add_edid_modes(connector, edid); 2362 kfree(edid); 2363 } else { 2364 dev_dbg(hdmi->dev, "failed to get edid\n"); 2365 } 2366 2367 return ret; 2368 } 2369 2370 static bool hdr_metadata_equal(const struct drm_connector_state *old_state, 2371 const struct drm_connector_state *new_state) 2372 { 2373 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 2374 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 2375 2376 if (!old_blob || !new_blob) 2377 return old_blob == new_blob; 2378 2379 if (old_blob->length != new_blob->length) 2380 return false; 2381 2382 return !memcmp(old_blob->data, new_blob->data, old_blob->length); 2383 } 2384 2385 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2386 struct drm_atomic_state *state) 2387 { 2388 struct drm_connector_state *old_state = 2389 drm_atomic_get_old_connector_state(state, connector); 2390 struct drm_connector_state *new_state = 2391 drm_atomic_get_new_connector_state(state, connector); 2392 struct drm_crtc *crtc = new_state->crtc; 2393 struct drm_crtc_state *crtc_state; 2394 2395 if (!crtc) 2396 return 0; 2397 2398 if (!hdr_metadata_equal(old_state, new_state)) { 2399 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2400 if (IS_ERR(crtc_state)) 2401 return PTR_ERR(crtc_state); 2402 2403 crtc_state->mode_changed = true; 2404 } 2405 2406 return 0; 2407 } 2408 2409 static void dw_hdmi_connector_force(struct drm_connector *connector) 2410 { 2411 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2412 connector); 2413 2414 mutex_lock(&hdmi->mutex); 2415 hdmi->force = connector->force; 2416 dw_hdmi_update_power(hdmi); 2417 dw_hdmi_update_phy_mask(hdmi); 2418 mutex_unlock(&hdmi->mutex); 2419 } 2420 2421 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2422 .fill_modes = drm_helper_probe_single_connector_modes, 2423 .detect = dw_hdmi_connector_detect, 2424 .destroy = drm_connector_cleanup, 2425 .force = dw_hdmi_connector_force, 2426 .reset = drm_atomic_helper_connector_reset, 2427 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2428 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2429 }; 2430 2431 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2432 .get_modes = dw_hdmi_connector_get_modes, 2433 .atomic_check = dw_hdmi_connector_atomic_check, 2434 }; 2435 2436 /* 2437 * Possible output formats : 2438 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2439 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2440 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2441 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2442 * - MEDIA_BUS_FMT_YUV16_1X48, 2443 * - MEDIA_BUS_FMT_RGB161616_1X48, 2444 * - MEDIA_BUS_FMT_UYVY12_1X24, 2445 * - MEDIA_BUS_FMT_YUV12_1X36, 2446 * - MEDIA_BUS_FMT_RGB121212_1X36, 2447 * - MEDIA_BUS_FMT_UYVY10_1X20, 2448 * - MEDIA_BUS_FMT_YUV10_1X30, 2449 * - MEDIA_BUS_FMT_RGB101010_1X30, 2450 * - MEDIA_BUS_FMT_UYVY8_1X16, 2451 * - MEDIA_BUS_FMT_YUV8_1X24, 2452 * - MEDIA_BUS_FMT_RGB888_1X24, 2453 */ 2454 2455 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2456 #define MAX_OUTPUT_SEL_FORMATS 11 2457 2458 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2459 struct drm_bridge_state *bridge_state, 2460 struct drm_crtc_state *crtc_state, 2461 struct drm_connector_state *conn_state, 2462 unsigned int *num_output_fmts) 2463 { 2464 struct drm_connector *conn = conn_state->connector; 2465 struct drm_display_info *info = &conn->display_info; 2466 struct drm_display_mode *mode = &crtc_state->mode; 2467 u8 max_bpc = conn_state->max_requested_bpc; 2468 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2469 (info->color_formats & DRM_COLOR_FORMAT_YCRCB420); 2470 u32 *output_fmts; 2471 unsigned int i = 0; 2472 2473 *num_output_fmts = 0; 2474 2475 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2476 GFP_KERNEL); 2477 if (!output_fmts) 2478 return NULL; 2479 2480 /* If dw-hdmi is the only bridge, avoid negociating with ourselves */ 2481 if (list_is_singular(&bridge->encoder->bridge_chain)) { 2482 *num_output_fmts = 1; 2483 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2484 2485 return output_fmts; 2486 } 2487 2488 /* 2489 * If the current mode enforces 4:2:0, force the output but format 2490 * to 4:2:0 and do not add the YUV422/444/RGB formats 2491 */ 2492 if (conn->ycbcr_420_allowed && 2493 (drm_mode_is_420_only(info, mode) || 2494 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2495 2496 /* Order bus formats from 16bit to 8bit if supported */ 2497 if (max_bpc >= 16 && info->bpc == 16 && 2498 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2499 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2500 2501 if (max_bpc >= 12 && info->bpc >= 12 && 2502 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2503 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2504 2505 if (max_bpc >= 10 && info->bpc >= 10 && 2506 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2507 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2508 2509 /* Default 8bit fallback */ 2510 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2511 2512 *num_output_fmts = i; 2513 2514 return output_fmts; 2515 } 2516 2517 /* 2518 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2519 * if supported. In any case the default RGB888 format is added 2520 */ 2521 2522 if (max_bpc >= 16 && info->bpc == 16) { 2523 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2524 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2525 2526 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2527 } 2528 2529 if (max_bpc >= 12 && info->bpc >= 12) { 2530 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 2531 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2532 2533 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2534 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2535 2536 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2537 } 2538 2539 if (max_bpc >= 10 && info->bpc >= 10) { 2540 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 2541 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2542 2543 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2544 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2545 2546 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2547 } 2548 2549 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 2550 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2551 2552 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 2553 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2554 2555 /* Default 8bit RGB fallback */ 2556 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2557 2558 *num_output_fmts = i; 2559 2560 return output_fmts; 2561 } 2562 2563 /* 2564 * Possible input formats : 2565 * - MEDIA_BUS_FMT_RGB888_1X24 2566 * - MEDIA_BUS_FMT_YUV8_1X24 2567 * - MEDIA_BUS_FMT_UYVY8_1X16 2568 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2569 * - MEDIA_BUS_FMT_RGB101010_1X30 2570 * - MEDIA_BUS_FMT_YUV10_1X30 2571 * - MEDIA_BUS_FMT_UYVY10_1X20 2572 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2573 * - MEDIA_BUS_FMT_RGB121212_1X36 2574 * - MEDIA_BUS_FMT_YUV12_1X36 2575 * - MEDIA_BUS_FMT_UYVY12_1X24 2576 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2577 * - MEDIA_BUS_FMT_RGB161616_1X48 2578 * - MEDIA_BUS_FMT_YUV16_1X48 2579 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2580 */ 2581 2582 /* Can return a maximum of 3 possible input formats for an output format */ 2583 #define MAX_INPUT_SEL_FORMATS 3 2584 2585 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2586 struct drm_bridge_state *bridge_state, 2587 struct drm_crtc_state *crtc_state, 2588 struct drm_connector_state *conn_state, 2589 u32 output_fmt, 2590 unsigned int *num_input_fmts) 2591 { 2592 u32 *input_fmts; 2593 unsigned int i = 0; 2594 2595 *num_input_fmts = 0; 2596 2597 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2598 GFP_KERNEL); 2599 if (!input_fmts) 2600 return NULL; 2601 2602 switch (output_fmt) { 2603 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2604 case MEDIA_BUS_FMT_FIXED: 2605 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2606 break; 2607 /* 8bit */ 2608 case MEDIA_BUS_FMT_RGB888_1X24: 2609 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2610 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2611 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2612 break; 2613 case MEDIA_BUS_FMT_YUV8_1X24: 2614 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2615 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2616 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2617 break; 2618 case MEDIA_BUS_FMT_UYVY8_1X16: 2619 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2620 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2621 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2622 break; 2623 2624 /* 10bit */ 2625 case MEDIA_BUS_FMT_RGB101010_1X30: 2626 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2627 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2628 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2629 break; 2630 case MEDIA_BUS_FMT_YUV10_1X30: 2631 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2632 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2633 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2634 break; 2635 case MEDIA_BUS_FMT_UYVY10_1X20: 2636 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2637 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2638 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2639 break; 2640 2641 /* 12bit */ 2642 case MEDIA_BUS_FMT_RGB121212_1X36: 2643 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2644 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2645 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2646 break; 2647 case MEDIA_BUS_FMT_YUV12_1X36: 2648 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2649 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2650 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2651 break; 2652 case MEDIA_BUS_FMT_UYVY12_1X24: 2653 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2654 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2655 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2656 break; 2657 2658 /* 16bit */ 2659 case MEDIA_BUS_FMT_RGB161616_1X48: 2660 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2661 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2662 break; 2663 case MEDIA_BUS_FMT_YUV16_1X48: 2664 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2665 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2666 break; 2667 2668 /*YUV 4:2:0 */ 2669 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2670 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2671 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2672 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2673 input_fmts[i++] = output_fmt; 2674 break; 2675 } 2676 2677 *num_input_fmts = i; 2678 2679 if (*num_input_fmts == 0) { 2680 kfree(input_fmts); 2681 input_fmts = NULL; 2682 } 2683 2684 return input_fmts; 2685 } 2686 2687 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2688 struct drm_bridge_state *bridge_state, 2689 struct drm_crtc_state *crtc_state, 2690 struct drm_connector_state *conn_state) 2691 { 2692 struct dw_hdmi *hdmi = bridge->driver_private; 2693 2694 hdmi->hdmi_data.enc_out_bus_format = 2695 bridge_state->output_bus_cfg.format; 2696 2697 hdmi->hdmi_data.enc_in_bus_format = 2698 bridge_state->input_bus_cfg.format; 2699 2700 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2701 bridge_state->input_bus_cfg.format, 2702 bridge_state->output_bus_cfg.format); 2703 2704 return 0; 2705 } 2706 2707 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2708 enum drm_bridge_attach_flags flags) 2709 { 2710 struct dw_hdmi *hdmi = bridge->driver_private; 2711 struct drm_encoder *encoder = bridge->encoder; 2712 struct drm_connector *connector = &hdmi->connector; 2713 struct cec_connector_info conn_info; 2714 struct cec_notifier *notifier; 2715 2716 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 2717 DRM_ERROR("Fix bridge driver to make connector optional!"); 2718 return -EINVAL; 2719 } 2720 2721 connector->interlace_allowed = 1; 2722 connector->polled = DRM_CONNECTOR_POLL_HPD; 2723 2724 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2725 2726 drm_connector_init_with_ddc(bridge->dev, connector, 2727 &dw_hdmi_connector_funcs, 2728 DRM_MODE_CONNECTOR_HDMIA, 2729 hdmi->ddc); 2730 2731 /* 2732 * drm_connector_attach_max_bpc_property() requires the 2733 * connector to have a state. 2734 */ 2735 drm_atomic_helper_connector_reset(connector); 2736 2737 drm_connector_attach_max_bpc_property(connector, 8, 16); 2738 2739 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2740 drm_object_attach_property(&connector->base, 2741 connector->dev->mode_config.hdr_output_metadata_property, 0); 2742 2743 drm_connector_attach_encoder(connector, encoder); 2744 2745 cec_fill_conn_info_from_drm(&conn_info, connector); 2746 2747 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2748 if (!notifier) 2749 return -ENOMEM; 2750 2751 mutex_lock(&hdmi->cec_notifier_mutex); 2752 hdmi->cec_notifier = notifier; 2753 mutex_unlock(&hdmi->cec_notifier_mutex); 2754 2755 return 0; 2756 } 2757 2758 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2759 { 2760 struct dw_hdmi *hdmi = bridge->driver_private; 2761 2762 mutex_lock(&hdmi->cec_notifier_mutex); 2763 cec_notifier_conn_unregister(hdmi->cec_notifier); 2764 hdmi->cec_notifier = NULL; 2765 mutex_unlock(&hdmi->cec_notifier_mutex); 2766 } 2767 2768 static enum drm_mode_status 2769 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2770 const struct drm_display_mode *mode) 2771 { 2772 struct dw_hdmi *hdmi = bridge->driver_private; 2773 struct drm_connector *connector = &hdmi->connector; 2774 enum drm_mode_status mode_status = MODE_OK; 2775 2776 /* We don't support double-clocked modes */ 2777 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2778 return MODE_BAD; 2779 2780 if (hdmi->plat_data->mode_valid) 2781 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2782 2783 return mode_status; 2784 } 2785 2786 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2787 const struct drm_display_mode *orig_mode, 2788 const struct drm_display_mode *mode) 2789 { 2790 struct dw_hdmi *hdmi = bridge->driver_private; 2791 2792 mutex_lock(&hdmi->mutex); 2793 2794 /* Store the display mode for plugin/DKMS poweron events */ 2795 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2796 2797 mutex_unlock(&hdmi->mutex); 2798 } 2799 2800 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2801 { 2802 struct dw_hdmi *hdmi = bridge->driver_private; 2803 2804 mutex_lock(&hdmi->mutex); 2805 hdmi->disabled = true; 2806 dw_hdmi_update_power(hdmi); 2807 dw_hdmi_update_phy_mask(hdmi); 2808 mutex_unlock(&hdmi->mutex); 2809 } 2810 2811 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2812 { 2813 struct dw_hdmi *hdmi = bridge->driver_private; 2814 2815 mutex_lock(&hdmi->mutex); 2816 hdmi->disabled = false; 2817 dw_hdmi_update_power(hdmi); 2818 dw_hdmi_update_phy_mask(hdmi); 2819 mutex_unlock(&hdmi->mutex); 2820 } 2821 2822 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2823 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2824 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2825 .atomic_reset = drm_atomic_helper_bridge_reset, 2826 .attach = dw_hdmi_bridge_attach, 2827 .detach = dw_hdmi_bridge_detach, 2828 .atomic_check = dw_hdmi_bridge_atomic_check, 2829 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 2830 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 2831 .enable = dw_hdmi_bridge_enable, 2832 .disable = dw_hdmi_bridge_disable, 2833 .mode_set = dw_hdmi_bridge_mode_set, 2834 .mode_valid = dw_hdmi_bridge_mode_valid, 2835 }; 2836 2837 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2838 { 2839 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2840 unsigned int stat; 2841 2842 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2843 if (!stat) 2844 return IRQ_NONE; 2845 2846 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2847 2848 i2c->stat = stat; 2849 2850 complete(&i2c->cmp); 2851 2852 return IRQ_HANDLED; 2853 } 2854 2855 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2856 { 2857 struct dw_hdmi *hdmi = dev_id; 2858 u8 intr_stat; 2859 irqreturn_t ret = IRQ_NONE; 2860 2861 if (hdmi->i2c) 2862 ret = dw_hdmi_i2c_irq(hdmi); 2863 2864 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2865 if (intr_stat) { 2866 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2867 return IRQ_WAKE_THREAD; 2868 } 2869 2870 return ret; 2871 } 2872 2873 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2874 { 2875 mutex_lock(&hdmi->mutex); 2876 2877 if (!hdmi->force) { 2878 /* 2879 * If the RX sense status indicates we're disconnected, 2880 * clear the software rxsense status. 2881 */ 2882 if (!rx_sense) 2883 hdmi->rxsense = false; 2884 2885 /* 2886 * Only set the software rxsense status when both 2887 * rxsense and hpd indicates we're connected. 2888 * This avoids what seems to be bad behaviour in 2889 * at least iMX6S versions of the phy. 2890 */ 2891 if (hpd) 2892 hdmi->rxsense = true; 2893 2894 dw_hdmi_update_power(hdmi); 2895 dw_hdmi_update_phy_mask(hdmi); 2896 } 2897 mutex_unlock(&hdmi->mutex); 2898 } 2899 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2900 2901 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2902 { 2903 struct dw_hdmi *hdmi = dev_id; 2904 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2905 2906 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2907 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2908 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2909 2910 phy_pol_mask = 0; 2911 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2912 phy_pol_mask |= HDMI_PHY_HPD; 2913 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2914 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2915 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2916 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2917 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2918 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2919 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2920 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2921 2922 if (phy_pol_mask) 2923 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2924 2925 /* 2926 * RX sense tells us whether the TDMS transmitters are detecting 2927 * load - in other words, there's something listening on the 2928 * other end of the link. Use this to decide whether we should 2929 * power on the phy as HPD may be toggled by the sink to merely 2930 * ask the source to re-read the EDID. 2931 */ 2932 if (intr_stat & 2933 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2934 dw_hdmi_setup_rx_sense(hdmi, 2935 phy_stat & HDMI_PHY_HPD, 2936 phy_stat & HDMI_PHY_RX_SENSE); 2937 2938 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 2939 mutex_lock(&hdmi->cec_notifier_mutex); 2940 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 2941 mutex_unlock(&hdmi->cec_notifier_mutex); 2942 } 2943 } 2944 2945 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2946 dev_dbg(hdmi->dev, "EVENT=%s\n", 2947 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2948 if (hdmi->bridge.dev) 2949 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2950 } 2951 2952 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2953 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2954 HDMI_IH_MUTE_PHY_STAT0); 2955 2956 return IRQ_HANDLED; 2957 } 2958 2959 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2960 { 2961 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2962 .name = "DWC HDMI TX PHY", 2963 .gen = 1, 2964 }, { 2965 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2966 .name = "DWC MHL PHY + HEAC PHY", 2967 .gen = 2, 2968 .has_svsret = true, 2969 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2970 }, { 2971 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2972 .name = "DWC MHL PHY", 2973 .gen = 2, 2974 .has_svsret = true, 2975 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2976 }, { 2977 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2978 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2979 .gen = 2, 2980 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2981 }, { 2982 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2983 .name = "DWC HDMI 3D TX PHY", 2984 .gen = 2, 2985 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2986 }, { 2987 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2988 .name = "DWC HDMI 2.0 TX PHY", 2989 .gen = 2, 2990 .has_svsret = true, 2991 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2992 }, { 2993 .type = DW_HDMI_PHY_VENDOR_PHY, 2994 .name = "Vendor PHY", 2995 } 2996 }; 2997 2998 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2999 { 3000 unsigned int i; 3001 u8 phy_type; 3002 3003 phy_type = hdmi->plat_data->phy_force_vendor ? 3004 DW_HDMI_PHY_VENDOR_PHY : 3005 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3006 3007 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3008 /* Vendor PHYs require support from the glue layer. */ 3009 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3010 dev_err(hdmi->dev, 3011 "Vendor HDMI PHY not supported by glue layer\n"); 3012 return -ENODEV; 3013 } 3014 3015 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3016 hdmi->phy.data = hdmi->plat_data->phy_data; 3017 hdmi->phy.name = hdmi->plat_data->phy_name; 3018 return 0; 3019 } 3020 3021 /* Synopsys PHYs are handled internally. */ 3022 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3023 if (dw_hdmi_phys[i].type == phy_type) { 3024 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3025 hdmi->phy.name = dw_hdmi_phys[i].name; 3026 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3027 3028 if (!dw_hdmi_phys[i].configure && 3029 !hdmi->plat_data->configure_phy) { 3030 dev_err(hdmi->dev, "%s requires platform support\n", 3031 hdmi->phy.name); 3032 return -ENODEV; 3033 } 3034 3035 return 0; 3036 } 3037 } 3038 3039 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3040 return -ENODEV; 3041 } 3042 3043 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3044 { 3045 mutex_lock(&hdmi->mutex); 3046 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3047 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3048 mutex_unlock(&hdmi->mutex); 3049 } 3050 3051 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3052 { 3053 mutex_lock(&hdmi->mutex); 3054 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3055 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3056 mutex_unlock(&hdmi->mutex); 3057 } 3058 3059 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3060 .write = hdmi_writeb, 3061 .read = hdmi_readb, 3062 .enable = dw_hdmi_cec_enable, 3063 .disable = dw_hdmi_cec_disable, 3064 }; 3065 3066 static const struct regmap_config hdmi_regmap_8bit_config = { 3067 .reg_bits = 32, 3068 .val_bits = 8, 3069 .reg_stride = 1, 3070 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3071 }; 3072 3073 static const struct regmap_config hdmi_regmap_32bit_config = { 3074 .reg_bits = 32, 3075 .val_bits = 32, 3076 .reg_stride = 4, 3077 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3078 }; 3079 3080 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3081 { 3082 initialize_hdmi_ih_mutes(hdmi); 3083 3084 /* 3085 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3086 * Even if we are using a separate i2c adapter doing this doesn't 3087 * hurt. 3088 */ 3089 dw_hdmi_i2c_init(hdmi); 3090 3091 if (hdmi->phy.ops->setup_hpd) 3092 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3093 } 3094 3095 static struct dw_hdmi * 3096 __dw_hdmi_probe(struct platform_device *pdev, 3097 const struct dw_hdmi_plat_data *plat_data) 3098 { 3099 struct device *dev = &pdev->dev; 3100 struct device_node *np = dev->of_node; 3101 struct platform_device_info pdevinfo; 3102 struct device_node *ddc_node; 3103 struct dw_hdmi_cec_data cec; 3104 struct dw_hdmi *hdmi; 3105 struct resource *iores = NULL; 3106 int irq; 3107 int ret; 3108 u32 val = 1; 3109 u8 prod_id0; 3110 u8 prod_id1; 3111 u8 config0; 3112 u8 config3; 3113 3114 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 3115 if (!hdmi) 3116 return ERR_PTR(-ENOMEM); 3117 3118 hdmi->plat_data = plat_data; 3119 hdmi->dev = dev; 3120 hdmi->sample_rate = 48000; 3121 hdmi->disabled = true; 3122 hdmi->rxsense = true; 3123 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3124 hdmi->mc_clkdis = 0x7f; 3125 hdmi->last_connector_result = connector_status_disconnected; 3126 3127 mutex_init(&hdmi->mutex); 3128 mutex_init(&hdmi->audio_mutex); 3129 mutex_init(&hdmi->cec_notifier_mutex); 3130 spin_lock_init(&hdmi->audio_lock); 3131 3132 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3133 if (ddc_node) { 3134 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3135 of_node_put(ddc_node); 3136 if (!hdmi->ddc) { 3137 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3138 return ERR_PTR(-EPROBE_DEFER); 3139 } 3140 3141 } else { 3142 dev_dbg(hdmi->dev, "no ddc property found\n"); 3143 } 3144 3145 if (!plat_data->regm) { 3146 const struct regmap_config *reg_config; 3147 3148 of_property_read_u32(np, "reg-io-width", &val); 3149 switch (val) { 3150 case 4: 3151 reg_config = &hdmi_regmap_32bit_config; 3152 hdmi->reg_shift = 2; 3153 break; 3154 case 1: 3155 reg_config = &hdmi_regmap_8bit_config; 3156 break; 3157 default: 3158 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3159 return ERR_PTR(-EINVAL); 3160 } 3161 3162 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3163 hdmi->regs = devm_ioremap_resource(dev, iores); 3164 if (IS_ERR(hdmi->regs)) { 3165 ret = PTR_ERR(hdmi->regs); 3166 goto err_res; 3167 } 3168 3169 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3170 if (IS_ERR(hdmi->regm)) { 3171 dev_err(dev, "Failed to configure regmap\n"); 3172 ret = PTR_ERR(hdmi->regm); 3173 goto err_res; 3174 } 3175 } else { 3176 hdmi->regm = plat_data->regm; 3177 } 3178 3179 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 3180 if (IS_ERR(hdmi->isfr_clk)) { 3181 ret = PTR_ERR(hdmi->isfr_clk); 3182 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3183 goto err_res; 3184 } 3185 3186 ret = clk_prepare_enable(hdmi->isfr_clk); 3187 if (ret) { 3188 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 3189 goto err_res; 3190 } 3191 3192 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 3193 if (IS_ERR(hdmi->iahb_clk)) { 3194 ret = PTR_ERR(hdmi->iahb_clk); 3195 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3196 goto err_isfr; 3197 } 3198 3199 ret = clk_prepare_enable(hdmi->iahb_clk); 3200 if (ret) { 3201 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 3202 goto err_isfr; 3203 } 3204 3205 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 3206 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 3207 hdmi->cec_clk = NULL; 3208 } else if (IS_ERR(hdmi->cec_clk)) { 3209 ret = PTR_ERR(hdmi->cec_clk); 3210 if (ret != -EPROBE_DEFER) 3211 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3212 ret); 3213 3214 hdmi->cec_clk = NULL; 3215 goto err_iahb; 3216 } else { 3217 ret = clk_prepare_enable(hdmi->cec_clk); 3218 if (ret) { 3219 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 3220 ret); 3221 goto err_iahb; 3222 } 3223 } 3224 3225 /* Product and revision IDs */ 3226 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3227 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3228 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3229 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3230 3231 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3232 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3233 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3234 hdmi->version, prod_id0, prod_id1); 3235 ret = -ENODEV; 3236 goto err_iahb; 3237 } 3238 3239 ret = dw_hdmi_detect_phy(hdmi); 3240 if (ret < 0) 3241 goto err_iahb; 3242 3243 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3244 hdmi->version >> 12, hdmi->version & 0xfff, 3245 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3246 hdmi->phy.name); 3247 3248 dw_hdmi_init_hw(hdmi); 3249 3250 irq = platform_get_irq(pdev, 0); 3251 if (irq < 0) { 3252 ret = irq; 3253 goto err_iahb; 3254 } 3255 3256 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3257 dw_hdmi_irq, IRQF_SHARED, 3258 dev_name(dev), hdmi); 3259 if (ret) 3260 goto err_iahb; 3261 3262 /* 3263 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3264 * N and cts values before enabling phy 3265 */ 3266 hdmi_init_clk_regenerator(hdmi); 3267 3268 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3269 if (!hdmi->ddc) { 3270 /* Look for (optional) stuff related to unwedging */ 3271 hdmi->pinctrl = devm_pinctrl_get(dev); 3272 if (!IS_ERR(hdmi->pinctrl)) { 3273 hdmi->unwedge_state = 3274 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3275 hdmi->default_state = 3276 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3277 3278 if (IS_ERR(hdmi->default_state) || 3279 IS_ERR(hdmi->unwedge_state)) { 3280 if (!IS_ERR(hdmi->unwedge_state)) 3281 dev_warn(dev, 3282 "Unwedge requires default pinctrl\n"); 3283 hdmi->default_state = NULL; 3284 hdmi->unwedge_state = NULL; 3285 } 3286 } 3287 3288 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3289 if (IS_ERR(hdmi->ddc)) 3290 hdmi->ddc = NULL; 3291 } 3292 3293 hdmi->bridge.driver_private = hdmi; 3294 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 3295 #ifdef CONFIG_OF 3296 hdmi->bridge.of_node = pdev->dev.of_node; 3297 #endif 3298 3299 if (hdmi->version >= 0x200a) 3300 hdmi->connector.ycbcr_420_allowed = 3301 hdmi->plat_data->ycbcr_420_allowed; 3302 else 3303 hdmi->connector.ycbcr_420_allowed = false; 3304 3305 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3306 pdevinfo.parent = dev; 3307 pdevinfo.id = PLATFORM_DEVID_AUTO; 3308 3309 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3310 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3311 3312 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3313 struct dw_hdmi_audio_data audio; 3314 3315 audio.phys = iores->start; 3316 audio.base = hdmi->regs; 3317 audio.irq = irq; 3318 audio.hdmi = hdmi; 3319 audio.eld = hdmi->connector.eld; 3320 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3321 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3322 3323 pdevinfo.name = "dw-hdmi-ahb-audio"; 3324 pdevinfo.data = &audio; 3325 pdevinfo.size_data = sizeof(audio); 3326 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3327 hdmi->audio = platform_device_register_full(&pdevinfo); 3328 } else if (config0 & HDMI_CONFIG0_I2S) { 3329 struct dw_hdmi_i2s_audio_data audio; 3330 3331 audio.hdmi = hdmi; 3332 audio.eld = hdmi->connector.eld; 3333 audio.write = hdmi_writeb; 3334 audio.read = hdmi_readb; 3335 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3336 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3337 3338 pdevinfo.name = "dw-hdmi-i2s-audio"; 3339 pdevinfo.data = &audio; 3340 pdevinfo.size_data = sizeof(audio); 3341 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3342 hdmi->audio = platform_device_register_full(&pdevinfo); 3343 } 3344 3345 if (config0 & HDMI_CONFIG0_CEC) { 3346 cec.hdmi = hdmi; 3347 cec.ops = &dw_hdmi_cec_ops; 3348 cec.irq = irq; 3349 3350 pdevinfo.name = "dw-hdmi-cec"; 3351 pdevinfo.data = &cec; 3352 pdevinfo.size_data = sizeof(cec); 3353 pdevinfo.dma_mask = 0; 3354 3355 hdmi->cec = platform_device_register_full(&pdevinfo); 3356 } 3357 3358 return hdmi; 3359 3360 err_iahb: 3361 if (hdmi->i2c) { 3362 i2c_del_adapter(&hdmi->i2c->adap); 3363 hdmi->ddc = NULL; 3364 } 3365 3366 clk_disable_unprepare(hdmi->iahb_clk); 3367 if (hdmi->cec_clk) 3368 clk_disable_unprepare(hdmi->cec_clk); 3369 err_isfr: 3370 clk_disable_unprepare(hdmi->isfr_clk); 3371 err_res: 3372 i2c_put_adapter(hdmi->ddc); 3373 3374 return ERR_PTR(ret); 3375 } 3376 3377 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 3378 { 3379 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3380 platform_device_unregister(hdmi->audio); 3381 if (!IS_ERR(hdmi->cec)) 3382 platform_device_unregister(hdmi->cec); 3383 3384 /* Disable all interrupts */ 3385 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3386 3387 clk_disable_unprepare(hdmi->iahb_clk); 3388 clk_disable_unprepare(hdmi->isfr_clk); 3389 if (hdmi->cec_clk) 3390 clk_disable_unprepare(hdmi->cec_clk); 3391 3392 if (hdmi->i2c) 3393 i2c_del_adapter(&hdmi->i2c->adap); 3394 else 3395 i2c_put_adapter(hdmi->ddc); 3396 } 3397 3398 /* ----------------------------------------------------------------------------- 3399 * Probe/remove API, used from platforms based on the DRM bridge API. 3400 */ 3401 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3402 const struct dw_hdmi_plat_data *plat_data) 3403 { 3404 struct dw_hdmi *hdmi; 3405 3406 hdmi = __dw_hdmi_probe(pdev, plat_data); 3407 if (IS_ERR(hdmi)) 3408 return hdmi; 3409 3410 drm_bridge_add(&hdmi->bridge); 3411 3412 return hdmi; 3413 } 3414 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3415 3416 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3417 { 3418 drm_bridge_remove(&hdmi->bridge); 3419 3420 __dw_hdmi_remove(hdmi); 3421 } 3422 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3423 3424 /* ----------------------------------------------------------------------------- 3425 * Bind/unbind API, used from platforms based on the component framework. 3426 */ 3427 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3428 struct drm_encoder *encoder, 3429 const struct dw_hdmi_plat_data *plat_data) 3430 { 3431 struct dw_hdmi *hdmi; 3432 int ret; 3433 3434 hdmi = __dw_hdmi_probe(pdev, plat_data); 3435 if (IS_ERR(hdmi)) 3436 return hdmi; 3437 3438 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3439 if (ret) { 3440 dw_hdmi_remove(hdmi); 3441 DRM_ERROR("Failed to initialize bridge with drm\n"); 3442 return ERR_PTR(ret); 3443 } 3444 3445 return hdmi; 3446 } 3447 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3448 3449 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3450 { 3451 __dw_hdmi_remove(hdmi); 3452 } 3453 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3454 3455 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3456 { 3457 dw_hdmi_init_hw(hdmi); 3458 } 3459 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3460 3461 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3462 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3463 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3464 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3465 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3466 MODULE_LICENSE("GPL"); 3467 MODULE_ALIAS("platform:dw-hdmi"); 3468