1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/kvm_host.h> 15 16 #include <asm/debug-monitors.h> 17 #include <asm/esr.h> 18 #include <asm/kvm_arm.h> 19 #include <asm/kvm_hyp.h> 20 #include <asm/ptrace.h> 21 #include <asm/cputype.h> 22 #include <asm/virt.h> 23 24 unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num); 25 unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu); 26 void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v); 27 28 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 29 void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr); 30 31 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 32 void kvm_inject_vabt(struct kvm_vcpu *vcpu); 33 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); 34 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); 35 void kvm_inject_undef32(struct kvm_vcpu *vcpu); 36 void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr); 37 void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr); 38 39 static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 40 { 41 return !(vcpu->arch.hcr_el2 & HCR_RW); 42 } 43 44 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 45 { 46 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 47 if (is_kernel_in_hyp_mode()) 48 vcpu->arch.hcr_el2 |= HCR_E2H; 49 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) { 50 /* route synchronous external abort exceptions to EL2 */ 51 vcpu->arch.hcr_el2 |= HCR_TEA; 52 /* trap error record accesses */ 53 vcpu->arch.hcr_el2 |= HCR_TERR; 54 } 55 56 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { 57 vcpu->arch.hcr_el2 |= HCR_FWB; 58 } else { 59 /* 60 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 61 * get set in SCTLR_EL1 such that we can detect when the guest 62 * MMU gets turned on and do the necessary cache maintenance 63 * then. 64 */ 65 vcpu->arch.hcr_el2 |= HCR_TVM; 66 } 67 68 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) 69 vcpu->arch.hcr_el2 &= ~HCR_RW; 70 71 /* 72 * TID3: trap feature register accesses that we virtualise. 73 * For now this is conditional, since no AArch32 feature regs 74 * are currently virtualised. 75 */ 76 if (!vcpu_el1_is_32bit(vcpu)) 77 vcpu->arch.hcr_el2 |= HCR_TID3; 78 79 if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || 80 vcpu_el1_is_32bit(vcpu)) 81 vcpu->arch.hcr_el2 |= HCR_TID2; 82 } 83 84 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 85 { 86 return (unsigned long *)&vcpu->arch.hcr_el2; 87 } 88 89 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 90 { 91 vcpu->arch.hcr_el2 &= ~HCR_TWE; 92 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count)) 93 vcpu->arch.hcr_el2 &= ~HCR_TWI; 94 else 95 vcpu->arch.hcr_el2 |= HCR_TWI; 96 } 97 98 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 99 { 100 vcpu->arch.hcr_el2 |= HCR_TWE; 101 vcpu->arch.hcr_el2 |= HCR_TWI; 102 } 103 104 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu) 105 { 106 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK); 107 } 108 109 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu) 110 { 111 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK); 112 } 113 114 static inline void vcpu_ptrauth_setup_lazy(struct kvm_vcpu *vcpu) 115 { 116 if (vcpu_has_ptrauth(vcpu)) 117 vcpu_ptrauth_disable(vcpu); 118 } 119 120 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 121 { 122 return vcpu->arch.vsesr_el2; 123 } 124 125 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 126 { 127 vcpu->arch.vsesr_el2 = vsesr; 128 } 129 130 static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 131 { 132 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc; 133 } 134 135 static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu) 136 { 137 return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1; 138 } 139 140 static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu) 141 { 142 if (vcpu->arch.sysregs_loaded_on_cpu) 143 return read_sysreg_el1(SYS_ELR); 144 else 145 return *__vcpu_elr_el1(vcpu); 146 } 147 148 static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v) 149 { 150 if (vcpu->arch.sysregs_loaded_on_cpu) 151 write_sysreg_el1(v, SYS_ELR); 152 else 153 *__vcpu_elr_el1(vcpu) = v; 154 } 155 156 static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 157 { 158 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate; 159 } 160 161 static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 162 { 163 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 164 } 165 166 static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 167 { 168 if (vcpu_mode_is_32bit(vcpu)) 169 return kvm_condition_valid32(vcpu); 170 171 return true; 172 } 173 174 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 175 { 176 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 177 } 178 179 /* 180 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 181 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 182 * AArch32 with banked registers. 183 */ 184 static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 185 u8 reg_num) 186 { 187 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num]; 188 } 189 190 static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 191 unsigned long val) 192 { 193 if (reg_num != 31) 194 vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val; 195 } 196 197 static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu) 198 { 199 if (vcpu_mode_is_32bit(vcpu)) 200 return vcpu_read_spsr32(vcpu); 201 202 if (vcpu->arch.sysregs_loaded_on_cpu) 203 return read_sysreg_el1(SYS_SPSR); 204 else 205 return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1]; 206 } 207 208 static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) 209 { 210 if (vcpu_mode_is_32bit(vcpu)) { 211 vcpu_write_spsr32(vcpu, v); 212 return; 213 } 214 215 if (vcpu->arch.sysregs_loaded_on_cpu) 216 write_sysreg_el1(v, SYS_SPSR); 217 else 218 vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v; 219 } 220 221 /* 222 * The layout of SPSR for an AArch32 state is different when observed from an 223 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 224 * view given an AArch64 view. 225 * 226 * In ARM DDI 0487E.a see: 227 * 228 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 229 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 230 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 231 * 232 * Which show the following differences: 233 * 234 * | Bit | AA64 | AA32 | Notes | 235 * +-----+------+------+-----------------------------| 236 * | 24 | DIT | J | J is RES0 in ARMv8 | 237 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 238 * 239 * ... and all other bits are (currently) common. 240 */ 241 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 242 { 243 const unsigned long overlap = BIT(24) | BIT(21); 244 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 245 246 spsr &= ~overlap; 247 248 spsr |= dit << 21; 249 250 return spsr; 251 } 252 253 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 254 { 255 u32 mode; 256 257 if (vcpu_mode_is_32bit(vcpu)) { 258 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 259 return mode > PSR_AA32_MODE_USR; 260 } 261 262 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 263 264 return mode != PSR_MODE_EL0t; 265 } 266 267 static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu) 268 { 269 return vcpu->arch.fault.esr_el2; 270 } 271 272 static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 273 { 274 u32 esr = kvm_vcpu_get_hsr(vcpu); 275 276 if (esr & ESR_ELx_CV) 277 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 278 279 return -1; 280 } 281 282 static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 283 { 284 return vcpu->arch.fault.far_el2; 285 } 286 287 static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 288 { 289 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; 290 } 291 292 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 293 { 294 return vcpu->arch.fault.disr_el1; 295 } 296 297 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 298 { 299 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK; 300 } 301 302 static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 303 { 304 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV); 305 } 306 307 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 308 { 309 return kvm_vcpu_get_hsr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 310 } 311 312 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 313 { 314 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE); 315 } 316 317 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 318 { 319 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF); 320 } 321 322 static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 323 { 324 return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 325 } 326 327 static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu) 328 { 329 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW); 330 } 331 332 static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 333 { 334 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) || 335 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */ 336 } 337 338 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 339 { 340 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM); 341 } 342 343 static inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 344 { 345 return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 346 } 347 348 /* This one is not specific to Data Abort */ 349 static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 350 { 351 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL); 352 } 353 354 static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 355 { 356 return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu)); 357 } 358 359 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 360 { 361 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 362 } 363 364 static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 365 { 366 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC; 367 } 368 369 static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu) 370 { 371 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE; 372 } 373 374 static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu) 375 { 376 switch (kvm_vcpu_trap_get_fault(vcpu)) { 377 case FSC_SEA: 378 case FSC_SEA_TTW0: 379 case FSC_SEA_TTW1: 380 case FSC_SEA_TTW2: 381 case FSC_SEA_TTW3: 382 case FSC_SECC: 383 case FSC_SECC_TTW0: 384 case FSC_SECC_TTW1: 385 case FSC_SECC_TTW2: 386 case FSC_SECC_TTW3: 387 return true; 388 default: 389 return false; 390 } 391 } 392 393 static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 394 { 395 u32 esr = kvm_vcpu_get_hsr(vcpu); 396 return ESR_ELx_SYS64_ISS_RT(esr); 397 } 398 399 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 400 { 401 if (kvm_vcpu_trap_is_iabt(vcpu)) 402 return false; 403 404 return kvm_vcpu_dabt_iswrite(vcpu); 405 } 406 407 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 408 { 409 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 410 } 411 412 static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu) 413 { 414 return vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG; 415 } 416 417 static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu, 418 bool flag) 419 { 420 if (flag) 421 vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG; 422 else 423 vcpu->arch.workaround_flags &= ~VCPU_WORKAROUND_2_FLAG; 424 } 425 426 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 427 { 428 if (vcpu_mode_is_32bit(vcpu)) { 429 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 430 } else { 431 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 432 sctlr |= (1 << 25); 433 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); 434 } 435 } 436 437 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 438 { 439 if (vcpu_mode_is_32bit(vcpu)) 440 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 441 442 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25)); 443 } 444 445 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 446 unsigned long data, 447 unsigned int len) 448 { 449 if (kvm_vcpu_is_be(vcpu)) { 450 switch (len) { 451 case 1: 452 return data & 0xff; 453 case 2: 454 return be16_to_cpu(data & 0xffff); 455 case 4: 456 return be32_to_cpu(data & 0xffffffff); 457 default: 458 return be64_to_cpu(data); 459 } 460 } else { 461 switch (len) { 462 case 1: 463 return data & 0xff; 464 case 2: 465 return le16_to_cpu(data & 0xffff); 466 case 4: 467 return le32_to_cpu(data & 0xffffffff); 468 default: 469 return le64_to_cpu(data); 470 } 471 } 472 473 return data; /* Leave LE untouched */ 474 } 475 476 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 477 unsigned long data, 478 unsigned int len) 479 { 480 if (kvm_vcpu_is_be(vcpu)) { 481 switch (len) { 482 case 1: 483 return data & 0xff; 484 case 2: 485 return cpu_to_be16(data & 0xffff); 486 case 4: 487 return cpu_to_be32(data & 0xffffffff); 488 default: 489 return cpu_to_be64(data); 490 } 491 } else { 492 switch (len) { 493 case 1: 494 return data & 0xff; 495 case 2: 496 return cpu_to_le16(data & 0xffff); 497 case 4: 498 return cpu_to_le32(data & 0xffffffff); 499 default: 500 return cpu_to_le64(data); 501 } 502 } 503 504 return data; /* Leave LE untouched */ 505 } 506 507 static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr) 508 { 509 if (vcpu_mode_is_32bit(vcpu)) 510 kvm_skip_instr32(vcpu, is_wide_instr); 511 else 512 *vcpu_pc(vcpu) += 4; 513 514 /* advance the singlestep state machine */ 515 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS; 516 } 517 518 /* 519 * Skip an instruction which has been emulated at hyp while most guest sysregs 520 * are live. 521 */ 522 static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu) 523 { 524 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR); 525 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR); 526 527 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); 528 529 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR); 530 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR); 531 } 532 533 #endif /* __ARM64_KVM_EMULATE_H__ */ 534