1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of_gpio.h> 16 #include <linux/bitfield.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/regulator/of_regulator.h> 19 #include <linux/regulator/driver.h> 20 #include <linux/regulator/consumer.h> 21 #include <dt-bindings/net/qca-ar803x.h> 22 23 #define AT803X_SPECIFIC_STATUS 0x11 24 #define AT803X_SS_SPEED_MASK (3 << 14) 25 #define AT803X_SS_SPEED_1000 (2 << 14) 26 #define AT803X_SS_SPEED_100 (1 << 14) 27 #define AT803X_SS_SPEED_10 (0 << 14) 28 #define AT803X_SS_DUPLEX BIT(13) 29 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 30 #define AT803X_SS_MDIX BIT(6) 31 32 #define AT803X_INTR_ENABLE 0x12 33 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 34 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 35 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 36 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 37 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 38 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 39 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 40 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 41 #define AT803X_INTR_ENABLE_WOL BIT(0) 42 43 #define AT803X_INTR_STATUS 0x13 44 45 #define AT803X_SMART_SPEED 0x14 46 #define AT803X_LED_CONTROL 0x18 47 48 #define AT803X_DEVICE_ADDR 0x03 49 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 50 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 51 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 52 #define AT803X_REG_CHIP_CONFIG 0x1f 53 #define AT803X_BT_BX_REG_SEL 0x8000 54 55 #define AT803X_DEBUG_ADDR 0x1D 56 #define AT803X_DEBUG_DATA 0x1E 57 58 #define AT803X_MODE_CFG_MASK 0x0F 59 #define AT803X_MODE_CFG_SGMII 0x01 60 61 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 62 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 63 64 #define AT803X_DEBUG_REG_0 0x00 65 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 66 67 #define AT803X_DEBUG_REG_5 0x05 68 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 69 70 #define AT803X_DEBUG_REG_1F 0x1F 71 #define AT803X_DEBUG_PLL_ON BIT(2) 72 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 73 74 /* AT803x supports either the XTAL input pad, an internal PLL or the 75 * DSP as clock reference for the clock output pad. The XTAL reference 76 * is only used for 25 MHz output, all other frequencies need the PLL. 77 * The DSP as a clock reference is used in synchronous ethernet 78 * applications. 79 * 80 * By default the PLL is only enabled if there is a link. Otherwise 81 * the PHY will go into low power state and disabled the PLL. You can 82 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 83 * enabled. 84 */ 85 #define AT803X_MMD7_CLK25M 0x8016 86 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 87 #define AT803X_CLK_OUT_25MHZ_XTAL 0 88 #define AT803X_CLK_OUT_25MHZ_DSP 1 89 #define AT803X_CLK_OUT_50MHZ_PLL 2 90 #define AT803X_CLK_OUT_50MHZ_DSP 3 91 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 92 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 93 #define AT803X_CLK_OUT_125MHZ_PLL 6 94 #define AT803X_CLK_OUT_125MHZ_DSP 7 95 96 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 97 * but doesn't support choosing between XTAL/PLL and DSP. 98 */ 99 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 100 101 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 102 #define AT803X_CLK_OUT_STRENGTH_FULL 0 103 #define AT803X_CLK_OUT_STRENGTH_HALF 1 104 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 105 106 #define ATH9331_PHY_ID 0x004dd041 107 #define ATH8030_PHY_ID 0x004dd076 108 #define ATH8031_PHY_ID 0x004dd074 109 #define ATH8035_PHY_ID 0x004dd072 110 #define AT803X_PHY_ID_MASK 0xffffffef 111 112 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 113 MODULE_AUTHOR("Matus Ujhelyi"); 114 MODULE_LICENSE("GPL"); 115 116 struct at803x_priv { 117 int flags; 118 #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ 119 u16 clk_25m_reg; 120 u16 clk_25m_mask; 121 struct regulator_dev *vddio_rdev; 122 struct regulator_dev *vddh_rdev; 123 struct regulator *vddio; 124 }; 125 126 struct at803x_context { 127 u16 bmcr; 128 u16 advertise; 129 u16 control1000; 130 u16 int_enable; 131 u16 smart_speed; 132 u16 led_control; 133 }; 134 135 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 136 { 137 int ret; 138 139 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 140 if (ret < 0) 141 return ret; 142 143 return phy_read(phydev, AT803X_DEBUG_DATA); 144 } 145 146 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 147 u16 clear, u16 set) 148 { 149 u16 val; 150 int ret; 151 152 ret = at803x_debug_reg_read(phydev, reg); 153 if (ret < 0) 154 return ret; 155 156 val = ret & 0xffff; 157 val &= ~clear; 158 val |= set; 159 160 return phy_write(phydev, AT803X_DEBUG_DATA, val); 161 } 162 163 static int at803x_enable_rx_delay(struct phy_device *phydev) 164 { 165 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 166 AT803X_DEBUG_RX_CLK_DLY_EN); 167 } 168 169 static int at803x_enable_tx_delay(struct phy_device *phydev) 170 { 171 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 172 AT803X_DEBUG_TX_CLK_DLY_EN); 173 } 174 175 static int at803x_disable_rx_delay(struct phy_device *phydev) 176 { 177 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 178 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 179 } 180 181 static int at803x_disable_tx_delay(struct phy_device *phydev) 182 { 183 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 184 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 185 } 186 187 /* save relevant PHY registers to private copy */ 188 static void at803x_context_save(struct phy_device *phydev, 189 struct at803x_context *context) 190 { 191 context->bmcr = phy_read(phydev, MII_BMCR); 192 context->advertise = phy_read(phydev, MII_ADVERTISE); 193 context->control1000 = phy_read(phydev, MII_CTRL1000); 194 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 195 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 196 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 197 } 198 199 /* restore relevant PHY registers from private copy */ 200 static void at803x_context_restore(struct phy_device *phydev, 201 const struct at803x_context *context) 202 { 203 phy_write(phydev, MII_BMCR, context->bmcr); 204 phy_write(phydev, MII_ADVERTISE, context->advertise); 205 phy_write(phydev, MII_CTRL1000, context->control1000); 206 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 207 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 208 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 209 } 210 211 static int at803x_set_wol(struct phy_device *phydev, 212 struct ethtool_wolinfo *wol) 213 { 214 struct net_device *ndev = phydev->attached_dev; 215 const u8 *mac; 216 int ret; 217 u32 value; 218 unsigned int i, offsets[] = { 219 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 220 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 221 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 222 }; 223 224 if (!ndev) 225 return -ENODEV; 226 227 if (wol->wolopts & WAKE_MAGIC) { 228 mac = (const u8 *) ndev->dev_addr; 229 230 if (!is_valid_ether_addr(mac)) 231 return -EINVAL; 232 233 for (i = 0; i < 3; i++) 234 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 235 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 236 237 value = phy_read(phydev, AT803X_INTR_ENABLE); 238 value |= AT803X_INTR_ENABLE_WOL; 239 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 240 if (ret) 241 return ret; 242 value = phy_read(phydev, AT803X_INTR_STATUS); 243 } else { 244 value = phy_read(phydev, AT803X_INTR_ENABLE); 245 value &= (~AT803X_INTR_ENABLE_WOL); 246 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 247 if (ret) 248 return ret; 249 value = phy_read(phydev, AT803X_INTR_STATUS); 250 } 251 252 return ret; 253 } 254 255 static void at803x_get_wol(struct phy_device *phydev, 256 struct ethtool_wolinfo *wol) 257 { 258 u32 value; 259 260 wol->supported = WAKE_MAGIC; 261 wol->wolopts = 0; 262 263 value = phy_read(phydev, AT803X_INTR_ENABLE); 264 if (value & AT803X_INTR_ENABLE_WOL) 265 wol->wolopts |= WAKE_MAGIC; 266 } 267 268 static int at803x_suspend(struct phy_device *phydev) 269 { 270 int value; 271 int wol_enabled; 272 273 value = phy_read(phydev, AT803X_INTR_ENABLE); 274 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 275 276 if (wol_enabled) 277 value = BMCR_ISOLATE; 278 else 279 value = BMCR_PDOWN; 280 281 phy_modify(phydev, MII_BMCR, 0, value); 282 283 return 0; 284 } 285 286 static int at803x_resume(struct phy_device *phydev) 287 { 288 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 289 } 290 291 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 292 unsigned int selector) 293 { 294 struct phy_device *phydev = rdev_get_drvdata(rdev); 295 296 if (selector) 297 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 298 0, AT803X_DEBUG_RGMII_1V8); 299 else 300 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 301 AT803X_DEBUG_RGMII_1V8, 0); 302 } 303 304 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 305 { 306 struct phy_device *phydev = rdev_get_drvdata(rdev); 307 int val; 308 309 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 310 if (val < 0) 311 return val; 312 313 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 314 } 315 316 static struct regulator_ops vddio_regulator_ops = { 317 .list_voltage = regulator_list_voltage_table, 318 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 319 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 320 }; 321 322 static const unsigned int vddio_voltage_table[] = { 323 1500000, 324 1800000, 325 }; 326 327 static const struct regulator_desc vddio_desc = { 328 .name = "vddio", 329 .of_match = of_match_ptr("vddio-regulator"), 330 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 331 .volt_table = vddio_voltage_table, 332 .ops = &vddio_regulator_ops, 333 .type = REGULATOR_VOLTAGE, 334 .owner = THIS_MODULE, 335 }; 336 337 static struct regulator_ops vddh_regulator_ops = { 338 }; 339 340 static const struct regulator_desc vddh_desc = { 341 .name = "vddh", 342 .of_match = of_match_ptr("vddh-regulator"), 343 .n_voltages = 1, 344 .fixed_uV = 2500000, 345 .ops = &vddh_regulator_ops, 346 .type = REGULATOR_VOLTAGE, 347 .owner = THIS_MODULE, 348 }; 349 350 static int at8031_register_regulators(struct phy_device *phydev) 351 { 352 struct at803x_priv *priv = phydev->priv; 353 struct device *dev = &phydev->mdio.dev; 354 struct regulator_config config = { }; 355 356 config.dev = dev; 357 config.driver_data = phydev; 358 359 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 360 if (IS_ERR(priv->vddio_rdev)) { 361 phydev_err(phydev, "failed to register VDDIO regulator\n"); 362 return PTR_ERR(priv->vddio_rdev); 363 } 364 365 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 366 if (IS_ERR(priv->vddh_rdev)) { 367 phydev_err(phydev, "failed to register VDDH regulator\n"); 368 return PTR_ERR(priv->vddh_rdev); 369 } 370 371 return 0; 372 } 373 374 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) 375 { 376 return (phydev->phy_id & phydev->drv->phy_id_mask) 377 == (phy_id & phydev->drv->phy_id_mask); 378 } 379 380 static int at803x_parse_dt(struct phy_device *phydev) 381 { 382 struct device_node *node = phydev->mdio.dev.of_node; 383 struct at803x_priv *priv = phydev->priv; 384 unsigned int sel, mask; 385 u32 freq, strength; 386 int ret; 387 388 if (!IS_ENABLED(CONFIG_OF_MDIO)) 389 return 0; 390 391 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 392 if (!ret) { 393 mask = AT803X_CLK_OUT_MASK; 394 switch (freq) { 395 case 25000000: 396 sel = AT803X_CLK_OUT_25MHZ_XTAL; 397 break; 398 case 50000000: 399 sel = AT803X_CLK_OUT_50MHZ_PLL; 400 break; 401 case 62500000: 402 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 403 break; 404 case 125000000: 405 sel = AT803X_CLK_OUT_125MHZ_PLL; 406 break; 407 default: 408 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 409 return -EINVAL; 410 } 411 412 priv->clk_25m_reg |= FIELD_PREP(mask, sel); 413 priv->clk_25m_mask |= mask; 414 415 /* Fixup for the AR8030/AR8035. This chip has another mask and 416 * doesn't support the DSP reference. Eg. the lowest bit of the 417 * mask. The upper two bits select the same frequencies. Mask 418 * the lowest bit here. 419 * 420 * Warning: 421 * There was no datasheet for the AR8030 available so this is 422 * just a guess. But the AR8035 is listed as pin compatible 423 * to the AR8030 so there might be a good chance it works on 424 * the AR8030 too. 425 */ 426 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || 427 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { 428 priv->clk_25m_reg &= ~AT8035_CLK_OUT_MASK; 429 priv->clk_25m_mask &= ~AT8035_CLK_OUT_MASK; 430 } 431 } 432 433 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 434 if (!ret) { 435 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 436 switch (strength) { 437 case AR803X_STRENGTH_FULL: 438 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 439 break; 440 case AR803X_STRENGTH_HALF: 441 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 442 break; 443 case AR803X_STRENGTH_QUARTER: 444 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 445 break; 446 default: 447 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 448 return -EINVAL; 449 } 450 } 451 452 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 453 * options. 454 */ 455 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 456 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 457 priv->flags |= AT803X_KEEP_PLL_ENABLED; 458 459 ret = at8031_register_regulators(phydev); 460 if (ret < 0) 461 return ret; 462 463 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 464 "vddio"); 465 if (IS_ERR(priv->vddio)) { 466 phydev_err(phydev, "failed to get VDDIO regulator\n"); 467 return PTR_ERR(priv->vddio); 468 } 469 470 ret = regulator_enable(priv->vddio); 471 if (ret < 0) 472 return ret; 473 } 474 475 return 0; 476 } 477 478 static int at803x_probe(struct phy_device *phydev) 479 { 480 struct device *dev = &phydev->mdio.dev; 481 struct at803x_priv *priv; 482 483 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 484 if (!priv) 485 return -ENOMEM; 486 487 phydev->priv = priv; 488 489 return at803x_parse_dt(phydev); 490 } 491 492 static void at803x_remove(struct phy_device *phydev) 493 { 494 struct at803x_priv *priv = phydev->priv; 495 496 if (priv->vddio) 497 regulator_disable(priv->vddio); 498 } 499 500 static int at803x_clk_out_config(struct phy_device *phydev) 501 { 502 struct at803x_priv *priv = phydev->priv; 503 int val; 504 505 if (!priv->clk_25m_mask) 506 return 0; 507 508 val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M); 509 if (val < 0) 510 return val; 511 512 val &= ~priv->clk_25m_mask; 513 val |= priv->clk_25m_reg; 514 515 return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val); 516 } 517 518 static int at8031_pll_config(struct phy_device *phydev) 519 { 520 struct at803x_priv *priv = phydev->priv; 521 522 /* The default after hardware reset is PLL OFF. After a soft reset, the 523 * values are retained. 524 */ 525 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 526 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 527 0, AT803X_DEBUG_PLL_ON); 528 else 529 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 530 AT803X_DEBUG_PLL_ON, 0); 531 } 532 533 static int at803x_config_init(struct phy_device *phydev) 534 { 535 int ret; 536 537 /* The RX and TX delay default is: 538 * after HW reset: RX delay enabled and TX delay disabled 539 * after SW reset: RX delay enabled, while TX delay retains the 540 * value before reset. 541 */ 542 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 543 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 544 ret = at803x_enable_rx_delay(phydev); 545 else 546 ret = at803x_disable_rx_delay(phydev); 547 if (ret < 0) 548 return ret; 549 550 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 551 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 552 ret = at803x_enable_tx_delay(phydev); 553 else 554 ret = at803x_disable_tx_delay(phydev); 555 if (ret < 0) 556 return ret; 557 558 ret = at803x_clk_out_config(phydev); 559 if (ret < 0) 560 return ret; 561 562 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 563 ret = at8031_pll_config(phydev); 564 if (ret < 0) 565 return ret; 566 } 567 568 return 0; 569 } 570 571 static int at803x_ack_interrupt(struct phy_device *phydev) 572 { 573 int err; 574 575 err = phy_read(phydev, AT803X_INTR_STATUS); 576 577 return (err < 0) ? err : 0; 578 } 579 580 static int at803x_config_intr(struct phy_device *phydev) 581 { 582 int err; 583 int value; 584 585 value = phy_read(phydev, AT803X_INTR_ENABLE); 586 587 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 588 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 589 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 590 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 591 value |= AT803X_INTR_ENABLE_LINK_FAIL; 592 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 593 594 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 595 } 596 else 597 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 598 599 return err; 600 } 601 602 static void at803x_link_change_notify(struct phy_device *phydev) 603 { 604 /* 605 * Conduct a hardware reset for AT8030 every time a link loss is 606 * signalled. This is necessary to circumvent a hardware bug that 607 * occurs when the cable is unplugged while TX packets are pending 608 * in the FIFO. In such cases, the FIFO enters an error mode it 609 * cannot recover from by software. 610 */ 611 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 612 struct at803x_context context; 613 614 at803x_context_save(phydev, &context); 615 616 phy_device_reset(phydev, 1); 617 msleep(1); 618 phy_device_reset(phydev, 0); 619 msleep(1); 620 621 at803x_context_restore(phydev, &context); 622 623 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 624 } 625 } 626 627 static int at803x_aneg_done(struct phy_device *phydev) 628 { 629 int ccr; 630 631 int aneg_done = genphy_aneg_done(phydev); 632 if (aneg_done != BMSR_ANEGCOMPLETE) 633 return aneg_done; 634 635 /* 636 * in SGMII mode, if copper side autoneg is successful, 637 * also check SGMII side autoneg result 638 */ 639 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 640 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII) 641 return aneg_done; 642 643 /* switch to SGMII/fiber page */ 644 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL); 645 646 /* check if the SGMII link is OK. */ 647 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { 648 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); 649 aneg_done = 0; 650 } 651 /* switch back to copper page */ 652 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); 653 654 return aneg_done; 655 } 656 657 static int at803x_read_status(struct phy_device *phydev) 658 { 659 int ss, err, old_link = phydev->link; 660 661 /* Update the link, but return if there was an error */ 662 err = genphy_update_link(phydev); 663 if (err) 664 return err; 665 666 /* why bother the PHY if nothing can have changed */ 667 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 668 return 0; 669 670 phydev->speed = SPEED_UNKNOWN; 671 phydev->duplex = DUPLEX_UNKNOWN; 672 phydev->pause = 0; 673 phydev->asym_pause = 0; 674 675 err = genphy_read_lpa(phydev); 676 if (err < 0) 677 return err; 678 679 /* Read the AT8035 PHY-Specific Status register, which indicates the 680 * speed and duplex that the PHY is actually using, irrespective of 681 * whether we are in autoneg mode or not. 682 */ 683 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 684 if (ss < 0) 685 return ss; 686 687 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 688 switch (ss & AT803X_SS_SPEED_MASK) { 689 case AT803X_SS_SPEED_10: 690 phydev->speed = SPEED_10; 691 break; 692 case AT803X_SS_SPEED_100: 693 phydev->speed = SPEED_100; 694 break; 695 case AT803X_SS_SPEED_1000: 696 phydev->speed = SPEED_1000; 697 break; 698 } 699 if (ss & AT803X_SS_DUPLEX) 700 phydev->duplex = DUPLEX_FULL; 701 else 702 phydev->duplex = DUPLEX_HALF; 703 if (ss & AT803X_SS_MDIX) 704 phydev->mdix = ETH_TP_MDI_X; 705 else 706 phydev->mdix = ETH_TP_MDI; 707 } 708 709 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 710 phy_resolve_aneg_pause(phydev); 711 712 return 0; 713 } 714 715 static struct phy_driver at803x_driver[] = { 716 { 717 /* Qualcomm Atheros AR8035 */ 718 .phy_id = ATH8035_PHY_ID, 719 .name = "Qualcomm Atheros AR8035", 720 .phy_id_mask = AT803X_PHY_ID_MASK, 721 .probe = at803x_probe, 722 .remove = at803x_remove, 723 .config_init = at803x_config_init, 724 .set_wol = at803x_set_wol, 725 .get_wol = at803x_get_wol, 726 .suspend = at803x_suspend, 727 .resume = at803x_resume, 728 /* PHY_GBIT_FEATURES */ 729 .read_status = at803x_read_status, 730 .ack_interrupt = at803x_ack_interrupt, 731 .config_intr = at803x_config_intr, 732 }, { 733 /* Qualcomm Atheros AR8030 */ 734 .phy_id = ATH8030_PHY_ID, 735 .name = "Qualcomm Atheros AR8030", 736 .phy_id_mask = AT803X_PHY_ID_MASK, 737 .probe = at803x_probe, 738 .remove = at803x_remove, 739 .config_init = at803x_config_init, 740 .link_change_notify = at803x_link_change_notify, 741 .set_wol = at803x_set_wol, 742 .get_wol = at803x_get_wol, 743 .suspend = at803x_suspend, 744 .resume = at803x_resume, 745 /* PHY_BASIC_FEATURES */ 746 .ack_interrupt = at803x_ack_interrupt, 747 .config_intr = at803x_config_intr, 748 }, { 749 /* Qualcomm Atheros AR8031/AR8033 */ 750 .phy_id = ATH8031_PHY_ID, 751 .name = "Qualcomm Atheros AR8031/AR8033", 752 .phy_id_mask = AT803X_PHY_ID_MASK, 753 .probe = at803x_probe, 754 .remove = at803x_remove, 755 .config_init = at803x_config_init, 756 .set_wol = at803x_set_wol, 757 .get_wol = at803x_get_wol, 758 .suspend = at803x_suspend, 759 .resume = at803x_resume, 760 /* PHY_GBIT_FEATURES */ 761 .read_status = at803x_read_status, 762 .aneg_done = at803x_aneg_done, 763 .ack_interrupt = &at803x_ack_interrupt, 764 .config_intr = &at803x_config_intr, 765 }, { 766 /* ATHEROS AR9331 */ 767 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 768 .name = "Qualcomm Atheros AR9331 built-in PHY", 769 .suspend = at803x_suspend, 770 .resume = at803x_resume, 771 /* PHY_BASIC_FEATURES */ 772 .ack_interrupt = &at803x_ack_interrupt, 773 .config_intr = &at803x_config_intr, 774 } }; 775 776 module_phy_driver(at803x_driver); 777 778 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 779 { ATH8030_PHY_ID, AT803X_PHY_ID_MASK }, 780 { ATH8031_PHY_ID, AT803X_PHY_ID_MASK }, 781 { ATH8035_PHY_ID, AT803X_PHY_ID_MASK }, 782 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 783 { } 784 }; 785 786 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 787