1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include "sdhci.h" 16 #include "sdhci-pci.h" 17 18 /* Genesys Logic extra registers */ 19 #define SDHCI_GLI_9750_WT 0x800 20 #define SDHCI_GLI_9750_WT_EN BIT(0) 21 #define GLI_9750_WT_EN_ON 0x1 22 #define GLI_9750_WT_EN_OFF 0x0 23 24 #define SDHCI_GLI_9750_DRIVING 0x860 25 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 26 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 27 #define GLI_9750_DRIVING_1_VALUE 0xFFF 28 #define GLI_9750_DRIVING_2_VALUE 0x3 29 #define SDHCI_GLI_9750_SEL_1 BIT(29) 30 #define SDHCI_GLI_9750_SEL_2 BIT(31) 31 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 32 33 #define SDHCI_GLI_9750_PLL 0x864 34 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 35 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 36 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 37 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 38 39 #define SDHCI_GLI_9750_SW_CTRL 0x874 40 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 41 #define GLI_9750_SW_CTRL_4_VALUE 0x3 42 43 #define SDHCI_GLI_9750_MISC 0x878 44 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 45 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 46 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 47 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 48 #define GLI_9750_MISC_RX_INV_ON 0x1 49 #define GLI_9750_MISC_RX_INV_OFF 0x0 50 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 51 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 52 53 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 54 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 55 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 56 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 57 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 58 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 59 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 60 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 61 62 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 63 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 64 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 65 66 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 67 68 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 69 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 70 71 #define PCIE_GLI_9763E_VHS 0x884 72 #define GLI_9763E_VHS_REV GENMASK(19, 16) 73 #define GLI_9763E_VHS_REV_R 0x0 74 #define GLI_9763E_VHS_REV_M 0x1 75 #define GLI_9763E_VHS_REV_W 0x2 76 #define PCIE_GLI_9763E_SCR 0x8E0 77 #define GLI_9763E_SCR_AXI_REQ BIT(9) 78 79 #define GLI_MAX_TUNING_LOOP 40 80 81 /* Genesys Logic chipset */ 82 static inline void gl9750_wt_on(struct sdhci_host *host) 83 { 84 u32 wt_value; 85 u32 wt_enable; 86 87 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 88 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 89 90 if (wt_enable == GLI_9750_WT_EN_ON) 91 return; 92 93 wt_value &= ~SDHCI_GLI_9750_WT_EN; 94 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 95 96 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 97 } 98 99 static inline void gl9750_wt_off(struct sdhci_host *host) 100 { 101 u32 wt_value; 102 u32 wt_enable; 103 104 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 105 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 106 107 if (wt_enable == GLI_9750_WT_EN_OFF) 108 return; 109 110 wt_value &= ~SDHCI_GLI_9750_WT_EN; 111 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 112 113 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 114 } 115 116 static void gli_set_9750(struct sdhci_host *host) 117 { 118 u32 driving_value; 119 u32 pll_value; 120 u32 sw_ctrl_value; 121 u32 misc_value; 122 u32 parameter_value; 123 u32 control_value; 124 u16 ctrl2; 125 126 gl9750_wt_on(host); 127 128 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 129 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 130 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 131 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 132 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 133 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 134 135 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 136 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 137 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 138 GLI_9750_DRIVING_1_VALUE); 139 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 140 GLI_9750_DRIVING_2_VALUE); 141 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 142 driving_value |= SDHCI_GLI_9750_SEL_2; 143 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 144 145 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 146 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 147 GLI_9750_SW_CTRL_4_VALUE); 148 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 149 150 /* reset the tuning flow after reinit and before starting tuning */ 151 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 152 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 153 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 154 GLI_9750_PLL_TX2_INV_VALUE); 155 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 156 GLI_9750_PLL_TX2_DLY_VALUE); 157 158 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 159 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 160 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 161 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 162 GLI_9750_MISC_TX1_INV_VALUE); 163 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 164 GLI_9750_MISC_RX_INV_VALUE); 165 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 166 GLI_9750_MISC_TX1_DLY_VALUE); 167 168 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 169 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 170 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 171 172 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 173 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 174 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 175 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 176 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 177 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 178 179 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 180 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 181 182 /* disable tuned clk */ 183 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 184 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 185 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 186 187 /* enable tuning parameters control */ 188 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 189 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 190 GLI_9750_TUNING_CONTROL_EN_ON); 191 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 192 193 /* write tuning parameters */ 194 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 195 196 /* disable tuning parameters control */ 197 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 198 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 199 GLI_9750_TUNING_CONTROL_EN_OFF); 200 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 201 202 /* clear tuned clk */ 203 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 204 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 205 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 206 207 gl9750_wt_off(host); 208 } 209 210 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 211 { 212 u32 misc_value; 213 214 gl9750_wt_on(host); 215 216 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 217 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 218 if (b) { 219 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 220 GLI_9750_MISC_RX_INV_ON); 221 } else { 222 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 223 GLI_9750_MISC_RX_INV_OFF); 224 } 225 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 226 227 gl9750_wt_off(host); 228 } 229 230 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 231 { 232 int i; 233 int rx_inv; 234 235 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 236 gli_set_9750_rx_inv(host, !!rx_inv); 237 sdhci_start_tuning(host); 238 239 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 240 u16 ctrl; 241 242 sdhci_send_tuning(host, opcode); 243 244 if (!host->tuning_done) { 245 sdhci_abort_tuning(host, opcode); 246 break; 247 } 248 249 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 250 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 251 if (ctrl & SDHCI_CTRL_TUNED_CLK) 252 return 0; /* Success! */ 253 break; 254 } 255 } 256 } 257 if (!host->tuning_done) { 258 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 259 mmc_hostname(host->mmc)); 260 return -ETIMEDOUT; 261 } 262 263 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 264 mmc_hostname(host->mmc)); 265 sdhci_reset_tuning(host); 266 267 return -EAGAIN; 268 } 269 270 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 271 { 272 host->mmc->retune_period = 0; 273 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 274 host->mmc->retune_period = host->tuning_count; 275 276 gli_set_9750(host); 277 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 278 sdhci_end_tuning(host); 279 280 return 0; 281 } 282 283 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 284 { 285 int ret; 286 287 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 288 PCI_IRQ_MSI | PCI_IRQ_MSIX); 289 if (ret < 0) { 290 pr_warn("%s: enable PCI MSI failed, error=%d\n", 291 mmc_hostname(slot->host->mmc), ret); 292 return; 293 } 294 295 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 296 } 297 298 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 299 { 300 struct sdhci_host *host = slot->host; 301 302 gli_pcie_enable_msi(slot); 303 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 304 sdhci_enable_v4_mode(host); 305 306 return 0; 307 } 308 309 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 310 { 311 struct sdhci_host *host = slot->host; 312 313 gli_pcie_enable_msi(slot); 314 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 315 sdhci_enable_v4_mode(host); 316 317 return 0; 318 } 319 320 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 321 { 322 /* 323 * According to Section 3.6.1 signal voltage switch procedure in 324 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 325 * follows: 326 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 327 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 328 * period. 329 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 330 * step (12). 331 * 332 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 333 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 334 */ 335 usleep_range(5000, 5500); 336 } 337 338 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 339 { 340 sdhci_reset(host, mask); 341 gli_set_9750(host); 342 } 343 344 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 345 { 346 u32 value; 347 348 value = readl(host->ioaddr + reg); 349 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 350 value |= 0xc8; 351 352 return value; 353 } 354 355 #ifdef CONFIG_PM_SLEEP 356 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 357 { 358 struct sdhci_pci_slot *slot = chip->slots[0]; 359 360 pci_free_irq_vectors(slot->chip->pdev); 361 gli_pcie_enable_msi(slot); 362 363 return sdhci_pci_resume_host(chip); 364 } 365 #endif 366 367 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 368 struct mmc_ios *ios) 369 { 370 struct sdhci_host *host = mmc_priv(mmc); 371 u32 val; 372 373 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 374 if (ios->enhanced_strobe) 375 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 376 else 377 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 378 379 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 380 } 381 382 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 383 unsigned int timing) 384 { 385 u16 ctrl_2; 386 387 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 388 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 389 if (timing == MMC_TIMING_MMC_HS200) 390 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 391 else if (timing == MMC_TIMING_MMC_HS) 392 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 393 else if (timing == MMC_TIMING_MMC_DDR52) 394 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 395 else if (timing == MMC_TIMING_MMC_HS400) 396 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 397 398 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 399 } 400 401 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 402 { 403 struct pci_dev *pdev = slot->chip->pdev; 404 u32 value; 405 406 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 407 value &= ~GLI_9763E_VHS_REV; 408 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 409 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 410 411 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 412 value |= GLI_9763E_SCR_AXI_REQ; 413 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 414 415 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 416 value &= ~GLI_9763E_VHS_REV; 417 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 418 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 419 } 420 421 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 422 { 423 struct sdhci_host *host = slot->host; 424 425 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 426 MMC_CAP_1_8V_DDR | 427 MMC_CAP_NONREMOVABLE; 428 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 429 MMC_CAP2_HS400_1_8V | 430 MMC_CAP2_HS400_ES | 431 MMC_CAP2_NO_SDIO | 432 MMC_CAP2_NO_SD; 433 gli_pcie_enable_msi(slot); 434 host->mmc_host_ops.hs400_enhanced_strobe = 435 gl9763e_hs400_enhanced_strobe; 436 gli_set_gl9763e(slot); 437 sdhci_enable_v4_mode(host); 438 439 return 0; 440 } 441 442 static const struct sdhci_ops sdhci_gl9755_ops = { 443 .set_clock = sdhci_set_clock, 444 .enable_dma = sdhci_pci_enable_dma, 445 .set_bus_width = sdhci_set_bus_width, 446 .reset = sdhci_reset, 447 .set_uhs_signaling = sdhci_set_uhs_signaling, 448 .voltage_switch = sdhci_gli_voltage_switch, 449 }; 450 451 const struct sdhci_pci_fixes sdhci_gl9755 = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 454 .probe_slot = gli_probe_slot_gl9755, 455 .ops = &sdhci_gl9755_ops, 456 #ifdef CONFIG_PM_SLEEP 457 .resume = sdhci_pci_gli_resume, 458 #endif 459 }; 460 461 static const struct sdhci_ops sdhci_gl9750_ops = { 462 .read_l = sdhci_gl9750_readl, 463 .set_clock = sdhci_set_clock, 464 .enable_dma = sdhci_pci_enable_dma, 465 .set_bus_width = sdhci_set_bus_width, 466 .reset = sdhci_gl9750_reset, 467 .set_uhs_signaling = sdhci_set_uhs_signaling, 468 .voltage_switch = sdhci_gli_voltage_switch, 469 .platform_execute_tuning = gl9750_execute_tuning, 470 }; 471 472 const struct sdhci_pci_fixes sdhci_gl9750 = { 473 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 474 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 475 .probe_slot = gli_probe_slot_gl9750, 476 .ops = &sdhci_gl9750_ops, 477 #ifdef CONFIG_PM_SLEEP 478 .resume = sdhci_pci_gli_resume, 479 #endif 480 }; 481 482 static const struct sdhci_ops sdhci_gl9763e_ops = { 483 .set_clock = sdhci_set_clock, 484 .enable_dma = sdhci_pci_enable_dma, 485 .set_bus_width = sdhci_set_bus_width, 486 .reset = sdhci_reset, 487 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 488 .voltage_switch = sdhci_gli_voltage_switch, 489 }; 490 491 const struct sdhci_pci_fixes sdhci_gl9763e = { 492 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 493 .probe_slot = gli_probe_slot_gl9763e, 494 .ops = &sdhci_gl9763e_ops, 495 #ifdef CONFIG_PM_SLEEP 496 .resume = sdhci_pci_gli_resume, 497 #endif 498 }; 499