1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include "sdhci.h" 16 #include "sdhci-pci.h" 17 18 /* Genesys Logic extra registers */ 19 #define SDHCI_GLI_9750_WT 0x800 20 #define SDHCI_GLI_9750_WT_EN BIT(0) 21 #define GLI_9750_WT_EN_ON 0x1 22 #define GLI_9750_WT_EN_OFF 0x0 23 24 #define SDHCI_GLI_9750_DRIVING 0x860 25 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 26 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 27 #define GLI_9750_DRIVING_1_VALUE 0xFFF 28 #define GLI_9750_DRIVING_2_VALUE 0x3 29 #define SDHCI_GLI_9750_SEL_1 BIT(29) 30 #define SDHCI_GLI_9750_SEL_2 BIT(31) 31 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 32 33 #define SDHCI_GLI_9750_PLL 0x864 34 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 35 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 36 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 37 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 38 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 39 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 40 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 41 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 42 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 43 44 #define SDHCI_GLI_9750_PLLSSC 0x86C 45 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 46 47 #define SDHCI_GLI_9750_SW_CTRL 0x874 48 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 49 #define GLI_9750_SW_CTRL_4_VALUE 0x3 50 51 #define SDHCI_GLI_9750_MISC 0x878 52 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 53 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 54 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 55 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 56 #define GLI_9750_MISC_RX_INV_ON 0x1 57 #define GLI_9750_MISC_RX_INV_OFF 0x0 58 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 59 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 60 61 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 62 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 63 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 64 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 65 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 66 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 67 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 68 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 69 70 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 71 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 72 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 73 74 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 75 76 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 77 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 78 79 #define PCIE_GLI_9763E_VHS 0x884 80 #define GLI_9763E_VHS_REV GENMASK(19, 16) 81 #define GLI_9763E_VHS_REV_R 0x0 82 #define GLI_9763E_VHS_REV_M 0x1 83 #define GLI_9763E_VHS_REV_W 0x2 84 #define PCIE_GLI_9763E_SCR 0x8E0 85 #define GLI_9763E_SCR_AXI_REQ BIT(9) 86 87 #define PCI_GLI_9755_WT 0x800 88 #define PCI_GLI_9755_WT_EN BIT(0) 89 #define GLI_9755_WT_EN_ON 0x1 90 #define GLI_9755_WT_EN_OFF 0x0 91 92 #define PCI_GLI_9755_PLL 0x64 93 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 94 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 95 #define PCI_GLI_9755_PLL_DIR BIT(15) 96 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 97 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 98 99 #define PCI_GLI_9755_PLLSSC 0x68 100 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 101 102 #define GLI_MAX_TUNING_LOOP 40 103 104 /* Genesys Logic chipset */ 105 static inline void gl9750_wt_on(struct sdhci_host *host) 106 { 107 u32 wt_value; 108 u32 wt_enable; 109 110 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 111 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 112 113 if (wt_enable == GLI_9750_WT_EN_ON) 114 return; 115 116 wt_value &= ~SDHCI_GLI_9750_WT_EN; 117 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 118 119 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 120 } 121 122 static inline void gl9750_wt_off(struct sdhci_host *host) 123 { 124 u32 wt_value; 125 u32 wt_enable; 126 127 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 128 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 129 130 if (wt_enable == GLI_9750_WT_EN_OFF) 131 return; 132 133 wt_value &= ~SDHCI_GLI_9750_WT_EN; 134 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 135 136 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 137 } 138 139 static void gli_set_9750(struct sdhci_host *host) 140 { 141 u32 driving_value; 142 u32 pll_value; 143 u32 sw_ctrl_value; 144 u32 misc_value; 145 u32 parameter_value; 146 u32 control_value; 147 u16 ctrl2; 148 149 gl9750_wt_on(host); 150 151 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 152 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 153 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 154 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 155 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 156 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 157 158 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 159 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 160 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 161 GLI_9750_DRIVING_1_VALUE); 162 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 163 GLI_9750_DRIVING_2_VALUE); 164 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 165 driving_value |= SDHCI_GLI_9750_SEL_2; 166 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 167 168 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 169 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 170 GLI_9750_SW_CTRL_4_VALUE); 171 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 172 173 /* reset the tuning flow after reinit and before starting tuning */ 174 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 175 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 176 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 177 GLI_9750_PLL_TX2_INV_VALUE); 178 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 179 GLI_9750_PLL_TX2_DLY_VALUE); 180 181 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 182 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 183 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 184 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 185 GLI_9750_MISC_TX1_INV_VALUE); 186 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 187 GLI_9750_MISC_RX_INV_VALUE); 188 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 189 GLI_9750_MISC_TX1_DLY_VALUE); 190 191 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 192 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 193 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 194 195 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 196 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 197 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 198 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 199 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 200 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 201 202 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 203 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 204 205 /* disable tuned clk */ 206 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 207 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 208 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 209 210 /* enable tuning parameters control */ 211 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 212 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 213 GLI_9750_TUNING_CONTROL_EN_ON); 214 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 215 216 /* write tuning parameters */ 217 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 218 219 /* disable tuning parameters control */ 220 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 221 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 222 GLI_9750_TUNING_CONTROL_EN_OFF); 223 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 224 225 /* clear tuned clk */ 226 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 227 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 228 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 229 230 gl9750_wt_off(host); 231 } 232 233 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 234 { 235 u32 misc_value; 236 237 gl9750_wt_on(host); 238 239 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 240 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 241 if (b) { 242 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 243 GLI_9750_MISC_RX_INV_ON); 244 } else { 245 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 246 GLI_9750_MISC_RX_INV_OFF); 247 } 248 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 249 250 gl9750_wt_off(host); 251 } 252 253 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 254 { 255 int i; 256 int rx_inv; 257 258 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 259 gli_set_9750_rx_inv(host, !!rx_inv); 260 sdhci_start_tuning(host); 261 262 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 263 u16 ctrl; 264 265 sdhci_send_tuning(host, opcode); 266 267 if (!host->tuning_done) { 268 sdhci_abort_tuning(host, opcode); 269 break; 270 } 271 272 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 273 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 274 if (ctrl & SDHCI_CTRL_TUNED_CLK) 275 return 0; /* Success! */ 276 break; 277 } 278 } 279 } 280 if (!host->tuning_done) { 281 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 282 mmc_hostname(host->mmc)); 283 return -ETIMEDOUT; 284 } 285 286 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 287 mmc_hostname(host->mmc)); 288 sdhci_reset_tuning(host); 289 290 return -EAGAIN; 291 } 292 293 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 294 { 295 host->mmc->retune_period = 0; 296 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 297 host->mmc->retune_period = host->tuning_count; 298 299 gli_set_9750(host); 300 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 301 sdhci_end_tuning(host); 302 303 return 0; 304 } 305 306 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 307 { 308 u32 pll; 309 310 gl9750_wt_on(host); 311 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 312 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 313 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 314 gl9750_wt_off(host); 315 } 316 317 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 318 { 319 u32 pll; 320 321 gl9750_wt_on(host); 322 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 323 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 324 SDHCI_GLI_9750_PLL_PDIV | 325 SDHCI_GLI_9750_PLL_DIR); 326 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 327 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 328 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 329 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 330 gl9750_wt_off(host); 331 332 /* wait for pll stable */ 333 mdelay(1); 334 } 335 336 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 337 { 338 u32 pll; 339 u32 ssc; 340 341 gl9750_wt_on(host); 342 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 343 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 344 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 345 SDHCI_GLI_9750_PLLSSC_EN); 346 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 347 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 348 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 349 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 350 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 351 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 352 gl9750_wt_off(host); 353 } 354 355 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 356 { 357 /* set pll to 205MHz and enable ssc */ 358 gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7); 359 gl9750_set_pll(host, 0x1, 0x246, 0x0); 360 } 361 362 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 363 { 364 struct mmc_ios *ios = &host->mmc->ios; 365 u16 clk; 366 367 host->mmc->actual_clock = 0; 368 369 gl9750_disable_ssc_pll(host); 370 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 371 372 if (clock == 0) 373 return; 374 375 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 376 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 377 host->mmc->actual_clock = 205000000; 378 gl9750_set_ssc_pll_205mhz(host); 379 } 380 381 sdhci_enable_clk(host, clk); 382 } 383 384 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 385 { 386 int ret; 387 388 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 389 PCI_IRQ_MSI | PCI_IRQ_MSIX); 390 if (ret < 0) { 391 pr_warn("%s: enable PCI MSI failed, error=%d\n", 392 mmc_hostname(slot->host->mmc), ret); 393 return; 394 } 395 396 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 397 } 398 399 static inline void gl9755_wt_on(struct pci_dev *pdev) 400 { 401 u32 wt_value; 402 u32 wt_enable; 403 404 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 405 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 406 407 if (wt_enable == GLI_9755_WT_EN_ON) 408 return; 409 410 wt_value &= ~PCI_GLI_9755_WT_EN; 411 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 412 413 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 414 } 415 416 static inline void gl9755_wt_off(struct pci_dev *pdev) 417 { 418 u32 wt_value; 419 u32 wt_enable; 420 421 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 422 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 423 424 if (wt_enable == GLI_9755_WT_EN_OFF) 425 return; 426 427 wt_value &= ~PCI_GLI_9755_WT_EN; 428 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 429 430 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 431 } 432 433 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 434 { 435 u32 pll; 436 437 gl9755_wt_on(pdev); 438 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 439 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 440 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 441 gl9755_wt_off(pdev); 442 } 443 444 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 445 { 446 u32 pll; 447 448 gl9755_wt_on(pdev); 449 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 450 pll &= ~(PCI_GLI_9755_PLL_LDIV | 451 PCI_GLI_9755_PLL_PDIV | 452 PCI_GLI_9755_PLL_DIR); 453 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 454 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 455 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 456 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 457 gl9755_wt_off(pdev); 458 459 /* wait for pll stable */ 460 mdelay(1); 461 } 462 463 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 464 { 465 u32 pll; 466 u32 ssc; 467 468 gl9755_wt_on(pdev); 469 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 470 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 471 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 472 PCI_GLI_9755_PLLSSC_EN); 473 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 474 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 475 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 476 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 477 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 478 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 479 gl9755_wt_off(pdev); 480 } 481 482 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 483 { 484 /* set pll to 205MHz and enable ssc */ 485 gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7); 486 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 487 } 488 489 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 490 { 491 struct sdhci_pci_slot *slot = sdhci_priv(host); 492 struct mmc_ios *ios = &host->mmc->ios; 493 struct pci_dev *pdev; 494 u16 clk; 495 496 pdev = slot->chip->pdev; 497 host->mmc->actual_clock = 0; 498 499 gl9755_disable_ssc_pll(pdev); 500 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 501 502 if (clock == 0) 503 return; 504 505 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 506 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 507 host->mmc->actual_clock = 205000000; 508 gl9755_set_ssc_pll_205mhz(pdev); 509 } 510 511 sdhci_enable_clk(host, clk); 512 } 513 514 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 515 { 516 struct sdhci_host *host = slot->host; 517 518 gli_pcie_enable_msi(slot); 519 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 520 sdhci_enable_v4_mode(host); 521 522 return 0; 523 } 524 525 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 526 { 527 struct sdhci_host *host = slot->host; 528 529 gli_pcie_enable_msi(slot); 530 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 531 sdhci_enable_v4_mode(host); 532 533 return 0; 534 } 535 536 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 537 { 538 /* 539 * According to Section 3.6.1 signal voltage switch procedure in 540 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 541 * follows: 542 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 543 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 544 * period. 545 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 546 * step (12). 547 * 548 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 549 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 550 */ 551 usleep_range(5000, 5500); 552 } 553 554 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 555 { 556 sdhci_reset(host, mask); 557 gli_set_9750(host); 558 } 559 560 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 561 { 562 u32 value; 563 564 value = readl(host->ioaddr + reg); 565 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 566 value |= 0xc8; 567 568 return value; 569 } 570 571 #ifdef CONFIG_PM_SLEEP 572 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 573 { 574 struct sdhci_pci_slot *slot = chip->slots[0]; 575 576 pci_free_irq_vectors(slot->chip->pdev); 577 gli_pcie_enable_msi(slot); 578 579 return sdhci_pci_resume_host(chip); 580 } 581 #endif 582 583 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 584 struct mmc_ios *ios) 585 { 586 struct sdhci_host *host = mmc_priv(mmc); 587 u32 val; 588 589 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 590 if (ios->enhanced_strobe) 591 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 592 else 593 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 594 595 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 596 } 597 598 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 599 unsigned int timing) 600 { 601 u16 ctrl_2; 602 603 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 604 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 605 if (timing == MMC_TIMING_MMC_HS200) 606 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 607 else if (timing == MMC_TIMING_MMC_HS) 608 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 609 else if (timing == MMC_TIMING_MMC_DDR52) 610 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 611 else if (timing == MMC_TIMING_MMC_HS400) 612 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 613 614 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 615 } 616 617 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 618 { 619 struct pci_dev *pdev = slot->chip->pdev; 620 u32 value; 621 622 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 623 value &= ~GLI_9763E_VHS_REV; 624 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 625 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 626 627 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 628 value |= GLI_9763E_SCR_AXI_REQ; 629 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 630 631 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 632 value &= ~GLI_9763E_VHS_REV; 633 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 634 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 635 } 636 637 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 638 { 639 struct sdhci_host *host = slot->host; 640 641 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 642 MMC_CAP_1_8V_DDR | 643 MMC_CAP_NONREMOVABLE; 644 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 645 MMC_CAP2_HS400_1_8V | 646 MMC_CAP2_HS400_ES | 647 MMC_CAP2_NO_SDIO | 648 MMC_CAP2_NO_SD; 649 gli_pcie_enable_msi(slot); 650 host->mmc_host_ops.hs400_enhanced_strobe = 651 gl9763e_hs400_enhanced_strobe; 652 gli_set_gl9763e(slot); 653 sdhci_enable_v4_mode(host); 654 655 return 0; 656 } 657 658 static const struct sdhci_ops sdhci_gl9755_ops = { 659 .set_clock = sdhci_gl9755_set_clock, 660 .enable_dma = sdhci_pci_enable_dma, 661 .set_bus_width = sdhci_set_bus_width, 662 .reset = sdhci_reset, 663 .set_uhs_signaling = sdhci_set_uhs_signaling, 664 .voltage_switch = sdhci_gli_voltage_switch, 665 }; 666 667 const struct sdhci_pci_fixes sdhci_gl9755 = { 668 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 669 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 670 .probe_slot = gli_probe_slot_gl9755, 671 .ops = &sdhci_gl9755_ops, 672 #ifdef CONFIG_PM_SLEEP 673 .resume = sdhci_pci_gli_resume, 674 #endif 675 }; 676 677 static const struct sdhci_ops sdhci_gl9750_ops = { 678 .read_l = sdhci_gl9750_readl, 679 .set_clock = sdhci_gl9750_set_clock, 680 .enable_dma = sdhci_pci_enable_dma, 681 .set_bus_width = sdhci_set_bus_width, 682 .reset = sdhci_gl9750_reset, 683 .set_uhs_signaling = sdhci_set_uhs_signaling, 684 .voltage_switch = sdhci_gli_voltage_switch, 685 .platform_execute_tuning = gl9750_execute_tuning, 686 }; 687 688 const struct sdhci_pci_fixes sdhci_gl9750 = { 689 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 690 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 691 .probe_slot = gli_probe_slot_gl9750, 692 .ops = &sdhci_gl9750_ops, 693 #ifdef CONFIG_PM_SLEEP 694 .resume = sdhci_pci_gli_resume, 695 #endif 696 }; 697 698 static const struct sdhci_ops sdhci_gl9763e_ops = { 699 .set_clock = sdhci_set_clock, 700 .enable_dma = sdhci_pci_enable_dma, 701 .set_bus_width = sdhci_set_bus_width, 702 .reset = sdhci_reset, 703 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 704 .voltage_switch = sdhci_gli_voltage_switch, 705 }; 706 707 const struct sdhci_pci_fixes sdhci_gl9763e = { 708 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 709 .probe_slot = gli_probe_slot_gl9763e, 710 .ops = &sdhci_gl9763e_ops, 711 #ifdef CONFIG_PM_SLEEP 712 .resume = sdhci_pci_gli_resume, 713 #endif 714 }; 715