1# SPDX-License-Identifier: GPL-2.0 2# 3# PCI Express Port Bus Configuration 4# 5config PCIEPORTBUS 6 bool "PCI Express Port Bus support" 7 help 8 This enables PCI Express Port Bus support. Users can then enable 9 support for Native Hot-Plug, Advanced Error Reporting, Power 10 Management Events, and Downstream Port Containment. 11 12# 13# Include service Kconfig here 14# 15config HOTPLUG_PCI_PCIE 16 bool "PCI Express Hotplug driver" 17 depends on HOTPLUG_PCI && PCIEPORTBUS 18 help 19 Say Y here if you have a motherboard that supports PCI Express Native 20 Hotplug 21 22 When in doubt, say N. 23 24config PCIEAER 25 bool "PCI Express Advanced Error Reporting support" 26 depends on PCIEPORTBUS 27 select RAS 28 default y 29 help 30 This enables PCI Express Root Port Advanced Error Reporting 31 (AER) driver support. Error reporting messages sent to Root 32 Port will be handled by PCI Express AER driver. 33 34config PCIEAER_INJECT 35 tristate "PCI Express error injection support" 36 depends on PCIEAER 37 select GENERIC_IRQ_INJECTION 38 help 39 This enables PCI Express Root Port Advanced Error Reporting 40 (AER) software error injector. 41 42 Debugging AER code is quite difficult because it is hard 43 to trigger various real hardware errors. Software-based 44 error injection can fake almost all kinds of errors with the 45 help of a user space helper tool aer-inject, which can be 46 gotten from: 47 http://www.kernel.org/pub/linux/utils/pci/aer-inject/ 48 49# 50# PCI Express ECRC 51# 52config PCIE_ECRC 53 bool "PCI Express ECRC settings control" 54 depends on PCIEAER 55 help 56 Used to override firmware/bios settings for PCI Express ECRC 57 (transaction layer end-to-end CRC checking). 58 59 When in doubt, say N. 60 61# 62# PCI Express ASPM 63# 64config PCIEASPM 65 bool "PCI Express ASPM control" if EXPERT 66 default y 67 help 68 This enables OS control over PCI Express ASPM (Active State 69 Power Management) and Clock Power Management. ASPM supports 70 state L0/L0s/L1. 71 72 ASPM is initially set up by the firmware. With this option enabled, 73 Linux can modify this state in order to disable ASPM on known-bad 74 hardware or configurations and enable it when known-safe. 75 76 ASPM can be disabled or enabled at runtime via 77 /sys/module/pcie_aspm/parameters/policy 78 79 When in doubt, say Y. 80 81choice 82 prompt "Default ASPM policy" 83 default PCIEASPM_DEFAULT 84 depends on PCIEASPM 85 86config PCIEASPM_DEFAULT 87 bool "BIOS default" 88 depends on PCIEASPM 89 help 90 Use the BIOS defaults for PCI Express ASPM. 91 92config PCIEASPM_POWERSAVE 93 bool "Powersave" 94 depends on PCIEASPM 95 help 96 Enable PCI Express ASPM L0s and L1 where possible, even if the 97 BIOS did not. 98 99config PCIEASPM_POWER_SUPERSAVE 100 bool "Power Supersave" 101 depends on PCIEASPM 102 help 103 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 104 possible. This would result in higher power savings while staying in L1 105 where the components support it. 106 107config PCIEASPM_PERFORMANCE 108 bool "Performance" 109 depends on PCIEASPM 110 help 111 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. 112endchoice 113 114config PCIE_PME 115 def_bool y 116 depends on PCIEPORTBUS && PM 117 118config PCIE_DPC 119 bool "PCI Express Downstream Port Containment support" 120 depends on PCIEPORTBUS && PCIEAER 121 help 122 This enables PCI Express Downstream Port Containment (DPC) 123 driver support. DPC events from Root and Downstream ports 124 will be handled by the DPC driver. If your system doesn't 125 have this capability or you do not want to use this feature, 126 it is safe to answer N. 127 128config PCIE_PTM 129 bool "PCI Express Precision Time Measurement support" 130 help 131 This enables PCI Express Precision Time Measurement (PTM) 132 support. 133 134 This is only useful if you have devices that support PTM, but it 135 is safe to enable even if you don't. 136 137config PCIE_BW 138 bool "PCI Express Bandwidth Change Notification" 139 depends on PCIEPORTBUS 140 help 141 This enables PCI Express Bandwidth Change Notification. If 142 you know link width or rate changes occur only to correct 143 unreliable links, you may answer Y. 144 145config PCIE_EDR 146 bool "PCI Express Error Disconnect Recover support" 147 depends on PCIE_DPC && ACPI 148 help 149 This option adds Error Disconnect Recover support as specified 150 in the Downstream Port Containment Related Enhancements ECN to 151 the PCI Firmware Specification r3.2. Enable this if you want to 152 support hybrid DPC model which uses both firmware and OS to 153 implement DPC. 154