1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_display.h" 8 #include "intel_display_types.h" 9 #include "intel_dp_mst.h" 10 #include "intel_tc.h" 11 12 static const char *tc_port_mode_name(enum tc_port_mode mode) 13 { 14 static const char * const names[] = { 15 [TC_PORT_TBT_ALT] = "tbt-alt", 16 [TC_PORT_DP_ALT] = "dp-alt", 17 [TC_PORT_LEGACY] = "legacy", 18 }; 19 20 if (WARN_ON(mode >= ARRAY_SIZE(names))) 21 mode = TC_PORT_TBT_ALT; 22 23 return names[mode]; 24 } 25 26 static void 27 tc_port_load_fia_params(struct drm_i915_private *i915, 28 struct intel_digital_port *dig_port) 29 { 30 enum port port = dig_port->base.port; 31 enum tc_port tc_port = intel_port_to_tc(i915, port); 32 u32 modular_fia; 33 34 if (INTEL_INFO(i915)->display.has_modular_fia) { 35 modular_fia = intel_uncore_read(&i915->uncore, 36 PORT_TX_DFLEXDPSP(FIA1)); 37 modular_fia &= MODULAR_FIA_MASK; 38 } else { 39 modular_fia = 0; 40 } 41 42 /* 43 * Each Modular FIA instance houses 2 TC ports. In SOC that has more 44 * than two TC ports, there are multiple instances of Modular FIA. 45 */ 46 if (modular_fia) { 47 dig_port->tc_phy_fia = tc_port / 2; 48 dig_port->tc_phy_fia_idx = tc_port % 2; 49 } else { 50 dig_port->tc_phy_fia = FIA1; 51 dig_port->tc_phy_fia_idx = tc_port; 52 } 53 } 54 55 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) 56 { 57 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 58 struct intel_uncore *uncore = &i915->uncore; 59 u32 lane_mask; 60 61 lane_mask = intel_uncore_read(uncore, 62 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 63 64 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); 65 66 lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx); 67 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); 68 } 69 70 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) 71 { 72 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 73 struct intel_uncore *uncore = &i915->uncore; 74 u32 pin_mask; 75 76 pin_mask = intel_uncore_read(uncore, 77 PORT_TX_DFLEXPA1(dig_port->tc_phy_fia)); 78 79 drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff); 80 81 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >> 82 DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); 83 } 84 85 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) 86 { 87 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 88 intel_wakeref_t wakeref; 89 u32 lane_mask; 90 91 if (dig_port->tc_mode != TC_PORT_DP_ALT) 92 return 4; 93 94 lane_mask = 0; 95 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) 96 lane_mask = intel_tc_port_get_lane_mask(dig_port); 97 98 switch (lane_mask) { 99 default: 100 MISSING_CASE(lane_mask); 101 /* fall-through */ 102 case 0x1: 103 case 0x2: 104 case 0x4: 105 case 0x8: 106 return 1; 107 case 0x3: 108 case 0xc: 109 return 2; 110 case 0xf: 111 return 4; 112 } 113 } 114 115 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, 116 int required_lanes) 117 { 118 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 119 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 120 struct intel_uncore *uncore = &i915->uncore; 121 u32 val; 122 123 drm_WARN_ON(&i915->drm, 124 lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); 125 126 val = intel_uncore_read(uncore, 127 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); 128 val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx); 129 130 switch (required_lanes) { 131 case 1: 132 val |= lane_reversal ? 133 DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) : 134 DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx); 135 break; 136 case 2: 137 val |= lane_reversal ? 138 DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) : 139 DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx); 140 break; 141 case 4: 142 val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx); 143 break; 144 default: 145 MISSING_CASE(required_lanes); 146 } 147 148 intel_uncore_write(uncore, 149 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val); 150 } 151 152 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, 153 u32 live_status_mask) 154 { 155 u32 valid_hpd_mask; 156 157 if (dig_port->tc_legacy_port) 158 valid_hpd_mask = BIT(TC_PORT_LEGACY); 159 else 160 valid_hpd_mask = BIT(TC_PORT_DP_ALT) | 161 BIT(TC_PORT_TBT_ALT); 162 163 if (!(live_status_mask & ~valid_hpd_mask)) 164 return; 165 166 /* If live status mismatches the VBT flag, trust the live status. */ 167 DRM_ERROR("Port %s: live status %08x mismatches the legacy port flag, fix flag\n", 168 dig_port->tc_port_name, live_status_mask); 169 170 dig_port->tc_legacy_port = !dig_port->tc_legacy_port; 171 } 172 173 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) 174 { 175 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 176 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); 177 struct intel_uncore *uncore = &i915->uncore; 178 u32 mask = 0; 179 u32 val; 180 181 val = intel_uncore_read(uncore, 182 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); 183 184 if (val == 0xffffffff) { 185 drm_dbg_kms(&i915->drm, 186 "Port %s: PHY in TCCOLD, nothing connected\n", 187 dig_port->tc_port_name); 188 return mask; 189 } 190 191 if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx)) 192 mask |= BIT(TC_PORT_TBT_ALT); 193 if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx)) 194 mask |= BIT(TC_PORT_DP_ALT); 195 196 if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)) 197 mask |= BIT(TC_PORT_LEGACY); 198 199 /* The sink can be connected only in a single mode. */ 200 if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) 201 tc_port_fixup_legacy_flag(dig_port, mask); 202 203 return mask; 204 } 205 206 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) 207 { 208 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 209 struct intel_uncore *uncore = &i915->uncore; 210 u32 val; 211 212 val = intel_uncore_read(uncore, 213 PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia)); 214 if (val == 0xffffffff) { 215 drm_dbg_kms(&i915->drm, 216 "Port %s: PHY in TCCOLD, assuming not complete\n", 217 dig_port->tc_port_name); 218 return false; 219 } 220 221 return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx); 222 } 223 224 static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port, 225 bool enable) 226 { 227 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 228 struct intel_uncore *uncore = &i915->uncore; 229 u32 val; 230 231 val = intel_uncore_read(uncore, 232 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 233 if (val == 0xffffffff) { 234 drm_dbg_kms(&i915->drm, 235 "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n", 236 dig_port->tc_port_name, 237 enableddisabled(enable)); 238 239 return false; 240 } 241 242 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 243 if (!enable) 244 val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); 245 246 intel_uncore_write(uncore, 247 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val); 248 249 if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10)) 250 drm_dbg_kms(&i915->drm, 251 "Port %s: PHY complete clear timed out\n", 252 dig_port->tc_port_name); 253 254 return true; 255 } 256 257 static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port) 258 { 259 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 260 struct intel_uncore *uncore = &i915->uncore; 261 u32 val; 262 263 val = intel_uncore_read(uncore, 264 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); 265 if (val == 0xffffffff) { 266 drm_dbg_kms(&i915->drm, 267 "Port %s: PHY in TCCOLD, assume safe mode\n", 268 dig_port->tc_port_name); 269 return true; 270 } 271 272 return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx)); 273 } 274 275 /* 276 * This function implements the first part of the Connect Flow described by our 277 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading 278 * lanes, EDID, etc) is done as needed in the typical places. 279 * 280 * Unlike the other ports, type-C ports are not available to use as soon as we 281 * get a hotplug. The type-C PHYs can be shared between multiple controllers: 282 * display, USB, etc. As a result, handshaking through FIA is required around 283 * connect and disconnect to cleanly transfer ownership with the controller and 284 * set the type-C power state. 285 */ 286 static void icl_tc_phy_connect(struct intel_digital_port *dig_port, 287 int required_lanes) 288 { 289 int max_lanes; 290 291 if (!icl_tc_phy_status_complete(dig_port)) { 292 DRM_DEBUG_KMS("Port %s: PHY not ready\n", 293 dig_port->tc_port_name); 294 goto out_set_tbt_alt_mode; 295 } 296 297 if (!icl_tc_phy_set_safe_mode(dig_port, false) && 298 !WARN_ON(dig_port->tc_legacy_port)) 299 goto out_set_tbt_alt_mode; 300 301 max_lanes = intel_tc_port_fia_max_lane_count(dig_port); 302 if (dig_port->tc_legacy_port) { 303 WARN_ON(max_lanes != 4); 304 dig_port->tc_mode = TC_PORT_LEGACY; 305 306 return; 307 } 308 309 /* 310 * Now we have to re-check the live state, in case the port recently 311 * became disconnected. Not necessary for legacy mode. 312 */ 313 if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { 314 DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n", 315 dig_port->tc_port_name); 316 goto out_set_safe_mode; 317 } 318 319 if (max_lanes < required_lanes) { 320 DRM_DEBUG_KMS("Port %s: PHY max lanes %d < required lanes %d\n", 321 dig_port->tc_port_name, 322 max_lanes, required_lanes); 323 goto out_set_safe_mode; 324 } 325 326 dig_port->tc_mode = TC_PORT_DP_ALT; 327 328 return; 329 330 out_set_safe_mode: 331 icl_tc_phy_set_safe_mode(dig_port, true); 332 out_set_tbt_alt_mode: 333 dig_port->tc_mode = TC_PORT_TBT_ALT; 334 } 335 336 /* 337 * See the comment at the connect function. This implements the Disconnect 338 * Flow. 339 */ 340 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port) 341 { 342 switch (dig_port->tc_mode) { 343 case TC_PORT_LEGACY: 344 /* Nothing to do, we never disconnect from legacy mode */ 345 break; 346 case TC_PORT_DP_ALT: 347 icl_tc_phy_set_safe_mode(dig_port, true); 348 dig_port->tc_mode = TC_PORT_TBT_ALT; 349 break; 350 case TC_PORT_TBT_ALT: 351 /* Nothing to do, we stay in TBT-alt mode */ 352 break; 353 default: 354 MISSING_CASE(dig_port->tc_mode); 355 } 356 } 357 358 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port) 359 { 360 if (!icl_tc_phy_status_complete(dig_port)) { 361 DRM_DEBUG_KMS("Port %s: PHY status not complete\n", 362 dig_port->tc_port_name); 363 return dig_port->tc_mode == TC_PORT_TBT_ALT; 364 } 365 366 if (icl_tc_phy_is_in_safe_mode(dig_port)) { 367 DRM_DEBUG_KMS("Port %s: PHY still in safe mode\n", 368 dig_port->tc_port_name); 369 370 return false; 371 } 372 373 return dig_port->tc_mode == TC_PORT_DP_ALT || 374 dig_port->tc_mode == TC_PORT_LEGACY; 375 } 376 377 static enum tc_port_mode 378 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port) 379 { 380 u32 live_status_mask = tc_port_live_status_mask(dig_port); 381 bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port); 382 enum tc_port_mode mode; 383 384 if (in_safe_mode || WARN_ON(!icl_tc_phy_status_complete(dig_port))) 385 return TC_PORT_TBT_ALT; 386 387 mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT; 388 if (live_status_mask) { 389 enum tc_port_mode live_mode = fls(live_status_mask) - 1; 390 391 if (!WARN_ON(live_mode == TC_PORT_TBT_ALT)) 392 mode = live_mode; 393 } 394 395 return mode; 396 } 397 398 static enum tc_port_mode 399 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port) 400 { 401 u32 live_status_mask = tc_port_live_status_mask(dig_port); 402 403 if (live_status_mask) 404 return fls(live_status_mask) - 1; 405 406 return icl_tc_phy_status_complete(dig_port) && 407 dig_port->tc_legacy_port ? TC_PORT_LEGACY : 408 TC_PORT_TBT_ALT; 409 } 410 411 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port, 412 int required_lanes) 413 { 414 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 415 enum tc_port_mode old_tc_mode = dig_port->tc_mode; 416 417 intel_display_power_flush_work(i915); 418 drm_WARN_ON(&i915->drm, 419 intel_display_power_is_enabled(i915, 420 intel_aux_power_domain(dig_port))); 421 422 icl_tc_phy_disconnect(dig_port); 423 icl_tc_phy_connect(dig_port, required_lanes); 424 425 drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n", 426 dig_port->tc_port_name, 427 tc_port_mode_name(old_tc_mode), 428 tc_port_mode_name(dig_port->tc_mode)); 429 } 430 431 static void 432 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port, 433 int refcount) 434 { 435 WARN_ON(dig_port->tc_link_refcount); 436 dig_port->tc_link_refcount = refcount; 437 } 438 439 void intel_tc_port_sanitize(struct intel_digital_port *dig_port) 440 { 441 struct intel_encoder *encoder = &dig_port->base; 442 int active_links = 0; 443 444 mutex_lock(&dig_port->tc_lock); 445 446 dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port); 447 if (dig_port->dp.is_mst) 448 active_links = intel_dp_mst_encoder_active_links(dig_port); 449 else if (encoder->base.crtc) 450 active_links = to_intel_crtc(encoder->base.crtc)->active; 451 452 if (active_links) { 453 if (!icl_tc_phy_is_connected(dig_port)) 454 DRM_DEBUG_KMS("Port %s: PHY disconnected with %d active link(s)\n", 455 dig_port->tc_port_name, active_links); 456 intel_tc_port_link_init_refcount(dig_port, active_links); 457 458 goto out; 459 } 460 461 if (dig_port->tc_legacy_port) 462 icl_tc_phy_connect(dig_port, 1); 463 464 out: 465 DRM_DEBUG_KMS("Port %s: sanitize mode (%s)\n", 466 dig_port->tc_port_name, 467 tc_port_mode_name(dig_port->tc_mode)); 468 469 mutex_unlock(&dig_port->tc_lock); 470 } 471 472 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port) 473 { 474 return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode; 475 } 476 477 /* 478 * The type-C ports are different because even when they are connected, they may 479 * not be available/usable by the graphics driver: see the comment on 480 * icl_tc_phy_connect(). So in our driver instead of adding the additional 481 * concept of "usable" and make everything check for "connected and usable" we 482 * define a port as "connected" when it is not only connected, but also when it 483 * is usable by the rest of the driver. That maintains the old assumption that 484 * connected ports are usable, and avoids exposing to the users objects they 485 * can't really use. 486 */ 487 bool intel_tc_port_connected(struct intel_digital_port *dig_port) 488 { 489 bool is_connected; 490 491 intel_tc_port_lock(dig_port); 492 is_connected = tc_port_live_status_mask(dig_port) & 493 BIT(dig_port->tc_mode); 494 intel_tc_port_unlock(dig_port); 495 496 return is_connected; 497 } 498 499 static void __intel_tc_port_lock(struct intel_digital_port *dig_port, 500 int required_lanes) 501 { 502 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 503 intel_wakeref_t wakeref; 504 505 wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE); 506 507 mutex_lock(&dig_port->tc_lock); 508 509 if (!dig_port->tc_link_refcount && 510 intel_tc_port_needs_reset(dig_port)) 511 intel_tc_port_reset_mode(dig_port, required_lanes); 512 513 drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref); 514 dig_port->tc_lock_wakeref = wakeref; 515 } 516 517 void intel_tc_port_lock(struct intel_digital_port *dig_port) 518 { 519 __intel_tc_port_lock(dig_port, 1); 520 } 521 522 void intel_tc_port_unlock(struct intel_digital_port *dig_port) 523 { 524 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 525 intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref); 526 527 mutex_unlock(&dig_port->tc_lock); 528 529 intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE, 530 wakeref); 531 } 532 533 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port) 534 { 535 return mutex_is_locked(&dig_port->tc_lock) || 536 dig_port->tc_link_refcount; 537 } 538 539 void intel_tc_port_get_link(struct intel_digital_port *dig_port, 540 int required_lanes) 541 { 542 __intel_tc_port_lock(dig_port, required_lanes); 543 dig_port->tc_link_refcount++; 544 intel_tc_port_unlock(dig_port); 545 } 546 547 void intel_tc_port_put_link(struct intel_digital_port *dig_port) 548 { 549 mutex_lock(&dig_port->tc_lock); 550 dig_port->tc_link_refcount--; 551 mutex_unlock(&dig_port->tc_lock); 552 } 553 554 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) 555 { 556 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 557 enum port port = dig_port->base.port; 558 enum tc_port tc_port = intel_port_to_tc(i915, port); 559 560 if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE)) 561 return; 562 563 snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name), 564 "%c/TC#%d", port_name(port), tc_port + 1); 565 566 mutex_init(&dig_port->tc_lock); 567 dig_port->tc_legacy_port = is_legacy; 568 dig_port->tc_link_refcount = 0; 569 tc_port_load_fia_params(i915, dig_port); 570 } 571