1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 cbb@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 status = "disabled"; 63 64 snps,write-requests = <1>; 65 snps,read-requests = <3>; 66 snps,burst-map = <0x7>; 67 snps,txpbl = <16>; 68 snps,rxpbl = <8>; 69 }; 70 71 aconnect@2900000 { 72 compatible = "nvidia,tegra194-aconnect", 73 "nvidia,tegra210-aconnect"; 74 clocks = <&bpmp TEGRA194_CLK_APE>, 75 <&bpmp TEGRA194_CLK_APB2APE>; 76 clock-names = "ape", "apb2ape"; 77 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges = <0x02900000 0x02900000 0x200000>; 81 status = "disabled"; 82 83 dma-controller@2930000 { 84 compatible = "nvidia,tegra194-adma", 85 "nvidia,tegra186-adma"; 86 reg = <0x02930000 0x20000>; 87 interrupt-parent = <&agic>; 88 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 120 #dma-cells = <1>; 121 clocks = <&bpmp TEGRA194_CLK_AHUB>; 122 clock-names = "d_audio"; 123 status = "disabled"; 124 }; 125 126 agic: interrupt-controller@2a40000 { 127 compatible = "nvidia,tegra194-agic", 128 "nvidia,tegra210-agic"; 129 #interrupt-cells = <3>; 130 interrupt-controller; 131 reg = <0x02a41000 0x1000>, 132 <0x02a42000 0x2000>; 133 interrupts = <GIC_SPI 145 134 (GIC_CPU_MASK_SIMPLE(4) | 135 IRQ_TYPE_LEVEL_HIGH)>; 136 clocks = <&bpmp TEGRA194_CLK_APE>; 137 clock-names = "clk"; 138 status = "disabled"; 139 }; 140 }; 141 142 pinmux: pinmux@2430000 { 143 compatible = "nvidia,tegra194-pinmux"; 144 reg = <0x2430000 0x17000 145 0xc300000 0x4000>; 146 147 status = "okay"; 148 149 pex_rst_c5_out_state: pex_rst_c5_out { 150 pex_rst { 151 nvidia,pins = "pex_l5_rst_n_pgg1"; 152 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 153 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 154 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 155 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 156 nvidia,tristate = <TEGRA_PIN_DISABLE>; 157 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158 }; 159 }; 160 161 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 162 clkreq { 163 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 164 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 165 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 166 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 167 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 168 nvidia,tristate = <TEGRA_PIN_DISABLE>; 169 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 170 }; 171 }; 172 }; 173 174 mc: memory-controller@2c00000 { 175 compatible = "nvidia,tegra194-mc"; 176 reg = <0x02c00000 0x100000>, 177 <0x02b80000 0x040000>, 178 <0x01700000 0x100000>; 179 status = "disabled"; 180 181 #address-cells = <2>; 182 #size-cells = <2>; 183 184 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 185 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 186 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 187 188 /* 189 * Bit 39 of addresses passing through the memory 190 * controller selects the XBAR format used when memory 191 * is accessed. This is used to transparently access 192 * memory in the XBAR format used by the discrete GPU 193 * (bit 39 set) or Tegra (bit 39 clear). 194 * 195 * As a consequence, the operating system must ensure 196 * that bit 39 is never used implicitly, for example 197 * via an I/O virtual address mapping of an IOMMU. If 198 * devices require access to the XBAR switch, their 199 * drivers must set this bit explicitly. 200 * 201 * Limit the DMA range for memory clients to [38:0]. 202 */ 203 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 204 205 emc: external-memory-controller@2c60000 { 206 compatible = "nvidia,tegra194-emc"; 207 reg = <0x0 0x02c60000 0x0 0x90000>, 208 <0x0 0x01780000 0x0 0x80000>; 209 clocks = <&bpmp TEGRA194_CLK_EMC>; 210 clock-names = "emc"; 211 212 nvidia,bpmp = <&bpmp>; 213 }; 214 }; 215 216 uarta: serial@3100000 { 217 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 218 reg = <0x03100000 0x40>; 219 reg-shift = <2>; 220 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&bpmp TEGRA194_CLK_UARTA>; 222 clock-names = "serial"; 223 resets = <&bpmp TEGRA194_RESET_UARTA>; 224 reset-names = "serial"; 225 status = "disabled"; 226 }; 227 228 uartb: serial@3110000 { 229 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 230 reg = <0x03110000 0x40>; 231 reg-shift = <2>; 232 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&bpmp TEGRA194_CLK_UARTB>; 234 clock-names = "serial"; 235 resets = <&bpmp TEGRA194_RESET_UARTB>; 236 reset-names = "serial"; 237 status = "disabled"; 238 }; 239 240 uartd: serial@3130000 { 241 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 242 reg = <0x03130000 0x40>; 243 reg-shift = <2>; 244 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&bpmp TEGRA194_CLK_UARTD>; 246 clock-names = "serial"; 247 resets = <&bpmp TEGRA194_RESET_UARTD>; 248 reset-names = "serial"; 249 status = "disabled"; 250 }; 251 252 uarte: serial@3140000 { 253 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 254 reg = <0x03140000 0x40>; 255 reg-shift = <2>; 256 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&bpmp TEGRA194_CLK_UARTE>; 258 clock-names = "serial"; 259 resets = <&bpmp TEGRA194_RESET_UARTE>; 260 reset-names = "serial"; 261 status = "disabled"; 262 }; 263 264 uartf: serial@3150000 { 265 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 266 reg = <0x03150000 0x40>; 267 reg-shift = <2>; 268 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&bpmp TEGRA194_CLK_UARTF>; 270 clock-names = "serial"; 271 resets = <&bpmp TEGRA194_RESET_UARTF>; 272 reset-names = "serial"; 273 status = "disabled"; 274 }; 275 276 gen1_i2c: i2c@3160000 { 277 compatible = "nvidia,tegra194-i2c"; 278 reg = <0x03160000 0x10000>; 279 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 clocks = <&bpmp TEGRA194_CLK_I2C1>; 283 clock-names = "div-clk"; 284 resets = <&bpmp TEGRA194_RESET_I2C1>; 285 reset-names = "i2c"; 286 status = "disabled"; 287 }; 288 289 uarth: serial@3170000 { 290 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 291 reg = <0x03170000 0x40>; 292 reg-shift = <2>; 293 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&bpmp TEGRA194_CLK_UARTH>; 295 clock-names = "serial"; 296 resets = <&bpmp TEGRA194_RESET_UARTH>; 297 reset-names = "serial"; 298 status = "disabled"; 299 }; 300 301 cam_i2c: i2c@3180000 { 302 compatible = "nvidia,tegra194-i2c"; 303 reg = <0x03180000 0x10000>; 304 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 clocks = <&bpmp TEGRA194_CLK_I2C3>; 308 clock-names = "div-clk"; 309 resets = <&bpmp TEGRA194_RESET_I2C3>; 310 reset-names = "i2c"; 311 status = "disabled"; 312 }; 313 314 /* shares pads with dpaux1 */ 315 dp_aux_ch1_i2c: i2c@3190000 { 316 compatible = "nvidia,tegra194-i2c"; 317 reg = <0x03190000 0x10000>; 318 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 clocks = <&bpmp TEGRA194_CLK_I2C4>; 322 clock-names = "div-clk"; 323 resets = <&bpmp TEGRA194_RESET_I2C4>; 324 reset-names = "i2c"; 325 status = "disabled"; 326 }; 327 328 /* shares pads with dpaux0 */ 329 dp_aux_ch0_i2c: i2c@31b0000 { 330 compatible = "nvidia,tegra194-i2c"; 331 reg = <0x031b0000 0x10000>; 332 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 clocks = <&bpmp TEGRA194_CLK_I2C6>; 336 clock-names = "div-clk"; 337 resets = <&bpmp TEGRA194_RESET_I2C6>; 338 reset-names = "i2c"; 339 status = "disabled"; 340 }; 341 342 gen7_i2c: i2c@31c0000 { 343 compatible = "nvidia,tegra194-i2c"; 344 reg = <0x031c0000 0x10000>; 345 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 clocks = <&bpmp TEGRA194_CLK_I2C7>; 349 clock-names = "div-clk"; 350 resets = <&bpmp TEGRA194_RESET_I2C7>; 351 reset-names = "i2c"; 352 status = "disabled"; 353 }; 354 355 gen9_i2c: i2c@31e0000 { 356 compatible = "nvidia,tegra194-i2c"; 357 reg = <0x031e0000 0x10000>; 358 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&bpmp TEGRA194_CLK_I2C9>; 362 clock-names = "div-clk"; 363 resets = <&bpmp TEGRA194_RESET_I2C9>; 364 reset-names = "i2c"; 365 status = "disabled"; 366 }; 367 368 pwm1: pwm@3280000 { 369 compatible = "nvidia,tegra194-pwm", 370 "nvidia,tegra186-pwm"; 371 reg = <0x3280000 0x10000>; 372 clocks = <&bpmp TEGRA194_CLK_PWM1>; 373 clock-names = "pwm"; 374 resets = <&bpmp TEGRA194_RESET_PWM1>; 375 reset-names = "pwm"; 376 status = "disabled"; 377 #pwm-cells = <2>; 378 }; 379 380 pwm2: pwm@3290000 { 381 compatible = "nvidia,tegra194-pwm", 382 "nvidia,tegra186-pwm"; 383 reg = <0x3290000 0x10000>; 384 clocks = <&bpmp TEGRA194_CLK_PWM2>; 385 clock-names = "pwm"; 386 resets = <&bpmp TEGRA194_RESET_PWM2>; 387 reset-names = "pwm"; 388 status = "disabled"; 389 #pwm-cells = <2>; 390 }; 391 392 pwm3: pwm@32a0000 { 393 compatible = "nvidia,tegra194-pwm", 394 "nvidia,tegra186-pwm"; 395 reg = <0x32a0000 0x10000>; 396 clocks = <&bpmp TEGRA194_CLK_PWM3>; 397 clock-names = "pwm"; 398 resets = <&bpmp TEGRA194_RESET_PWM3>; 399 reset-names = "pwm"; 400 status = "disabled"; 401 #pwm-cells = <2>; 402 }; 403 404 pwm5: pwm@32c0000 { 405 compatible = "nvidia,tegra194-pwm", 406 "nvidia,tegra186-pwm"; 407 reg = <0x32c0000 0x10000>; 408 clocks = <&bpmp TEGRA194_CLK_PWM5>; 409 clock-names = "pwm"; 410 resets = <&bpmp TEGRA194_RESET_PWM5>; 411 reset-names = "pwm"; 412 status = "disabled"; 413 #pwm-cells = <2>; 414 }; 415 416 pwm6: pwm@32d0000 { 417 compatible = "nvidia,tegra194-pwm", 418 "nvidia,tegra186-pwm"; 419 reg = <0x32d0000 0x10000>; 420 clocks = <&bpmp TEGRA194_CLK_PWM6>; 421 clock-names = "pwm"; 422 resets = <&bpmp TEGRA194_RESET_PWM6>; 423 reset-names = "pwm"; 424 status = "disabled"; 425 #pwm-cells = <2>; 426 }; 427 428 pwm7: pwm@32e0000 { 429 compatible = "nvidia,tegra194-pwm", 430 "nvidia,tegra186-pwm"; 431 reg = <0x32e0000 0x10000>; 432 clocks = <&bpmp TEGRA194_CLK_PWM7>; 433 clock-names = "pwm"; 434 resets = <&bpmp TEGRA194_RESET_PWM7>; 435 reset-names = "pwm"; 436 status = "disabled"; 437 #pwm-cells = <2>; 438 }; 439 440 pwm8: pwm@32f0000 { 441 compatible = "nvidia,tegra194-pwm", 442 "nvidia,tegra186-pwm"; 443 reg = <0x32f0000 0x10000>; 444 clocks = <&bpmp TEGRA194_CLK_PWM8>; 445 clock-names = "pwm"; 446 resets = <&bpmp TEGRA194_RESET_PWM8>; 447 reset-names = "pwm"; 448 status = "disabled"; 449 #pwm-cells = <2>; 450 }; 451 452 sdmmc1: sdhci@3400000 { 453 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 454 reg = <0x03400000 0x10000>; 455 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 457 clock-names = "sdhci"; 458 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 459 reset-names = "sdhci"; 460 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 461 <0x07>; 462 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 463 <0x07>; 464 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 465 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 466 <0x07>; 467 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 468 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 469 nvidia,default-tap = <0x9>; 470 nvidia,default-trim = <0x5>; 471 status = "disabled"; 472 }; 473 474 sdmmc3: sdhci@3440000 { 475 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 476 reg = <0x03440000 0x10000>; 477 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 479 clock-names = "sdhci"; 480 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 481 reset-names = "sdhci"; 482 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 483 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 484 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 485 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 486 <0x07>; 487 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 488 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 489 <0x07>; 490 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 491 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 492 nvidia,default-tap = <0x9>; 493 nvidia,default-trim = <0x5>; 494 status = "disabled"; 495 }; 496 497 sdmmc4: sdhci@3460000 { 498 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 499 reg = <0x03460000 0x10000>; 500 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 502 clock-names = "sdhci"; 503 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 504 <&bpmp TEGRA194_CLK_PLLC4>; 505 assigned-clock-parents = 506 <&bpmp TEGRA194_CLK_PLLC4>; 507 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 508 reset-names = "sdhci"; 509 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 510 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 511 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 512 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 513 <0x0a>; 514 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 515 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 516 <0x0a>; 517 nvidia,default-tap = <0x8>; 518 nvidia,default-trim = <0x14>; 519 nvidia,dqs-trim = <40>; 520 supports-cqe; 521 status = "disabled"; 522 }; 523 524 hda@3510000 { 525 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 526 reg = <0x3510000 0x10000>; 527 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&bpmp TEGRA194_CLK_HDA>, 529 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 530 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 531 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 532 resets = <&bpmp TEGRA194_RESET_HDA>, 533 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 534 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 535 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 536 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 537 status = "disabled"; 538 }; 539 540 xusb_padctl: padctl@3520000 { 541 compatible = "nvidia,tegra194-xusb-padctl"; 542 reg = <0x03520000 0x1000>, 543 <0x03540000 0x1000>; 544 reg-names = "padctl", "ao"; 545 546 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 547 reset-names = "padctl"; 548 549 status = "disabled"; 550 551 pads { 552 usb2 { 553 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 554 clock-names = "trk"; 555 556 lanes { 557 usb2-0 { 558 nvidia,function = "xusb"; 559 status = "disabled"; 560 #phy-cells = <0>; 561 }; 562 563 usb2-1 { 564 nvidia,function = "xusb"; 565 status = "disabled"; 566 #phy-cells = <0>; 567 }; 568 569 usb2-2 { 570 nvidia,function = "xusb"; 571 status = "disabled"; 572 #phy-cells = <0>; 573 }; 574 575 usb2-3 { 576 nvidia,function = "xusb"; 577 status = "disabled"; 578 #phy-cells = <0>; 579 }; 580 }; 581 }; 582 583 usb3 { 584 lanes { 585 usb3-0 { 586 nvidia,function = "xusb"; 587 status = "disabled"; 588 #phy-cells = <0>; 589 }; 590 591 usb3-1 { 592 nvidia,function = "xusb"; 593 status = "disabled"; 594 #phy-cells = <0>; 595 }; 596 597 usb3-2 { 598 nvidia,function = "xusb"; 599 status = "disabled"; 600 #phy-cells = <0>; 601 }; 602 603 usb3-3 { 604 nvidia,function = "xusb"; 605 status = "disabled"; 606 #phy-cells = <0>; 607 }; 608 }; 609 }; 610 }; 611 612 ports { 613 usb2-0 { 614 status = "disabled"; 615 }; 616 617 usb2-1 { 618 status = "disabled"; 619 }; 620 621 usb2-2 { 622 status = "disabled"; 623 }; 624 625 usb2-3 { 626 status = "disabled"; 627 }; 628 629 usb3-0 { 630 status = "disabled"; 631 }; 632 633 usb3-1 { 634 status = "disabled"; 635 }; 636 637 usb3-2 { 638 status = "disabled"; 639 }; 640 641 usb3-3 { 642 status = "disabled"; 643 }; 644 }; 645 }; 646 647 usb@3550000 { 648 compatible = "nvidia,tegra194-xudc"; 649 reg = <0x03550000 0x8000>, 650 <0x03558000 0x1000>; 651 reg-names = "base", "fpci"; 652 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 654 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 655 <&bpmp TEGRA194_CLK_XUSB_SS>, 656 <&bpmp TEGRA194_CLK_XUSB_FS>; 657 clock-names = "dev", "ss", "ss_src", "fs_src"; 658 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 659 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 660 power-domain-names = "dev", "ss"; 661 nvidia,xusb-padctl = <&xusb_padctl>; 662 status = "disabled"; 663 }; 664 665 usb@3610000 { 666 compatible = "nvidia,tegra194-xusb"; 667 reg = <0x03610000 0x40000>, 668 <0x03600000 0x10000>; 669 reg-names = "hcd", "fpci"; 670 671 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 674 675 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 676 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 677 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 678 <&bpmp TEGRA194_CLK_XUSB_SS>, 679 <&bpmp TEGRA194_CLK_CLK_M>, 680 <&bpmp TEGRA194_CLK_XUSB_FS>, 681 <&bpmp TEGRA194_CLK_UTMIPLL>, 682 <&bpmp TEGRA194_CLK_CLK_M>, 683 <&bpmp TEGRA194_CLK_PLLE>; 684 clock-names = "xusb_host", "xusb_falcon_src", 685 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 686 "xusb_fs_src", "pll_u_480m", "clk_m", 687 "pll_e"; 688 689 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 690 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 691 power-domain-names = "xusb_host", "xusb_ss"; 692 693 nvidia,xusb-padctl = <&xusb_padctl>; 694 status = "disabled"; 695 }; 696 697 fuse@3820000 { 698 compatible = "nvidia,tegra194-efuse"; 699 reg = <0x03820000 0x10000>; 700 clocks = <&bpmp TEGRA194_CLK_FUSE>; 701 clock-names = "fuse"; 702 }; 703 704 gic: interrupt-controller@3881000 { 705 compatible = "arm,gic-400"; 706 #interrupt-cells = <3>; 707 interrupt-controller; 708 reg = <0x03881000 0x1000>, 709 <0x03882000 0x2000>, 710 <0x03884000 0x2000>, 711 <0x03886000 0x2000>; 712 interrupts = <GIC_PPI 9 713 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 714 interrupt-parent = <&gic>; 715 }; 716 717 cec@3960000 { 718 compatible = "nvidia,tegra194-cec"; 719 reg = <0x03960000 0x10000>; 720 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&bpmp TEGRA194_CLK_CEC>; 722 clock-names = "cec"; 723 status = "disabled"; 724 }; 725 726 hsp_top0: hsp@3c00000 { 727 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 728 reg = <0x03c00000 0xa0000>; 729 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 739 "shared3", "shared4", "shared5", "shared6", 740 "shared7"; 741 #mbox-cells = <2>; 742 }; 743 744 p2u_hsio_0: phy@3e10000 { 745 compatible = "nvidia,tegra194-p2u"; 746 reg = <0x03e10000 0x10000>; 747 reg-names = "ctl"; 748 749 #phy-cells = <0>; 750 }; 751 752 p2u_hsio_1: phy@3e20000 { 753 compatible = "nvidia,tegra194-p2u"; 754 reg = <0x03e20000 0x10000>; 755 reg-names = "ctl"; 756 757 #phy-cells = <0>; 758 }; 759 760 p2u_hsio_2: phy@3e30000 { 761 compatible = "nvidia,tegra194-p2u"; 762 reg = <0x03e30000 0x10000>; 763 reg-names = "ctl"; 764 765 #phy-cells = <0>; 766 }; 767 768 p2u_hsio_3: phy@3e40000 { 769 compatible = "nvidia,tegra194-p2u"; 770 reg = <0x03e40000 0x10000>; 771 reg-names = "ctl"; 772 773 #phy-cells = <0>; 774 }; 775 776 p2u_hsio_4: phy@3e50000 { 777 compatible = "nvidia,tegra194-p2u"; 778 reg = <0x03e50000 0x10000>; 779 reg-names = "ctl"; 780 781 #phy-cells = <0>; 782 }; 783 784 p2u_hsio_5: phy@3e60000 { 785 compatible = "nvidia,tegra194-p2u"; 786 reg = <0x03e60000 0x10000>; 787 reg-names = "ctl"; 788 789 #phy-cells = <0>; 790 }; 791 792 p2u_hsio_6: phy@3e70000 { 793 compatible = "nvidia,tegra194-p2u"; 794 reg = <0x03e70000 0x10000>; 795 reg-names = "ctl"; 796 797 #phy-cells = <0>; 798 }; 799 800 p2u_hsio_7: phy@3e80000 { 801 compatible = "nvidia,tegra194-p2u"; 802 reg = <0x03e80000 0x10000>; 803 reg-names = "ctl"; 804 805 #phy-cells = <0>; 806 }; 807 808 p2u_hsio_8: phy@3e90000 { 809 compatible = "nvidia,tegra194-p2u"; 810 reg = <0x03e90000 0x10000>; 811 reg-names = "ctl"; 812 813 #phy-cells = <0>; 814 }; 815 816 p2u_hsio_9: phy@3ea0000 { 817 compatible = "nvidia,tegra194-p2u"; 818 reg = <0x03ea0000 0x10000>; 819 reg-names = "ctl"; 820 821 #phy-cells = <0>; 822 }; 823 824 p2u_nvhs_0: phy@3eb0000 { 825 compatible = "nvidia,tegra194-p2u"; 826 reg = <0x03eb0000 0x10000>; 827 reg-names = "ctl"; 828 829 #phy-cells = <0>; 830 }; 831 832 p2u_nvhs_1: phy@3ec0000 { 833 compatible = "nvidia,tegra194-p2u"; 834 reg = <0x03ec0000 0x10000>; 835 reg-names = "ctl"; 836 837 #phy-cells = <0>; 838 }; 839 840 p2u_nvhs_2: phy@3ed0000 { 841 compatible = "nvidia,tegra194-p2u"; 842 reg = <0x03ed0000 0x10000>; 843 reg-names = "ctl"; 844 845 #phy-cells = <0>; 846 }; 847 848 p2u_nvhs_3: phy@3ee0000 { 849 compatible = "nvidia,tegra194-p2u"; 850 reg = <0x03ee0000 0x10000>; 851 reg-names = "ctl"; 852 853 #phy-cells = <0>; 854 }; 855 856 p2u_nvhs_4: phy@3ef0000 { 857 compatible = "nvidia,tegra194-p2u"; 858 reg = <0x03ef0000 0x10000>; 859 reg-names = "ctl"; 860 861 #phy-cells = <0>; 862 }; 863 864 p2u_nvhs_5: phy@3f00000 { 865 compatible = "nvidia,tegra194-p2u"; 866 reg = <0x03f00000 0x10000>; 867 reg-names = "ctl"; 868 869 #phy-cells = <0>; 870 }; 871 872 p2u_nvhs_6: phy@3f10000 { 873 compatible = "nvidia,tegra194-p2u"; 874 reg = <0x03f10000 0x10000>; 875 reg-names = "ctl"; 876 877 #phy-cells = <0>; 878 }; 879 880 p2u_nvhs_7: phy@3f20000 { 881 compatible = "nvidia,tegra194-p2u"; 882 reg = <0x03f20000 0x10000>; 883 reg-names = "ctl"; 884 885 #phy-cells = <0>; 886 }; 887 888 p2u_hsio_10: phy@3f30000 { 889 compatible = "nvidia,tegra194-p2u"; 890 reg = <0x03f30000 0x10000>; 891 reg-names = "ctl"; 892 893 #phy-cells = <0>; 894 }; 895 896 p2u_hsio_11: phy@3f40000 { 897 compatible = "nvidia,tegra194-p2u"; 898 reg = <0x03f40000 0x10000>; 899 reg-names = "ctl"; 900 901 #phy-cells = <0>; 902 }; 903 904 hsp_aon: hsp@c150000 { 905 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 906 reg = <0x0c150000 0xa0000>; 907 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 911 /* 912 * Shared interrupt 0 is routed only to AON/SPE, so 913 * we only have 4 shared interrupts for the CCPLEX. 914 */ 915 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 916 #mbox-cells = <2>; 917 }; 918 919 gen2_i2c: i2c@c240000 { 920 compatible = "nvidia,tegra194-i2c"; 921 reg = <0x0c240000 0x10000>; 922 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 clocks = <&bpmp TEGRA194_CLK_I2C2>; 926 clock-names = "div-clk"; 927 resets = <&bpmp TEGRA194_RESET_I2C2>; 928 reset-names = "i2c"; 929 status = "disabled"; 930 }; 931 932 gen8_i2c: i2c@c250000 { 933 compatible = "nvidia,tegra194-i2c"; 934 reg = <0x0c250000 0x10000>; 935 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 clocks = <&bpmp TEGRA194_CLK_I2C8>; 939 clock-names = "div-clk"; 940 resets = <&bpmp TEGRA194_RESET_I2C8>; 941 reset-names = "i2c"; 942 status = "disabled"; 943 }; 944 945 uartc: serial@c280000 { 946 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 947 reg = <0x0c280000 0x40>; 948 reg-shift = <2>; 949 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&bpmp TEGRA194_CLK_UARTC>; 951 clock-names = "serial"; 952 resets = <&bpmp TEGRA194_RESET_UARTC>; 953 reset-names = "serial"; 954 status = "disabled"; 955 }; 956 957 uartg: serial@c290000 { 958 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 959 reg = <0x0c290000 0x40>; 960 reg-shift = <2>; 961 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&bpmp TEGRA194_CLK_UARTG>; 963 clock-names = "serial"; 964 resets = <&bpmp TEGRA194_RESET_UARTG>; 965 reset-names = "serial"; 966 status = "disabled"; 967 }; 968 969 rtc: rtc@c2a0000 { 970 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 971 reg = <0x0c2a0000 0x10000>; 972 interrupt-parent = <&pmc>; 973 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 975 clock-names = "rtc"; 976 status = "disabled"; 977 }; 978 979 gpio_aon: gpio@c2f0000 { 980 compatible = "nvidia,tegra194-gpio-aon"; 981 reg-names = "security", "gpio"; 982 reg = <0xc2f0000 0x1000>, 983 <0xc2f1000 0x1000>; 984 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 988 gpio-controller; 989 #gpio-cells = <2>; 990 interrupt-controller; 991 #interrupt-cells = <2>; 992 }; 993 994 pwm4: pwm@c340000 { 995 compatible = "nvidia,tegra194-pwm", 996 "nvidia,tegra186-pwm"; 997 reg = <0xc340000 0x10000>; 998 clocks = <&bpmp TEGRA194_CLK_PWM4>; 999 clock-names = "pwm"; 1000 resets = <&bpmp TEGRA194_RESET_PWM4>; 1001 reset-names = "pwm"; 1002 status = "disabled"; 1003 #pwm-cells = <2>; 1004 }; 1005 1006 pmc: pmc@c360000 { 1007 compatible = "nvidia,tegra194-pmc"; 1008 reg = <0x0c360000 0x10000>, 1009 <0x0c370000 0x10000>, 1010 <0x0c380000 0x10000>, 1011 <0x0c390000 0x10000>, 1012 <0x0c3a0000 0x10000>; 1013 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1014 1015 #interrupt-cells = <2>; 1016 interrupt-controller; 1017 }; 1018 1019 host1x@13e00000 { 1020 compatible = "nvidia,tegra194-host1x", "simple-bus"; 1021 reg = <0x13e00000 0x10000>, 1022 <0x13e10000 0x10000>; 1023 reg-names = "hypervisor", "vm"; 1024 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1027 clock-names = "host1x"; 1028 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1029 reset-names = "host1x"; 1030 1031 #address-cells = <1>; 1032 #size-cells = <1>; 1033 1034 ranges = <0x15000000 0x15000000 0x01000000>; 1035 1036 display-hub@15200000 { 1037 compatible = "nvidia,tegra194-display", "simple-bus"; 1038 reg = <0x15200000 0x00040000>; 1039 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1040 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1041 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1042 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1043 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1044 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1045 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1046 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1047 "wgrp3", "wgrp4", "wgrp5"; 1048 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1049 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1050 clock-names = "disp", "hub"; 1051 status = "disabled"; 1052 1053 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1054 1055 #address-cells = <1>; 1056 #size-cells = <1>; 1057 1058 ranges = <0x15200000 0x15200000 0x40000>; 1059 1060 display@15200000 { 1061 compatible = "nvidia,tegra194-dc"; 1062 reg = <0x15200000 0x10000>; 1063 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1065 clock-names = "dc"; 1066 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1067 reset-names = "dc"; 1068 1069 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1070 1071 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1072 nvidia,head = <0>; 1073 }; 1074 1075 display@15210000 { 1076 compatible = "nvidia,tegra194-dc"; 1077 reg = <0x15210000 0x10000>; 1078 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1080 clock-names = "dc"; 1081 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1082 reset-names = "dc"; 1083 1084 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1085 1086 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1087 nvidia,head = <1>; 1088 }; 1089 1090 display@15220000 { 1091 compatible = "nvidia,tegra194-dc"; 1092 reg = <0x15220000 0x10000>; 1093 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1095 clock-names = "dc"; 1096 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1097 reset-names = "dc"; 1098 1099 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1100 1101 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1102 nvidia,head = <2>; 1103 }; 1104 1105 display@15230000 { 1106 compatible = "nvidia,tegra194-dc"; 1107 reg = <0x15230000 0x10000>; 1108 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1110 clock-names = "dc"; 1111 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1112 reset-names = "dc"; 1113 1114 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1115 1116 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1117 nvidia,head = <3>; 1118 }; 1119 }; 1120 1121 vic@15340000 { 1122 compatible = "nvidia,tegra194-vic"; 1123 reg = <0x15340000 0x00040000>; 1124 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&bpmp TEGRA194_CLK_VIC>; 1126 clock-names = "vic"; 1127 resets = <&bpmp TEGRA194_RESET_VIC>; 1128 reset-names = "vic"; 1129 1130 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1131 }; 1132 1133 dpaux0: dpaux@155c0000 { 1134 compatible = "nvidia,tegra194-dpaux"; 1135 reg = <0x155c0000 0x10000>; 1136 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1138 <&bpmp TEGRA194_CLK_PLLDP>; 1139 clock-names = "dpaux", "parent"; 1140 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1141 reset-names = "dpaux"; 1142 status = "disabled"; 1143 1144 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1145 1146 state_dpaux0_aux: pinmux-aux { 1147 groups = "dpaux-io"; 1148 function = "aux"; 1149 }; 1150 1151 state_dpaux0_i2c: pinmux-i2c { 1152 groups = "dpaux-io"; 1153 function = "i2c"; 1154 }; 1155 1156 state_dpaux0_off: pinmux-off { 1157 groups = "dpaux-io"; 1158 function = "off"; 1159 }; 1160 1161 i2c-bus { 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 }; 1165 }; 1166 1167 dpaux1: dpaux@155d0000 { 1168 compatible = "nvidia,tegra194-dpaux"; 1169 reg = <0x155d0000 0x10000>; 1170 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1172 <&bpmp TEGRA194_CLK_PLLDP>; 1173 clock-names = "dpaux", "parent"; 1174 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1175 reset-names = "dpaux"; 1176 status = "disabled"; 1177 1178 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1179 1180 state_dpaux1_aux: pinmux-aux { 1181 groups = "dpaux-io"; 1182 function = "aux"; 1183 }; 1184 1185 state_dpaux1_i2c: pinmux-i2c { 1186 groups = "dpaux-io"; 1187 function = "i2c"; 1188 }; 1189 1190 state_dpaux1_off: pinmux-off { 1191 groups = "dpaux-io"; 1192 function = "off"; 1193 }; 1194 1195 i2c-bus { 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 }; 1199 }; 1200 1201 dpaux2: dpaux@155e0000 { 1202 compatible = "nvidia,tegra194-dpaux"; 1203 reg = <0x155e0000 0x10000>; 1204 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1206 <&bpmp TEGRA194_CLK_PLLDP>; 1207 clock-names = "dpaux", "parent"; 1208 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1209 reset-names = "dpaux"; 1210 status = "disabled"; 1211 1212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1213 1214 state_dpaux2_aux: pinmux-aux { 1215 groups = "dpaux-io"; 1216 function = "aux"; 1217 }; 1218 1219 state_dpaux2_i2c: pinmux-i2c { 1220 groups = "dpaux-io"; 1221 function = "i2c"; 1222 }; 1223 1224 state_dpaux2_off: pinmux-off { 1225 groups = "dpaux-io"; 1226 function = "off"; 1227 }; 1228 1229 i2c-bus { 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 }; 1233 }; 1234 1235 dpaux3: dpaux@155f0000 { 1236 compatible = "nvidia,tegra194-dpaux"; 1237 reg = <0x155f0000 0x10000>; 1238 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1240 <&bpmp TEGRA194_CLK_PLLDP>; 1241 clock-names = "dpaux", "parent"; 1242 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1243 reset-names = "dpaux"; 1244 status = "disabled"; 1245 1246 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1247 1248 state_dpaux3_aux: pinmux-aux { 1249 groups = "dpaux-io"; 1250 function = "aux"; 1251 }; 1252 1253 state_dpaux3_i2c: pinmux-i2c { 1254 groups = "dpaux-io"; 1255 function = "i2c"; 1256 }; 1257 1258 state_dpaux3_off: pinmux-off { 1259 groups = "dpaux-io"; 1260 function = "off"; 1261 }; 1262 1263 i2c-bus { 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 }; 1267 }; 1268 1269 sor0: sor@15b00000 { 1270 compatible = "nvidia,tegra194-sor"; 1271 reg = <0x15b00000 0x40000>; 1272 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1274 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1275 <&bpmp TEGRA194_CLK_PLLD>, 1276 <&bpmp TEGRA194_CLK_PLLDP>, 1277 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1278 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1279 clock-names = "sor", "out", "parent", "dp", "safe", 1280 "pad"; 1281 resets = <&bpmp TEGRA194_RESET_SOR0>; 1282 reset-names = "sor"; 1283 pinctrl-0 = <&state_dpaux0_aux>; 1284 pinctrl-1 = <&state_dpaux0_i2c>; 1285 pinctrl-2 = <&state_dpaux0_off>; 1286 pinctrl-names = "aux", "i2c", "off"; 1287 status = "disabled"; 1288 1289 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1290 nvidia,interface = <0>; 1291 }; 1292 1293 sor1: sor@15b40000 { 1294 compatible = "nvidia,tegra194-sor"; 1295 reg = <0x15b40000 0x40000>; 1296 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1297 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1298 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1299 <&bpmp TEGRA194_CLK_PLLD2>, 1300 <&bpmp TEGRA194_CLK_PLLDP>, 1301 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1302 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1303 clock-names = "sor", "out", "parent", "dp", "safe", 1304 "pad"; 1305 resets = <&bpmp TEGRA194_RESET_SOR1>; 1306 reset-names = "sor"; 1307 pinctrl-0 = <&state_dpaux1_aux>; 1308 pinctrl-1 = <&state_dpaux1_i2c>; 1309 pinctrl-2 = <&state_dpaux1_off>; 1310 pinctrl-names = "aux", "i2c", "off"; 1311 status = "disabled"; 1312 1313 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1314 nvidia,interface = <1>; 1315 }; 1316 1317 sor2: sor@15b80000 { 1318 compatible = "nvidia,tegra194-sor"; 1319 reg = <0x15b80000 0x40000>; 1320 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1322 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1323 <&bpmp TEGRA194_CLK_PLLD3>, 1324 <&bpmp TEGRA194_CLK_PLLDP>, 1325 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1326 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1327 clock-names = "sor", "out", "parent", "dp", "safe", 1328 "pad"; 1329 resets = <&bpmp TEGRA194_RESET_SOR2>; 1330 reset-names = "sor"; 1331 pinctrl-0 = <&state_dpaux2_aux>; 1332 pinctrl-1 = <&state_dpaux2_i2c>; 1333 pinctrl-2 = <&state_dpaux2_off>; 1334 pinctrl-names = "aux", "i2c", "off"; 1335 status = "disabled"; 1336 1337 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1338 nvidia,interface = <2>; 1339 }; 1340 1341 sor3: sor@15bc0000 { 1342 compatible = "nvidia,tegra194-sor"; 1343 reg = <0x15bc0000 0x40000>; 1344 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1346 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1347 <&bpmp TEGRA194_CLK_PLLD4>, 1348 <&bpmp TEGRA194_CLK_PLLDP>, 1349 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1350 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1351 clock-names = "sor", "out", "parent", "dp", "safe", 1352 "pad"; 1353 resets = <&bpmp TEGRA194_RESET_SOR3>; 1354 reset-names = "sor"; 1355 pinctrl-0 = <&state_dpaux3_aux>; 1356 pinctrl-1 = <&state_dpaux3_i2c>; 1357 pinctrl-2 = <&state_dpaux3_off>; 1358 pinctrl-names = "aux", "i2c", "off"; 1359 status = "disabled"; 1360 1361 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1362 nvidia,interface = <3>; 1363 }; 1364 }; 1365 }; 1366 1367 pcie@14100000 { 1368 compatible = "nvidia,tegra194-pcie"; 1369 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1370 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 1371 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 1372 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1373 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1374 reg-names = "appl", "config", "atu_dma", "dbi"; 1375 1376 status = "disabled"; 1377 1378 #address-cells = <3>; 1379 #size-cells = <2>; 1380 device_type = "pci"; 1381 num-lanes = <1>; 1382 num-viewport = <8>; 1383 linux,pci-domain = <1>; 1384 1385 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1386 clock-names = "core"; 1387 1388 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1389 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1390 reset-names = "apb", "core"; 1391 1392 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1393 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1394 interrupt-names = "intr", "msi"; 1395 1396 #interrupt-cells = <1>; 1397 interrupt-map-mask = <0 0 0 0>; 1398 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1399 1400 nvidia,bpmp = <&bpmp 1>; 1401 1402 nvidia,aspm-cmrt-us = <60>; 1403 nvidia,aspm-pwr-on-t-us = <20>; 1404 nvidia,aspm-l0s-entrance-latency-us = <3>; 1405 1406 bus-range = <0x0 0xff>; 1407 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1408 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1409 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1410 }; 1411 1412 pcie@14120000 { 1413 compatible = "nvidia,tegra194-pcie"; 1414 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1415 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 1416 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 1417 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1418 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1419 reg-names = "appl", "config", "atu_dma", "dbi"; 1420 1421 status = "disabled"; 1422 1423 #address-cells = <3>; 1424 #size-cells = <2>; 1425 device_type = "pci"; 1426 num-lanes = <1>; 1427 num-viewport = <8>; 1428 linux,pci-domain = <2>; 1429 1430 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1431 clock-names = "core"; 1432 1433 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1434 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1435 reset-names = "apb", "core"; 1436 1437 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1438 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1439 interrupt-names = "intr", "msi"; 1440 1441 #interrupt-cells = <1>; 1442 interrupt-map-mask = <0 0 0 0>; 1443 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1444 1445 nvidia,bpmp = <&bpmp 2>; 1446 1447 nvidia,aspm-cmrt-us = <60>; 1448 nvidia,aspm-pwr-on-t-us = <20>; 1449 nvidia,aspm-l0s-entrance-latency-us = <3>; 1450 1451 bus-range = <0x0 0xff>; 1452 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1453 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1454 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1455 }; 1456 1457 pcie@14140000 { 1458 compatible = "nvidia,tegra194-pcie"; 1459 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1460 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 1461 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 1462 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1463 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1464 reg-names = "appl", "config", "atu_dma", "dbi"; 1465 1466 status = "disabled"; 1467 1468 #address-cells = <3>; 1469 #size-cells = <2>; 1470 device_type = "pci"; 1471 num-lanes = <1>; 1472 num-viewport = <8>; 1473 linux,pci-domain = <3>; 1474 1475 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1476 clock-names = "core"; 1477 1478 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1479 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1480 reset-names = "apb", "core"; 1481 1482 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1483 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1484 interrupt-names = "intr", "msi"; 1485 1486 #interrupt-cells = <1>; 1487 interrupt-map-mask = <0 0 0 0>; 1488 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1489 1490 nvidia,bpmp = <&bpmp 3>; 1491 1492 nvidia,aspm-cmrt-us = <60>; 1493 nvidia,aspm-pwr-on-t-us = <20>; 1494 nvidia,aspm-l0s-entrance-latency-us = <3>; 1495 1496 bus-range = <0x0 0xff>; 1497 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1498 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1499 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1500 }; 1501 1502 pcie@14160000 { 1503 compatible = "nvidia,tegra194-pcie"; 1504 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1505 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1506 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 1507 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1508 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1509 reg-names = "appl", "config", "atu_dma", "dbi"; 1510 1511 status = "disabled"; 1512 1513 #address-cells = <3>; 1514 #size-cells = <2>; 1515 device_type = "pci"; 1516 num-lanes = <4>; 1517 num-viewport = <8>; 1518 linux,pci-domain = <4>; 1519 1520 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1521 clock-names = "core"; 1522 1523 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1524 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1525 reset-names = "apb", "core"; 1526 1527 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1528 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1529 interrupt-names = "intr", "msi"; 1530 1531 #interrupt-cells = <1>; 1532 interrupt-map-mask = <0 0 0 0>; 1533 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1534 1535 nvidia,bpmp = <&bpmp 4>; 1536 1537 nvidia,aspm-cmrt-us = <60>; 1538 nvidia,aspm-pwr-on-t-us = <20>; 1539 nvidia,aspm-l0s-entrance-latency-us = <3>; 1540 1541 bus-range = <0x0 0xff>; 1542 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1543 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1544 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1545 }; 1546 1547 pcie@14180000 { 1548 compatible = "nvidia,tegra194-pcie"; 1549 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1550 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1551 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 1552 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1553 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1554 reg-names = "appl", "config", "atu_dma", "dbi"; 1555 1556 status = "disabled"; 1557 1558 #address-cells = <3>; 1559 #size-cells = <2>; 1560 device_type = "pci"; 1561 num-lanes = <8>; 1562 num-viewport = <8>; 1563 linux,pci-domain = <0>; 1564 1565 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1566 clock-names = "core"; 1567 1568 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1569 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1570 reset-names = "apb", "core"; 1571 1572 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1573 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1574 interrupt-names = "intr", "msi"; 1575 1576 #interrupt-cells = <1>; 1577 interrupt-map-mask = <0 0 0 0>; 1578 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1579 1580 nvidia,bpmp = <&bpmp 0>; 1581 1582 nvidia,aspm-cmrt-us = <60>; 1583 nvidia,aspm-pwr-on-t-us = <20>; 1584 nvidia,aspm-l0s-entrance-latency-us = <3>; 1585 1586 bus-range = <0x0 0xff>; 1587 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1588 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1589 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1590 }; 1591 1592 pcie@141a0000 { 1593 compatible = "nvidia,tegra194-pcie"; 1594 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1595 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1596 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 1597 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1598 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1599 reg-names = "appl", "config", "atu_dma", "dbi"; 1600 1601 status = "disabled"; 1602 1603 #address-cells = <3>; 1604 #size-cells = <2>; 1605 device_type = "pci"; 1606 num-lanes = <8>; 1607 num-viewport = <8>; 1608 linux,pci-domain = <5>; 1609 1610 pinctrl-names = "default"; 1611 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1612 1613 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1614 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1615 clock-names = "core", "core_m"; 1616 1617 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1618 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1619 reset-names = "apb", "core"; 1620 1621 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1622 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1623 interrupt-names = "intr", "msi"; 1624 1625 nvidia,bpmp = <&bpmp 5>; 1626 1627 #interrupt-cells = <1>; 1628 interrupt-map-mask = <0 0 0 0>; 1629 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1630 1631 nvidia,aspm-cmrt-us = <60>; 1632 nvidia,aspm-pwr-on-t-us = <20>; 1633 nvidia,aspm-l0s-entrance-latency-us = <3>; 1634 1635 bus-range = <0x0 0xff>; 1636 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1637 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1638 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1639 }; 1640 1641 pcie_ep@14160000 { 1642 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1643 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1644 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1645 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1646 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */ 1647 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1648 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1649 1650 status = "disabled"; 1651 1652 num-lanes = <4>; 1653 num-ib-windows = <2>; 1654 num-ob-windows = <8>; 1655 1656 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1657 clock-names = "core"; 1658 1659 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1660 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1661 reset-names = "apb", "core"; 1662 1663 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1664 interrupt-names = "intr"; 1665 1666 nvidia,bpmp = <&bpmp 4>; 1667 1668 nvidia,aspm-cmrt-us = <60>; 1669 nvidia,aspm-pwr-on-t-us = <20>; 1670 nvidia,aspm-l0s-entrance-latency-us = <3>; 1671 }; 1672 1673 pcie_ep@14180000 { 1674 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1675 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1676 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1677 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1678 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */ 1679 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1680 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1681 1682 status = "disabled"; 1683 1684 num-lanes = <8>; 1685 num-ib-windows = <2>; 1686 num-ob-windows = <8>; 1687 1688 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1689 clock-names = "core"; 1690 1691 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1692 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1693 reset-names = "apb", "core"; 1694 1695 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1696 interrupt-names = "intr"; 1697 1698 nvidia,bpmp = <&bpmp 0>; 1699 1700 nvidia,aspm-cmrt-us = <60>; 1701 nvidia,aspm-pwr-on-t-us = <20>; 1702 nvidia,aspm-l0s-entrance-latency-us = <3>; 1703 }; 1704 1705 pcie_ep@141a0000 { 1706 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1708 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1709 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1710 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ 1711 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1712 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1713 1714 status = "disabled"; 1715 1716 num-lanes = <8>; 1717 num-ib-windows = <2>; 1718 num-ob-windows = <8>; 1719 1720 pinctrl-names = "default"; 1721 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 1722 1723 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 1724 clock-names = "core"; 1725 1726 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1727 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1728 reset-names = "apb", "core"; 1729 1730 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1731 interrupt-names = "intr"; 1732 1733 nvidia,bpmp = <&bpmp 5>; 1734 1735 nvidia,aspm-cmrt-us = <60>; 1736 nvidia,aspm-pwr-on-t-us = <20>; 1737 nvidia,aspm-l0s-entrance-latency-us = <3>; 1738 }; 1739 1740 sysram@40000000 { 1741 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1742 reg = <0x0 0x40000000 0x0 0x50000>; 1743 #address-cells = <1>; 1744 #size-cells = <1>; 1745 ranges = <0x0 0x0 0x40000000 0x50000>; 1746 1747 cpu_bpmp_tx: shmem@4e000 { 1748 compatible = "nvidia,tegra194-bpmp-shmem"; 1749 reg = <0x4e000 0x1000>; 1750 label = "cpu-bpmp-tx"; 1751 pool; 1752 }; 1753 1754 cpu_bpmp_rx: shmem@4f000 { 1755 compatible = "nvidia,tegra194-bpmp-shmem"; 1756 reg = <0x4f000 0x1000>; 1757 label = "cpu-bpmp-rx"; 1758 pool; 1759 }; 1760 }; 1761 1762 bpmp: bpmp { 1763 compatible = "nvidia,tegra186-bpmp"; 1764 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1765 TEGRA_HSP_DB_MASTER_BPMP>; 1766 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1767 #clock-cells = <1>; 1768 #reset-cells = <1>; 1769 #power-domain-cells = <1>; 1770 1771 bpmp_i2c: i2c { 1772 compatible = "nvidia,tegra186-bpmp-i2c"; 1773 nvidia,bpmp-bus-id = <5>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 }; 1777 1778 bpmp_thermal: thermal { 1779 compatible = "nvidia,tegra186-bpmp-thermal"; 1780 #thermal-sensor-cells = <1>; 1781 }; 1782 }; 1783 1784 cpus { 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 1788 cpu0_0: cpu@0 { 1789 compatible = "nvidia,tegra194-carmel"; 1790 device_type = "cpu"; 1791 reg = <0x000>; 1792 enable-method = "psci"; 1793 i-cache-size = <131072>; 1794 i-cache-line-size = <64>; 1795 i-cache-sets = <512>; 1796 d-cache-size = <65536>; 1797 d-cache-line-size = <64>; 1798 d-cache-sets = <256>; 1799 next-level-cache = <&l2c_0>; 1800 }; 1801 1802 cpu0_1: cpu@1 { 1803 compatible = "nvidia,tegra194-carmel"; 1804 device_type = "cpu"; 1805 reg = <0x001>; 1806 enable-method = "psci"; 1807 i-cache-size = <131072>; 1808 i-cache-line-size = <64>; 1809 i-cache-sets = <512>; 1810 d-cache-size = <65536>; 1811 d-cache-line-size = <64>; 1812 d-cache-sets = <256>; 1813 next-level-cache = <&l2c_0>; 1814 }; 1815 1816 cpu1_0: cpu@100 { 1817 compatible = "nvidia,tegra194-carmel"; 1818 device_type = "cpu"; 1819 reg = <0x100>; 1820 enable-method = "psci"; 1821 i-cache-size = <131072>; 1822 i-cache-line-size = <64>; 1823 i-cache-sets = <512>; 1824 d-cache-size = <65536>; 1825 d-cache-line-size = <64>; 1826 d-cache-sets = <256>; 1827 next-level-cache = <&l2c_1>; 1828 }; 1829 1830 cpu1_1: cpu@101 { 1831 compatible = "nvidia,tegra194-carmel"; 1832 device_type = "cpu"; 1833 reg = <0x101>; 1834 enable-method = "psci"; 1835 i-cache-size = <131072>; 1836 i-cache-line-size = <64>; 1837 i-cache-sets = <512>; 1838 d-cache-size = <65536>; 1839 d-cache-line-size = <64>; 1840 d-cache-sets = <256>; 1841 next-level-cache = <&l2c_1>; 1842 }; 1843 1844 cpu2_0: cpu@200 { 1845 compatible = "nvidia,tegra194-carmel"; 1846 device_type = "cpu"; 1847 reg = <0x200>; 1848 enable-method = "psci"; 1849 i-cache-size = <131072>; 1850 i-cache-line-size = <64>; 1851 i-cache-sets = <512>; 1852 d-cache-size = <65536>; 1853 d-cache-line-size = <64>; 1854 d-cache-sets = <256>; 1855 next-level-cache = <&l2c_2>; 1856 }; 1857 1858 cpu2_1: cpu@201 { 1859 compatible = "nvidia,tegra194-carmel"; 1860 device_type = "cpu"; 1861 reg = <0x201>; 1862 enable-method = "psci"; 1863 i-cache-size = <131072>; 1864 i-cache-line-size = <64>; 1865 i-cache-sets = <512>; 1866 d-cache-size = <65536>; 1867 d-cache-line-size = <64>; 1868 d-cache-sets = <256>; 1869 next-level-cache = <&l2c_2>; 1870 }; 1871 1872 cpu3_0: cpu@300 { 1873 compatible = "nvidia,tegra194-carmel"; 1874 device_type = "cpu"; 1875 reg = <0x300>; 1876 enable-method = "psci"; 1877 i-cache-size = <131072>; 1878 i-cache-line-size = <64>; 1879 i-cache-sets = <512>; 1880 d-cache-size = <65536>; 1881 d-cache-line-size = <64>; 1882 d-cache-sets = <256>; 1883 next-level-cache = <&l2c_3>; 1884 }; 1885 1886 cpu3_1: cpu@301 { 1887 compatible = "nvidia,tegra194-carmel"; 1888 device_type = "cpu"; 1889 reg = <0x301>; 1890 enable-method = "psci"; 1891 i-cache-size = <131072>; 1892 i-cache-line-size = <64>; 1893 i-cache-sets = <512>; 1894 d-cache-size = <65536>; 1895 d-cache-line-size = <64>; 1896 d-cache-sets = <256>; 1897 next-level-cache = <&l2c_3>; 1898 }; 1899 1900 cpu-map { 1901 cluster0 { 1902 core0 { 1903 cpu = <&cpu0_0>; 1904 }; 1905 1906 core1 { 1907 cpu = <&cpu0_1>; 1908 }; 1909 }; 1910 1911 cluster1 { 1912 core0 { 1913 cpu = <&cpu1_0>; 1914 }; 1915 1916 core1 { 1917 cpu = <&cpu1_1>; 1918 }; 1919 }; 1920 1921 cluster2 { 1922 core0 { 1923 cpu = <&cpu2_0>; 1924 }; 1925 1926 core1 { 1927 cpu = <&cpu2_1>; 1928 }; 1929 }; 1930 1931 cluster3 { 1932 core0 { 1933 cpu = <&cpu3_0>; 1934 }; 1935 1936 core1 { 1937 cpu = <&cpu3_1>; 1938 }; 1939 }; 1940 }; 1941 1942 l2c_0: l2-cache0 { 1943 cache-size = <2097152>; 1944 cache-line-size = <64>; 1945 cache-sets = <2048>; 1946 next-level-cache = <&l3c>; 1947 }; 1948 1949 l2c_1: l2-cache1 { 1950 cache-size = <2097152>; 1951 cache-line-size = <64>; 1952 cache-sets = <2048>; 1953 next-level-cache = <&l3c>; 1954 }; 1955 1956 l2c_2: l2-cache2 { 1957 cache-size = <2097152>; 1958 cache-line-size = <64>; 1959 cache-sets = <2048>; 1960 next-level-cache = <&l3c>; 1961 }; 1962 1963 l2c_3: l2-cache3 { 1964 cache-size = <2097152>; 1965 cache-line-size = <64>; 1966 cache-sets = <2048>; 1967 next-level-cache = <&l3c>; 1968 }; 1969 1970 l3c: l3-cache { 1971 cache-size = <4194304>; 1972 cache-line-size = <64>; 1973 cache-sets = <4096>; 1974 }; 1975 }; 1976 1977 psci { 1978 compatible = "arm,psci-1.0"; 1979 status = "okay"; 1980 method = "smc"; 1981 }; 1982 1983 tcu: tcu { 1984 compatible = "nvidia,tegra194-tcu"; 1985 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1986 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1987 mbox-names = "rx", "tx"; 1988 }; 1989 1990 thermal-zones { 1991 cpu { 1992 thermal-sensors = <&{/bpmp/thermal} 1993 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1994 status = "disabled"; 1995 }; 1996 1997 gpu { 1998 thermal-sensors = <&{/bpmp/thermal} 1999 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2000 status = "disabled"; 2001 }; 2002 2003 aux { 2004 thermal-sensors = <&{/bpmp/thermal} 2005 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2006 status = "disabled"; 2007 }; 2008 2009 pllx { 2010 thermal-sensors = <&{/bpmp/thermal} 2011 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2012 status = "disabled"; 2013 }; 2014 2015 ao { 2016 thermal-sensors = <&{/bpmp/thermal} 2017 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2018 status = "disabled"; 2019 }; 2020 2021 tj { 2022 thermal-sensors = <&{/bpmp/thermal} 2023 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2024 status = "disabled"; 2025 }; 2026 }; 2027 2028 timer { 2029 compatible = "arm,armv8-timer"; 2030 interrupts = <GIC_PPI 13 2031 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2032 <GIC_PPI 14 2033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2034 <GIC_PPI 11 2035 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2036 <GIC_PPI 10 2037 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2038 interrupt-parent = <&gic>; 2039 always-on; 2040 }; 2041}; 2042