1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 #include "amdgpu_dm_crc.h" 54 55 /* Forward declarations */ 56 struct amdgpu_device; 57 struct drm_device; 58 struct amdgpu_dm_irq_handler_data; 59 struct dc; 60 struct amdgpu_bo; 61 struct dmub_srv; 62 63 struct common_irq_params { 64 struct amdgpu_device *adev; 65 enum dc_irq_source irq_src; 66 }; 67 68 /** 69 * struct irq_list_head - Linked-list for low context IRQ handlers. 70 * 71 * @head: The list_head within &struct handler_data 72 * @work: A work_struct containing the deferred handler work 73 */ 74 struct irq_list_head { 75 struct list_head head; 76 /* In case this interrupt needs post-processing, 'work' will be queued*/ 77 struct work_struct work; 78 }; 79 80 /** 81 * struct dm_compressor_info - Buffer info used by frame buffer compression 82 * @cpu_addr: MMIO cpu addr 83 * @bo_ptr: Pointer to the buffer object 84 * @gpu_addr: MMIO gpu addr 85 */ 86 struct dm_comressor_info { 87 void *cpu_addr; 88 struct amdgpu_bo *bo_ptr; 89 uint64_t gpu_addr; 90 }; 91 92 /** 93 * struct amdgpu_dm_backlight_caps - Information about backlight 94 * 95 * Describe the backlight support for ACPI or eDP AUX. 96 */ 97 struct amdgpu_dm_backlight_caps { 98 /** 99 * @ext_caps: Keep the data struct with all the information about the 100 * display support for HDR. 101 */ 102 union dpcd_sink_ext_caps *ext_caps; 103 /** 104 * @aux_min_input_signal: Min brightness value supported by the display 105 */ 106 u32 aux_min_input_signal; 107 /** 108 * @aux_max_input_signal: Max brightness value supported by the display 109 * in nits. 110 */ 111 u32 aux_max_input_signal; 112 /** 113 * @min_input_signal: minimum possible input in range 0-255. 114 */ 115 int min_input_signal; 116 /** 117 * @max_input_signal: maximum possible input in range 0-255. 118 */ 119 int max_input_signal; 120 /** 121 * @caps_valid: true if these values are from the ACPI interface. 122 */ 123 bool caps_valid; 124 /** 125 * @aux_support: Describes if the display supports AUX backlight. 126 */ 127 bool aux_support; 128 }; 129 130 /** 131 * struct amdgpu_display_manager - Central amdgpu display manager device 132 * 133 * @dc: Display Core control structure 134 * @adev: AMDGPU base driver structure 135 * @ddev: DRM base driver structure 136 * @display_indexes_num: Max number of display streams supported 137 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 138 * @backlight_dev: Backlight control device 139 * @backlight_link: Link on which to control backlight 140 * @backlight_caps: Capabilities of the backlight device 141 * @freesync_module: Module handling freesync calculations 142 * @fw_dmcu: Reference to DMCU firmware 143 * @dmcu_fw_version: Version of the DMCU firmware 144 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 145 * @cached_state: Caches device atomic state for suspend/resume 146 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 147 */ 148 struct amdgpu_display_manager { 149 150 struct dc *dc; 151 152 /** 153 * @dmub_srv: 154 * 155 * DMUB service, used for controlling the DMUB on hardware 156 * that supports it. The pointer to the dmub_srv will be 157 * NULL on hardware that does not support it. 158 */ 159 struct dmub_srv *dmub_srv; 160 161 /** 162 * @dmub_fb_info: 163 * 164 * Framebuffer regions for the DMUB. 165 */ 166 struct dmub_srv_fb_info *dmub_fb_info; 167 168 /** 169 * @dmub_fw: 170 * 171 * DMUB firmware, required on hardware that has DMUB support. 172 */ 173 const struct firmware *dmub_fw; 174 175 /** 176 * @dmub_bo: 177 * 178 * Buffer object for the DMUB. 179 */ 180 struct amdgpu_bo *dmub_bo; 181 182 /** 183 * @dmub_bo_gpu_addr: 184 * 185 * GPU virtual address for the DMUB buffer object. 186 */ 187 u64 dmub_bo_gpu_addr; 188 189 /** 190 * @dmub_bo_cpu_addr: 191 * 192 * CPU address for the DMUB buffer object. 193 */ 194 void *dmub_bo_cpu_addr; 195 196 /** 197 * @dmcub_fw_version: 198 * 199 * DMCUB firmware version. 200 */ 201 uint32_t dmcub_fw_version; 202 203 /** 204 * @cgs_device: 205 * 206 * The Common Graphics Services device. It provides an interface for 207 * accessing registers. 208 */ 209 struct cgs_device *cgs_device; 210 211 struct amdgpu_device *adev; 212 struct drm_device *ddev; 213 u16 display_indexes_num; 214 215 /** 216 * @atomic_obj: 217 * 218 * In combination with &dm_atomic_state it helps manage 219 * global atomic state that doesn't map cleanly into existing 220 * drm resources, like &dc_context. 221 */ 222 struct drm_private_obj atomic_obj; 223 224 /** 225 * @dc_lock: 226 * 227 * Guards access to DC functions that can issue register write 228 * sequences. 229 */ 230 struct mutex dc_lock; 231 232 /** 233 * @audio_lock: 234 * 235 * Guards access to audio instance changes. 236 */ 237 struct mutex audio_lock; 238 239 /** 240 * @audio_component: 241 * 242 * Used to notify ELD changes to sound driver. 243 */ 244 struct drm_audio_component *audio_component; 245 246 /** 247 * @audio_registered: 248 * 249 * True if the audio component has been registered 250 * successfully, false otherwise. 251 */ 252 bool audio_registered; 253 254 /** 255 * @irq_handler_list_low_tab: 256 * 257 * Low priority IRQ handler table. 258 * 259 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 260 * source. Low priority IRQ handlers are deferred to a workqueue to be 261 * processed. Hence, they can sleep. 262 * 263 * Note that handlers are called in the same order as they were 264 * registered (FIFO). 265 */ 266 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 267 268 /** 269 * @irq_handler_list_high_tab: 270 * 271 * High priority IRQ handler table. 272 * 273 * It is a n*m table, same as &irq_handler_list_low_tab. However, 274 * handlers in this table are not deferred and are called immediately. 275 */ 276 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 277 278 /** 279 * @pflip_params: 280 * 281 * Page flip IRQ parameters, passed to registered handlers when 282 * triggered. 283 */ 284 struct common_irq_params 285 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 286 287 /** 288 * @vblank_params: 289 * 290 * Vertical blanking IRQ parameters, passed to registered handlers when 291 * triggered. 292 */ 293 struct common_irq_params 294 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 295 296 /** 297 * @vupdate_params: 298 * 299 * Vertical update IRQ parameters, passed to registered handlers when 300 * triggered. 301 */ 302 struct common_irq_params 303 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 304 305 spinlock_t irq_handler_list_table_lock; 306 307 struct backlight_device *backlight_dev; 308 309 const struct dc_link *backlight_link; 310 struct amdgpu_dm_backlight_caps backlight_caps; 311 312 struct mod_freesync *freesync_module; 313 #ifdef CONFIG_DRM_AMD_DC_HDCP 314 struct hdcp_workqueue *hdcp_workqueue; 315 #endif 316 317 struct drm_atomic_state *cached_state; 318 319 struct dm_comressor_info compressor; 320 321 const struct firmware *fw_dmcu; 322 uint32_t dmcu_fw_version; 323 /** 324 * @soc_bounding_box: 325 * 326 * gpu_info FW provided soc bounding box struct or 0 if not 327 * available in FW 328 */ 329 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 330 }; 331 332 struct amdgpu_dm_connector { 333 334 struct drm_connector base; 335 uint32_t connector_id; 336 337 /* we need to mind the EDID between detect 338 and get modes due to analog/digital/tvencoder */ 339 struct edid *edid; 340 341 /* shared with amdgpu */ 342 struct amdgpu_hpd hpd; 343 344 /* number of modes generated from EDID at 'dc_sink' */ 345 int num_modes; 346 347 /* The 'old' sink - before an HPD. 348 * The 'current' sink is in dc_link->sink. */ 349 struct dc_sink *dc_sink; 350 struct dc_link *dc_link; 351 struct dc_sink *dc_em_sink; 352 353 /* DM only */ 354 struct drm_dp_mst_topology_mgr mst_mgr; 355 struct amdgpu_dm_dp_aux dm_dp_aux; 356 struct drm_dp_mst_port *port; 357 struct amdgpu_dm_connector *mst_port; 358 struct amdgpu_encoder *mst_encoder; 359 struct drm_dp_aux *dsc_aux; 360 361 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 362 struct amdgpu_i2c_adapter *i2c; 363 364 /* Monitor range limits */ 365 int min_vfreq ; 366 int max_vfreq ; 367 int pixel_clock_mhz; 368 369 /* Audio instance - protected by audio_lock. */ 370 int audio_inst; 371 372 struct mutex hpd_lock; 373 374 bool fake_enable; 375 #ifdef CONFIG_DEBUG_FS 376 uint32_t debugfs_dpcd_address; 377 uint32_t debugfs_dpcd_size; 378 #endif 379 bool force_yuv420_output; 380 }; 381 382 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 383 384 extern const struct amdgpu_ip_block_version dm_ip_block; 385 386 struct amdgpu_framebuffer; 387 struct amdgpu_display_manager; 388 struct dc_validation_set; 389 struct dc_plane_state; 390 391 struct dm_plane_state { 392 struct drm_plane_state base; 393 struct dc_plane_state *dc_state; 394 }; 395 396 struct dm_crtc_state { 397 struct drm_crtc_state base; 398 struct dc_stream_state *stream; 399 400 bool cm_has_degamma; 401 bool cm_is_degamma_srgb; 402 403 int update_type; 404 int active_planes; 405 bool interrupts_enabled; 406 407 int crc_skip_count; 408 enum amdgpu_dm_pipe_crc_source crc_src; 409 410 bool freesync_timing_changed; 411 bool freesync_vrr_info_changed; 412 413 bool vrr_supported; 414 struct mod_freesync_config freesync_config; 415 struct mod_vrr_params vrr_params; 416 struct dc_info_packet vrr_infopacket; 417 418 int abm_level; 419 }; 420 421 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 422 423 struct dm_atomic_state { 424 struct drm_private_state base; 425 426 struct dc_state *context; 427 }; 428 429 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 430 431 struct dm_connector_state { 432 struct drm_connector_state base; 433 434 enum amdgpu_rmx_type scaling; 435 uint8_t underscan_vborder; 436 uint8_t underscan_hborder; 437 bool underscan_enable; 438 bool freesync_capable; 439 uint8_t abm_level; 440 int vcpi_slots; 441 uint64_t pbn; 442 }; 443 444 #define to_dm_connector_state(x)\ 445 container_of((x), struct dm_connector_state, base) 446 447 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 448 struct drm_connector_state * 449 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 450 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 451 struct drm_connector_state *state, 452 struct drm_property *property, 453 uint64_t val); 454 455 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 456 const struct drm_connector_state *state, 457 struct drm_property *property, 458 uint64_t *val); 459 460 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 461 462 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 463 struct amdgpu_dm_connector *aconnector, 464 int connector_type, 465 struct dc_link *link, 466 int link_index); 467 468 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 469 struct drm_display_mode *mode); 470 471 void dm_restore_drm_connector_state(struct drm_device *dev, 472 struct drm_connector *connector); 473 474 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 475 struct edid *edid); 476 477 #define MAX_COLOR_LUT_ENTRIES 4096 478 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 479 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 480 481 void amdgpu_dm_init_color_mod(void); 482 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 483 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 484 struct dc_plane_state *dc_plane_state); 485 486 void amdgpu_dm_update_connector_after_detect( 487 struct amdgpu_dm_connector *aconnector); 488 489 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 490 491 #endif /* __AMDGPU_DM_H__ */ 492