1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_VCN_H__ 25 #define __AMDGPU_VCN_H__ 26 27 #define AMDGPU_VCN_STACK_SIZE (128*1024) 28 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 29 30 #define AMDGPU_VCN_FIRMWARE_OFFSET 256 31 #define AMDGPU_VCN_MAX_ENC_RINGS 3 32 33 #define AMDGPU_MAX_VCN_INSTANCES 2 34 #define AMDGPU_MAX_VCN_ENC_RINGS AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES 35 36 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0) 37 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1) 38 39 #define VCN_DEC_KMD_CMD 0x80000000 40 #define VCN_DEC_CMD_FENCE 0x00000000 41 #define VCN_DEC_CMD_TRAP 0x00000001 42 #define VCN_DEC_CMD_WRITE_REG 0x00000004 43 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 44 #define VCN_DEC_CMD_PACKET_START 0x0000000a 45 #define VCN_DEC_CMD_PACKET_END 0x0000000b 46 47 #define VCN_ENC_CMD_NO_OP 0x00000000 48 #define VCN_ENC_CMD_END 0x00000001 49 #define VCN_ENC_CMD_IB 0x00000002 50 #define VCN_ENC_CMD_FENCE 0x00000003 51 #define VCN_ENC_CMD_TRAP 0x00000004 52 #define VCN_ENC_CMD_REG_WRITE 0x0000000b 53 #define VCN_ENC_CMD_REG_WAIT 0x0000000c 54 55 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 56 #define VCN_AON_SOC_ADDRESS_2_0 0x1f800 57 #define VCN_VID_IP_ADDRESS_2_0 0x0 58 #define VCN_AON_IP_ADDRESS_2_0 0x30000 59 60 #define mmUVD_RBC_XX_IB_REG_CHECK 0x026b 61 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 62 #define mmUVD_REG_XX_MASK 0x026c 63 #define mmUVD_REG_XX_MASK_BASE_IDX 1 64 65 /* 1 second timeout */ 66 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 67 68 #define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask, sram_sel) \ 69 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \ 70 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 71 UVD_DPG_LMA_CTL__MASK_EN_MASK | \ 72 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \ 73 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 74 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 75 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \ 76 }) 77 78 #define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask, sram_sel) \ 79 do { \ 80 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \ 81 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \ 82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 83 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 84 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \ 85 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 86 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 87 } while (0) 88 89 #define SOC15_DPG_MODE_OFFSET_2_0(ip, inst_idx, reg) \ 90 ({ \ 91 uint32_t internal_reg_offset, addr; \ 92 bool video_range, aon_range; \ 93 \ 94 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ 95 addr <<= 2; \ 96 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \ 97 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \ 98 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \ 99 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \ 100 if (video_range) \ 101 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \ 102 (VCN_VID_IP_ADDRESS_2_0)); \ 103 else if (aon_range) \ 104 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \ 105 (VCN_AON_IP_ADDRESS_2_0)); \ 106 else \ 107 internal_reg_offset = (0xFFFFF & addr); \ 108 \ 109 internal_reg_offset >>= 2; \ 110 }) 111 112 #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en) \ 113 ({ \ 114 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \ 115 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 116 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 117 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 118 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \ 119 }) 120 121 #define WREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, value, mask_en, indirect) \ 122 do { \ 123 if (!indirect) { \ 124 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \ 125 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \ 126 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 127 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 128 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 129 } else { \ 130 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset; \ 131 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value; \ 132 } \ 133 } while (0) 134 135 enum engine_status_constants { 136 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 137 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0, 138 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 139 UVD_STATUS__UVD_BUSY = 0x00000004, 140 GB_ADDR_CONFIG_DEFAULT = 0x26010011, 141 UVD_STATUS__IDLE = 0x2, 142 UVD_STATUS__BUSY = 0x5, 143 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 144 UVD_STATUS__RBC_BUSY = 0x1, 145 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0, 146 }; 147 148 enum internal_dpg_state { 149 VCN_DPG_STATE__UNPAUSE = 0, 150 VCN_DPG_STATE__PAUSE, 151 }; 152 153 struct dpg_pause_state { 154 enum internal_dpg_state fw_based; 155 enum internal_dpg_state jpeg; 156 }; 157 158 struct amdgpu_vcn_reg{ 159 unsigned data0; 160 unsigned data1; 161 unsigned cmd; 162 unsigned nop; 163 unsigned context_id; 164 unsigned ib_vmid; 165 unsigned ib_bar_low; 166 unsigned ib_bar_high; 167 unsigned ib_size; 168 unsigned gp_scratch8; 169 unsigned scratch9; 170 }; 171 172 struct amdgpu_vcn_inst { 173 struct amdgpu_bo *vcpu_bo; 174 void *cpu_addr; 175 uint64_t gpu_addr; 176 void *saved_bo; 177 struct amdgpu_ring ring_dec; 178 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 179 struct amdgpu_irq_src irq; 180 struct amdgpu_vcn_reg external; 181 struct amdgpu_bo *dpg_sram_bo; 182 struct dpg_pause_state pause_state; 183 void *dpg_sram_cpu_addr; 184 uint64_t dpg_sram_gpu_addr; 185 uint32_t *dpg_sram_curr_addr; 186 }; 187 188 struct amdgpu_vcn { 189 unsigned fw_version; 190 struct delayed_work idle_work; 191 const struct firmware *fw; /* VCN firmware */ 192 unsigned num_enc_rings; 193 enum amd_powergating_state cur_state; 194 bool indirect_sram; 195 196 uint8_t num_vcn_inst; 197 struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES]; 198 struct amdgpu_vcn_reg internal; 199 struct drm_gpu_scheduler *vcn_enc_sched[AMDGPU_MAX_VCN_ENC_RINGS]; 200 struct drm_gpu_scheduler *vcn_dec_sched[AMDGPU_MAX_VCN_INSTANCES]; 201 uint32_t num_vcn_enc_sched; 202 uint32_t num_vcn_dec_sched; 203 204 unsigned harvest_config; 205 int (*pause_dpg_mode)(struct amdgpu_device *adev, 206 int inst_idx, struct dpg_pause_state *new_state); 207 }; 208 209 int amdgpu_vcn_sw_init(struct amdgpu_device *adev); 210 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); 211 int amdgpu_vcn_suspend(struct amdgpu_device *adev); 212 int amdgpu_vcn_resume(struct amdgpu_device *adev); 213 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 214 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 215 216 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 217 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 218 219 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 220 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 221 222 #endif 223