1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "mcdi_port_common.h" 12 #include "efx_common.h" 13 #include "nic.h" 14 15 int efx_mcdi_get_phy_cfg(struct efx_nic *efx, struct efx_mcdi_phy_data *cfg) 16 { 17 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PHY_CFG_OUT_LEN); 18 size_t outlen; 19 int rc; 20 21 BUILD_BUG_ON(MC_CMD_GET_PHY_CFG_IN_LEN != 0); 22 BUILD_BUG_ON(MC_CMD_GET_PHY_CFG_OUT_NAME_LEN != sizeof(cfg->name)); 23 24 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PHY_CFG, NULL, 0, 25 outbuf, sizeof(outbuf), &outlen); 26 if (rc) 27 goto fail; 28 29 if (outlen < MC_CMD_GET_PHY_CFG_OUT_LEN) { 30 rc = -EIO; 31 goto fail; 32 } 33 34 cfg->flags = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_FLAGS); 35 cfg->type = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_TYPE); 36 cfg->supported_cap = 37 MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_SUPPORTED_CAP); 38 cfg->channel = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_CHANNEL); 39 cfg->port = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_PRT); 40 cfg->stats_mask = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_STATS_MASK); 41 memcpy(cfg->name, MCDI_PTR(outbuf, GET_PHY_CFG_OUT_NAME), 42 sizeof(cfg->name)); 43 cfg->media = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_MEDIA_TYPE); 44 cfg->mmd_mask = MCDI_DWORD(outbuf, GET_PHY_CFG_OUT_MMD_MASK); 45 memcpy(cfg->revision, MCDI_PTR(outbuf, GET_PHY_CFG_OUT_REVISION), 46 sizeof(cfg->revision)); 47 48 return 0; 49 50 fail: 51 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 52 return rc; 53 } 54 55 void efx_link_set_advertising(struct efx_nic *efx, 56 const unsigned long *advertising) 57 { 58 memcpy(efx->link_advertising, advertising, 59 sizeof(__ETHTOOL_DECLARE_LINK_MODE_MASK())); 60 61 efx->link_advertising[0] |= ADVERTISED_Autoneg; 62 if (advertising[0] & ADVERTISED_Pause) 63 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 64 else 65 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 66 if (advertising[0] & ADVERTISED_Asym_Pause) 67 efx->wanted_fc ^= EFX_FC_TX; 68 } 69 70 int efx_mcdi_set_link(struct efx_nic *efx, u32 capabilities, 71 u32 flags, u32 loopback_mode, u32 loopback_speed) 72 { 73 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_LINK_IN_LEN); 74 int rc; 75 76 BUILD_BUG_ON(MC_CMD_SET_LINK_OUT_LEN != 0); 77 78 MCDI_SET_DWORD(inbuf, SET_LINK_IN_CAP, capabilities); 79 MCDI_SET_DWORD(inbuf, SET_LINK_IN_FLAGS, flags); 80 MCDI_SET_DWORD(inbuf, SET_LINK_IN_LOOPBACK_MODE, loopback_mode); 81 MCDI_SET_DWORD(inbuf, SET_LINK_IN_LOOPBACK_SPEED, loopback_speed); 82 83 rc = efx_mcdi_rpc(efx, MC_CMD_SET_LINK, inbuf, sizeof(inbuf), 84 NULL, 0, NULL); 85 return rc; 86 } 87 88 int efx_mcdi_loopback_modes(struct efx_nic *efx, u64 *loopback_modes) 89 { 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_LOOPBACK_MODES_OUT_LEN); 91 size_t outlen; 92 int rc; 93 94 rc = efx_mcdi_rpc(efx, MC_CMD_GET_LOOPBACK_MODES, NULL, 0, 95 outbuf, sizeof(outbuf), &outlen); 96 if (rc) 97 goto fail; 98 99 if (outlen < (MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST + 100 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN)) { 101 rc = -EIO; 102 goto fail; 103 } 104 105 *loopback_modes = MCDI_QWORD(outbuf, GET_LOOPBACK_MODES_OUT_SUGGESTED); 106 107 return 0; 108 109 fail: 110 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 111 return rc; 112 } 113 114 void mcdi_to_ethtool_linkset(u32 media, u32 cap, unsigned long *linkset) 115 { 116 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ 117 linkset) 118 119 bitmap_zero(linkset, __ETHTOOL_LINK_MODE_MASK_NBITS); 120 switch (media) { 121 case MC_CMD_MEDIA_KX4: 122 SET_BIT(Backplane); 123 if (cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 124 SET_BIT(1000baseKX_Full); 125 if (cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 126 SET_BIT(10000baseKX4_Full); 127 if (cap & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 128 SET_BIT(40000baseKR4_Full); 129 break; 130 131 case MC_CMD_MEDIA_XFP: 132 case MC_CMD_MEDIA_SFP_PLUS: 133 case MC_CMD_MEDIA_QSFP_PLUS: 134 SET_BIT(FIBRE); 135 if (cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 136 SET_BIT(1000baseT_Full); 137 if (cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 138 SET_BIT(10000baseT_Full); 139 if (cap & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 140 SET_BIT(40000baseCR4_Full); 141 if (cap & (1 << MC_CMD_PHY_CAP_100000FDX_LBN)) 142 SET_BIT(100000baseCR4_Full); 143 if (cap & (1 << MC_CMD_PHY_CAP_25000FDX_LBN)) 144 SET_BIT(25000baseCR_Full); 145 if (cap & (1 << MC_CMD_PHY_CAP_50000FDX_LBN)) 146 SET_BIT(50000baseCR2_Full); 147 break; 148 149 case MC_CMD_MEDIA_BASE_T: 150 SET_BIT(TP); 151 if (cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 152 SET_BIT(10baseT_Half); 153 if (cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 154 SET_BIT(10baseT_Full); 155 if (cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 156 SET_BIT(100baseT_Half); 157 if (cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 158 SET_BIT(100baseT_Full); 159 if (cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 160 SET_BIT(1000baseT_Half); 161 if (cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 162 SET_BIT(1000baseT_Full); 163 if (cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 164 SET_BIT(10000baseT_Full); 165 break; 166 } 167 168 if (cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 169 SET_BIT(Pause); 170 if (cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 171 SET_BIT(Asym_Pause); 172 if (cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 173 SET_BIT(Autoneg); 174 175 #undef SET_BIT 176 } 177 178 u32 ethtool_linkset_to_mcdi_cap(const unsigned long *linkset) 179 { 180 u32 result = 0; 181 182 #define TEST_BIT(name) test_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ 183 linkset) 184 185 if (TEST_BIT(10baseT_Half)) 186 result |= (1 << MC_CMD_PHY_CAP_10HDX_LBN); 187 if (TEST_BIT(10baseT_Full)) 188 result |= (1 << MC_CMD_PHY_CAP_10FDX_LBN); 189 if (TEST_BIT(100baseT_Half)) 190 result |= (1 << MC_CMD_PHY_CAP_100HDX_LBN); 191 if (TEST_BIT(100baseT_Full)) 192 result |= (1 << MC_CMD_PHY_CAP_100FDX_LBN); 193 if (TEST_BIT(1000baseT_Half)) 194 result |= (1 << MC_CMD_PHY_CAP_1000HDX_LBN); 195 if (TEST_BIT(1000baseT_Full) || TEST_BIT(1000baseKX_Full)) 196 result |= (1 << MC_CMD_PHY_CAP_1000FDX_LBN); 197 if (TEST_BIT(10000baseT_Full) || TEST_BIT(10000baseKX4_Full)) 198 result |= (1 << MC_CMD_PHY_CAP_10000FDX_LBN); 199 if (TEST_BIT(40000baseCR4_Full) || TEST_BIT(40000baseKR4_Full)) 200 result |= (1 << MC_CMD_PHY_CAP_40000FDX_LBN); 201 if (TEST_BIT(100000baseCR4_Full)) 202 result |= (1 << MC_CMD_PHY_CAP_100000FDX_LBN); 203 if (TEST_BIT(25000baseCR_Full)) 204 result |= (1 << MC_CMD_PHY_CAP_25000FDX_LBN); 205 if (TEST_BIT(50000baseCR2_Full)) 206 result |= (1 << MC_CMD_PHY_CAP_50000FDX_LBN); 207 if (TEST_BIT(Pause)) 208 result |= (1 << MC_CMD_PHY_CAP_PAUSE_LBN); 209 if (TEST_BIT(Asym_Pause)) 210 result |= (1 << MC_CMD_PHY_CAP_ASYM_LBN); 211 if (TEST_BIT(Autoneg)) 212 result |= (1 << MC_CMD_PHY_CAP_AN_LBN); 213 214 #undef TEST_BIT 215 216 return result; 217 } 218 219 u32 efx_get_mcdi_phy_flags(struct efx_nic *efx) 220 { 221 struct efx_mcdi_phy_data *phy_cfg = efx->phy_data; 222 enum efx_phy_mode mode, supported; 223 u32 flags; 224 225 /* TODO: Advertise the capabilities supported by this PHY */ 226 supported = 0; 227 if (phy_cfg->flags & (1 << MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN)) 228 supported |= PHY_MODE_TX_DISABLED; 229 if (phy_cfg->flags & (1 << MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN)) 230 supported |= PHY_MODE_LOW_POWER; 231 if (phy_cfg->flags & (1 << MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN)) 232 supported |= PHY_MODE_OFF; 233 234 mode = efx->phy_mode & supported; 235 236 flags = 0; 237 if (mode & PHY_MODE_TX_DISABLED) 238 flags |= (1 << MC_CMD_SET_LINK_IN_TXDIS_LBN); 239 if (mode & PHY_MODE_LOW_POWER) 240 flags |= (1 << MC_CMD_SET_LINK_IN_LOWPOWER_LBN); 241 if (mode & PHY_MODE_OFF) 242 flags |= (1 << MC_CMD_SET_LINK_IN_POWEROFF_LBN); 243 244 return flags; 245 } 246 247 u8 mcdi_to_ethtool_media(u32 media) 248 { 249 switch (media) { 250 case MC_CMD_MEDIA_XAUI: 251 case MC_CMD_MEDIA_CX4: 252 case MC_CMD_MEDIA_KX4: 253 return PORT_OTHER; 254 255 case MC_CMD_MEDIA_XFP: 256 case MC_CMD_MEDIA_SFP_PLUS: 257 case MC_CMD_MEDIA_QSFP_PLUS: 258 return PORT_FIBRE; 259 260 case MC_CMD_MEDIA_BASE_T: 261 return PORT_TP; 262 263 default: 264 return PORT_OTHER; 265 } 266 } 267 268 void efx_mcdi_phy_decode_link(struct efx_nic *efx, 269 struct efx_link_state *link_state, 270 u32 speed, u32 flags, u32 fcntl) 271 { 272 switch (fcntl) { 273 case MC_CMD_FCNTL_AUTO: 274 WARN_ON(1); /* This is not a link mode */ 275 link_state->fc = EFX_FC_AUTO | EFX_FC_TX | EFX_FC_RX; 276 break; 277 case MC_CMD_FCNTL_BIDIR: 278 link_state->fc = EFX_FC_TX | EFX_FC_RX; 279 break; 280 case MC_CMD_FCNTL_RESPOND: 281 link_state->fc = EFX_FC_RX; 282 break; 283 default: 284 WARN_ON(1); 285 /* Fall through */ 286 case MC_CMD_FCNTL_OFF: 287 link_state->fc = 0; 288 break; 289 } 290 291 link_state->up = !!(flags & (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 292 link_state->fd = !!(flags & (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 293 link_state->speed = speed; 294 } 295 296 /* The semantics of the ethtool FEC mode bitmask are not well defined, 297 * particularly the meaning of combinations of bits. Which means we get to 298 * define our own semantics, as follows: 299 * OFF overrides any other bits, and means "disable all FEC" (with the 300 * exception of 25G KR4/CR4, where it is not possible to reject it if AN 301 * partner requests it). 302 * AUTO on its own means use cable requirements and link partner autoneg with 303 * fw-default preferences for the cable type. 304 * AUTO and either RS or BASER means use the specified FEC type if cable and 305 * link partner support it, otherwise autoneg/fw-default. 306 * RS or BASER alone means use the specified FEC type if cable and link partner 307 * support it and either requests it, otherwise no FEC. 308 * Both RS and BASER (whether AUTO or not) means use FEC if cable and link 309 * partner support it, preferring RS to BASER. 310 */ 311 u32 ethtool_fec_caps_to_mcdi(u32 ethtool_cap) 312 { 313 u32 ret = 0; 314 315 if (ethtool_cap & ETHTOOL_FEC_OFF) 316 return 0; 317 318 if (ethtool_cap & ETHTOOL_FEC_AUTO) 319 ret |= (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN) | 320 (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN) | 321 (1 << MC_CMD_PHY_CAP_RS_FEC_LBN); 322 if (ethtool_cap & ETHTOOL_FEC_RS) 323 ret |= (1 << MC_CMD_PHY_CAP_RS_FEC_LBN) | 324 (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN); 325 if (ethtool_cap & ETHTOOL_FEC_BASER) 326 ret |= (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN) | 327 (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN) | 328 (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN) | 329 (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN); 330 return ret; 331 } 332 333 /* Invert ethtool_fec_caps_to_mcdi. There are two combinations that function 334 * can never produce, (baser xor rs) and neither req; the implementation below 335 * maps both of those to AUTO. This should never matter, and it's not clear 336 * what a better mapping would be anyway. 337 */ 338 u32 mcdi_fec_caps_to_ethtool(u32 caps, bool is_25g) 339 { 340 bool rs = caps & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN), 341 rs_req = caps & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN), 342 baser = is_25g ? caps & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN) 343 : caps & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN), 344 baser_req = is_25g ? caps & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN) 345 : caps & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN); 346 347 if (!baser && !rs) 348 return ETHTOOL_FEC_OFF; 349 return (rs_req ? ETHTOOL_FEC_RS : 0) | 350 (baser_req ? ETHTOOL_FEC_BASER : 0) | 351 (baser == baser_req && rs == rs_req ? 0 : ETHTOOL_FEC_AUTO); 352 } 353 354 /* Verify that the forced flow control settings (!EFX_FC_AUTO) are 355 * supported by the link partner. Warn the user if this isn't the case 356 */ 357 void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa) 358 { 359 struct efx_mcdi_phy_data *phy_cfg = efx->phy_data; 360 u32 rmtadv; 361 362 /* The link partner capabilities are only relevant if the 363 * link supports flow control autonegotiation 364 */ 365 if (~phy_cfg->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 366 return; 367 368 /* If flow control autoneg is supported and enabled, then fine */ 369 if (efx->wanted_fc & EFX_FC_AUTO) 370 return; 371 372 rmtadv = 0; 373 if (lpa & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 374 rmtadv |= ADVERTISED_Pause; 375 if (lpa & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 376 rmtadv |= ADVERTISED_Asym_Pause; 377 378 if ((efx->wanted_fc & EFX_FC_TX) && rmtadv == ADVERTISED_Asym_Pause) 379 netif_err(efx, link, efx->net_dev, 380 "warning: link partner doesn't support pause frames"); 381 } 382 383 bool efx_mcdi_phy_poll(struct efx_nic *efx) 384 { 385 struct efx_link_state old_state = efx->link_state; 386 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_LINK_OUT_LEN); 387 int rc; 388 389 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 390 391 BUILD_BUG_ON(MC_CMD_GET_LINK_IN_LEN != 0); 392 393 rc = efx_mcdi_rpc(efx, MC_CMD_GET_LINK, NULL, 0, 394 outbuf, sizeof(outbuf), NULL); 395 if (rc) 396 efx->link_state.up = false; 397 else 398 efx_mcdi_phy_decode_link( 399 efx, &efx->link_state, 400 MCDI_DWORD(outbuf, GET_LINK_OUT_LINK_SPEED), 401 MCDI_DWORD(outbuf, GET_LINK_OUT_FLAGS), 402 MCDI_DWORD(outbuf, GET_LINK_OUT_FCNTL)); 403 404 return !efx_link_state_equal(&efx->link_state, &old_state); 405 } 406 407 int efx_mcdi_phy_get_fecparam(struct efx_nic *efx, struct ethtool_fecparam *fec) 408 { 409 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_LINK_OUT_V2_LEN); 410 u32 caps, active, speed; /* MCDI format */ 411 bool is_25g = false; 412 size_t outlen; 413 int rc; 414 415 BUILD_BUG_ON(MC_CMD_GET_LINK_IN_LEN != 0); 416 rc = efx_mcdi_rpc(efx, MC_CMD_GET_LINK, NULL, 0, 417 outbuf, sizeof(outbuf), &outlen); 418 if (rc) 419 return rc; 420 if (outlen < MC_CMD_GET_LINK_OUT_V2_LEN) 421 return -EOPNOTSUPP; 422 423 /* behaviour for 25G/50G links depends on 25G BASER bit */ 424 speed = MCDI_DWORD(outbuf, GET_LINK_OUT_V2_LINK_SPEED); 425 is_25g = speed == 25000 || speed == 50000; 426 427 caps = MCDI_DWORD(outbuf, GET_LINK_OUT_V2_CAP); 428 fec->fec = mcdi_fec_caps_to_ethtool(caps, is_25g); 429 /* BASER is never supported on 100G */ 430 if (speed == 100000) 431 fec->fec &= ~ETHTOOL_FEC_BASER; 432 433 active = MCDI_DWORD(outbuf, GET_LINK_OUT_V2_FEC_TYPE); 434 switch (active) { 435 case MC_CMD_FEC_NONE: 436 fec->active_fec = ETHTOOL_FEC_OFF; 437 break; 438 case MC_CMD_FEC_BASER: 439 fec->active_fec = ETHTOOL_FEC_BASER; 440 break; 441 case MC_CMD_FEC_RS: 442 fec->active_fec = ETHTOOL_FEC_RS; 443 break; 444 default: 445 netif_warn(efx, hw, efx->net_dev, 446 "Firmware reports unrecognised FEC_TYPE %u\n", 447 active); 448 /* We don't know what firmware has picked. AUTO is as good a 449 * "can't happen" value as any other. 450 */ 451 fec->active_fec = ETHTOOL_FEC_AUTO; 452 break; 453 } 454 455 return 0; 456 } 457 458 int efx_mcdi_phy_test_alive(struct efx_nic *efx) 459 { 460 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PHY_STATE_OUT_LEN); 461 size_t outlen; 462 int rc; 463 464 BUILD_BUG_ON(MC_CMD_GET_PHY_STATE_IN_LEN != 0); 465 466 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PHY_STATE, NULL, 0, 467 outbuf, sizeof(outbuf), &outlen); 468 if (rc) 469 return rc; 470 471 if (outlen < MC_CMD_GET_PHY_STATE_OUT_LEN) 472 return -EIO; 473 if (MCDI_DWORD(outbuf, GET_PHY_STATE_OUT_STATE) != MC_CMD_PHY_STATE_OK) 474 return -EINVAL; 475 476 return 0; 477 } 478 479 int efx_mcdi_port_reconfigure(struct efx_nic *efx) 480 { 481 struct efx_mcdi_phy_data *phy_cfg = efx->phy_data; 482 u32 caps = (efx->link_advertising[0] ? 483 ethtool_linkset_to_mcdi_cap(efx->link_advertising) : 484 phy_cfg->forced_cap); 485 486 caps |= ethtool_fec_caps_to_mcdi(efx->fec_config); 487 488 return efx_mcdi_set_link(efx, caps, efx_get_mcdi_phy_flags(efx), 489 efx->loopback_mode, 0); 490 } 491 492 static unsigned int efx_calc_mac_mtu(struct efx_nic *efx) 493 { 494 return EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 495 } 496 497 int efx_mcdi_set_mac(struct efx_nic *efx) 498 { 499 u32 fcntl; 500 MCDI_DECLARE_BUF(cmdbytes, MC_CMD_SET_MAC_IN_LEN); 501 502 BUILD_BUG_ON(MC_CMD_SET_MAC_OUT_LEN != 0); 503 504 /* This has no effect on EF10 */ 505 ether_addr_copy(MCDI_PTR(cmdbytes, SET_MAC_IN_ADDR), 506 efx->net_dev->dev_addr); 507 508 MCDI_SET_DWORD(cmdbytes, SET_MAC_IN_MTU, efx_calc_mac_mtu(efx)); 509 MCDI_SET_DWORD(cmdbytes, SET_MAC_IN_DRAIN, 0); 510 511 /* Set simple MAC filter for Siena */ 512 MCDI_POPULATE_DWORD_1(cmdbytes, SET_MAC_IN_REJECT, 513 SET_MAC_IN_REJECT_UNCST, efx->unicast_filter); 514 515 MCDI_POPULATE_DWORD_1(cmdbytes, SET_MAC_IN_FLAGS, 516 SET_MAC_IN_FLAG_INCLUDE_FCS, 517 !!(efx->net_dev->features & NETIF_F_RXFCS)); 518 519 switch (efx->wanted_fc) { 520 case EFX_FC_RX | EFX_FC_TX: 521 fcntl = MC_CMD_FCNTL_BIDIR; 522 break; 523 case EFX_FC_RX: 524 fcntl = MC_CMD_FCNTL_RESPOND; 525 break; 526 default: 527 fcntl = MC_CMD_FCNTL_OFF; 528 break; 529 } 530 if (efx->wanted_fc & EFX_FC_AUTO) 531 fcntl = MC_CMD_FCNTL_AUTO; 532 if (efx->fc_disable) 533 fcntl = MC_CMD_FCNTL_OFF; 534 535 MCDI_SET_DWORD(cmdbytes, SET_MAC_IN_FCNTL, fcntl); 536 537 return efx_mcdi_rpc(efx, MC_CMD_SET_MAC, cmdbytes, sizeof(cmdbytes), 538 NULL, 0, NULL); 539 } 540 541 int efx_mcdi_set_mtu(struct efx_nic *efx) 542 { 543 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MAC_EXT_IN_LEN); 544 545 BUILD_BUG_ON(MC_CMD_SET_MAC_OUT_LEN != 0); 546 547 MCDI_SET_DWORD(inbuf, SET_MAC_EXT_IN_MTU, efx_calc_mac_mtu(efx)); 548 549 MCDI_POPULATE_DWORD_1(inbuf, SET_MAC_EXT_IN_CONTROL, 550 SET_MAC_EXT_IN_CFG_MTU, 1); 551 552 return efx_mcdi_rpc(efx, MC_CMD_SET_MAC, inbuf, sizeof(inbuf), 553 NULL, 0, NULL); 554 } 555 556 enum efx_stats_action { 557 EFX_STATS_ENABLE, 558 EFX_STATS_DISABLE, 559 EFX_STATS_PULL, 560 }; 561 562 static int efx_mcdi_mac_stats(struct efx_nic *efx, 563 enum efx_stats_action action, int clear) 564 { 565 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 566 int rc; 567 int change = action == EFX_STATS_PULL ? 0 : 1; 568 int enable = action == EFX_STATS_ENABLE ? 1 : 0; 569 int period = action == EFX_STATS_ENABLE ? 1000 : 0; 570 dma_addr_t dma_addr = efx->stats_buffer.dma_addr; 571 u32 dma_len = action != EFX_STATS_DISABLE ? 572 efx->num_mac_stats * sizeof(u64) : 0; 573 574 BUILD_BUG_ON(MC_CMD_MAC_STATS_OUT_DMA_LEN != 0); 575 576 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, dma_addr); 577 MCDI_POPULATE_DWORD_7(inbuf, MAC_STATS_IN_CMD, 578 MAC_STATS_IN_DMA, !!enable, 579 MAC_STATS_IN_CLEAR, clear, 580 MAC_STATS_IN_PERIODIC_CHANGE, change, 581 MAC_STATS_IN_PERIODIC_ENABLE, enable, 582 MAC_STATS_IN_PERIODIC_CLEAR, 0, 583 MAC_STATS_IN_PERIODIC_NOEVENT, 1, 584 MAC_STATS_IN_PERIOD_MS, period); 585 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 586 587 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) 588 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, efx->vport_id); 589 590 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 591 NULL, 0, NULL); 592 /* Expect ENOENT if DMA queues have not been set up */ 593 if (rc && (rc != -ENOENT || atomic_read(&efx->active_queues))) 594 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, sizeof(inbuf), 595 NULL, 0, rc); 596 return rc; 597 } 598 599 void efx_mcdi_mac_start_stats(struct efx_nic *efx) 600 { 601 __le64 *dma_stats = efx->stats_buffer.addr; 602 603 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 604 605 efx_mcdi_mac_stats(efx, EFX_STATS_ENABLE, 0); 606 } 607 608 void efx_mcdi_mac_stop_stats(struct efx_nic *efx) 609 { 610 efx_mcdi_mac_stats(efx, EFX_STATS_DISABLE, 0); 611 } 612 613 #define EFX_MAC_STATS_WAIT_US 100 614 #define EFX_MAC_STATS_WAIT_ATTEMPTS 10 615 616 void efx_mcdi_mac_pull_stats(struct efx_nic *efx) 617 { 618 __le64 *dma_stats = efx->stats_buffer.addr; 619 int attempts = EFX_MAC_STATS_WAIT_ATTEMPTS; 620 621 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 622 efx_mcdi_mac_stats(efx, EFX_STATS_PULL, 0); 623 624 while (dma_stats[efx->num_mac_stats - 1] == 625 EFX_MC_STATS_GENERATION_INVALID && 626 attempts-- != 0) 627 udelay(EFX_MAC_STATS_WAIT_US); 628 } 629 630 int efx_mcdi_mac_init_stats(struct efx_nic *efx) 631 { 632 int rc; 633 634 if (!efx->num_mac_stats) 635 return 0; 636 637 /* Allocate buffer for stats */ 638 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, 639 efx->num_mac_stats * sizeof(u64), GFP_KERNEL); 640 if (rc) { 641 netif_warn(efx, probe, efx->net_dev, 642 "failed to allocate DMA buffer: %d\n", rc); 643 return rc; 644 } 645 646 netif_dbg(efx, probe, efx->net_dev, 647 "stats buffer at %llx (virt %p phys %llx)\n", 648 (u64) efx->stats_buffer.dma_addr, 649 efx->stats_buffer.addr, 650 (u64) virt_to_phys(efx->stats_buffer.addr)); 651 652 return 0; 653 } 654 655 void efx_mcdi_mac_fini_stats(struct efx_nic *efx) 656 { 657 efx_nic_free_buffer(efx, &efx->stats_buffer); 658 } 659 660 /* Get physical port number (EF10 only; on Siena it is same as PF number) */ 661 int efx_mcdi_port_get_number(struct efx_nic *efx) 662 { 663 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN); 664 int rc; 665 666 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PORT_ASSIGNMENT, NULL, 0, 667 outbuf, sizeof(outbuf), NULL); 668 if (rc) 669 return rc; 670 671 return MCDI_DWORD(outbuf, GET_PORT_ASSIGNMENT_OUT_PORT); 672 } 673 674 static unsigned int efx_mcdi_event_link_speed[] = { 675 [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100, 676 [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000, 677 [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000, 678 [MCDI_EVENT_LINKCHANGE_SPEED_40G] = 40000, 679 [MCDI_EVENT_LINKCHANGE_SPEED_25G] = 25000, 680 [MCDI_EVENT_LINKCHANGE_SPEED_50G] = 50000, 681 [MCDI_EVENT_LINKCHANGE_SPEED_100G] = 100000, 682 }; 683 684 void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev) 685 { 686 u32 flags, fcntl, speed, lpa; 687 688 speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED); 689 EFX_WARN_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed)); 690 speed = efx_mcdi_event_link_speed[speed]; 691 692 flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS); 693 fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL); 694 lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP); 695 696 /* efx->link_state is only modified by efx_mcdi_phy_get_link(), 697 * which is only run after flushing the event queues. Therefore, it 698 * is safe to modify the link state outside of the mac_lock here. 699 */ 700 efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl); 701 702 efx_mcdi_phy_check_fcntl(efx, lpa); 703 704 efx_link_status_changed(efx); 705 } 706