1[ 2 { 3 "ArchStdEvent": "L1D_CACHE_RD" 4 }, 5 { 6 "ArchStdEvent": "L1D_CACHE_WR" 7 }, 8 { 9 "ArchStdEvent": "L1D_CACHE_REFILL_RD" 10 }, 11 { 12 "ArchStdEvent": "L1D_CACHE_INVAL" 13 }, 14 { 15 "ArchStdEvent": "L1D_TLB_REFILL_RD" 16 }, 17 { 18 "ArchStdEvent": "L1D_TLB_REFILL_WR" 19 }, 20 { 21 "ArchStdEvent": "L2D_CACHE_RD" 22 }, 23 { 24 "ArchStdEvent": "L2D_CACHE_WR" 25 }, 26 { 27 "ArchStdEvent": "L2D_CACHE_REFILL_RD" 28 }, 29 { 30 "ArchStdEvent": "L2D_CACHE_REFILL_WR" 31 }, 32 { 33 "ArchStdEvent": "L2D_CACHE_WB_VICTIM" 34 }, 35 { 36 "ArchStdEvent": "L2D_CACHE_WB_CLEAN" 37 }, 38 { 39 "ArchStdEvent": "L2D_CACHE_INVAL" 40 }, 41 { 42 "PublicDescription": "Level 1 instruction cache refill", 43 "EventCode": "0x01", 44 "EventName": "L1I_CACHE_REFILL", 45 "BriefDescription": "L1I cache refill" 46 }, 47 { 48 "PublicDescription": "Level 1 instruction TLB refill", 49 "EventCode": "0x02", 50 "EventName": "L1I_TLB_REFILL", 51 "BriefDescription": "L1I TLB refill" 52 }, 53 { 54 "PublicDescription": "Level 1 data cache refill", 55 "EventCode": "0x03", 56 "EventName": "L1D_CACHE_REFILL", 57 "BriefDescription": "L1D cache refill" 58 }, 59 { 60 "PublicDescription": "Level 1 data cache access", 61 "EventCode": "0x04", 62 "EventName": "L1D_CACHE_ACCESS", 63 "BriefDescription": "L1D cache access" 64 }, 65 { 66 "PublicDescription": "Level 1 data TLB refill", 67 "EventCode": "0x05", 68 "EventName": "L1D_TLB_REFILL", 69 "BriefDescription": "L1D TLB refill" 70 }, 71 { 72 "PublicDescription": "Level 1 instruction cache access", 73 "EventCode": "0x14", 74 "EventName": "L1I_CACHE_ACCESS", 75 "BriefDescription": "L1I cache access" 76 }, 77 { 78 "PublicDescription": "Level 2 data cache access", 79 "EventCode": "0x16", 80 "EventName": "L2D_CACHE_ACCESS", 81 "BriefDescription": "L2D cache access" 82 }, 83 { 84 "PublicDescription": "Level 2 data refill", 85 "EventCode": "0x17", 86 "EventName": "L2D_CACHE_REFILL", 87 "BriefDescription": "L2D cache refill" 88 }, 89 { 90 "PublicDescription": "Level 2 data cache, Write-Back", 91 "EventCode": "0x18", 92 "EventName": "L2D_CACHE_WB", 93 "BriefDescription": "L2D cache Write-Back" 94 }, 95 { 96 "PublicDescription": "Level 1 data TLB access. This event counts any load or store operation which accesses the data L1 TLB", 97 "EventCode": "0x25", 98 "EventName": "L1D_TLB_ACCESS", 99 "BriefDescription": "L1D TLB access" 100 }, 101 { 102 "PublicDescription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses the instruction L1 TLB", 103 "EventCode": "0x26", 104 "EventName": "L1I_TLB_ACCESS", 105 "BriefDescription": "L1I TLB access" 106 }, 107 { 108 "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count", 109 "EventCode": "0x34", 110 "EventName": "L2D_TLB_ACCESS", 111 "BriefDescription": "L2D TLB access" 112 }, 113 { 114 "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count", 115 "EventCode": "0x35", 116 "EventName": "L2I_TLB_ACCESS", 117 "BriefDescription": "L2D TLB access" 118 }, 119 { 120 "PublicDescription": "Branch target buffer misprediction", 121 "EventCode": "0x102", 122 "EventName": "BTB_MIS_PRED", 123 "BriefDescription": "BTB misprediction" 124 }, 125 { 126 "PublicDescription": "ITB miss", 127 "EventCode": "0x103", 128 "EventName": "ITB_MISS", 129 "BriefDescription": "ITB miss" 130 }, 131 { 132 "PublicDescription": "DTB miss", 133 "EventCode": "0x104", 134 "EventName": "DTB_MISS", 135 "BriefDescription": "DTB miss" 136 }, 137 { 138 "PublicDescription": "Level 1 data cache late miss", 139 "EventCode": "0x105", 140 "EventName": "L1D_CACHE_LATE_MISS", 141 "BriefDescription": "L1D cache late miss" 142 }, 143 { 144 "PublicDescription": "Level 1 data cache prefetch request", 145 "EventCode": "0x106", 146 "EventName": "L1D_CACHE_PREFETCH", 147 "BriefDescription": "L1D cache prefetch" 148 }, 149 { 150 "PublicDescription": "Level 2 data cache prefetch request", 151 "EventCode": "0x107", 152 "EventName": "L2D_CACHE_PREFETCH", 153 "BriefDescription": "L2D cache prefetch" 154 }, 155 { 156 "PublicDescription": "Level 1 stage 2 TLB refill", 157 "EventCode": "0x111", 158 "EventName": "L1_STAGE2_TLB_REFILL", 159 "BriefDescription": "L1 stage 2 TLB refill" 160 }, 161 { 162 "PublicDescription": "Page walk cache level-0 stage-1 hit", 163 "EventCode": "0x112", 164 "EventName": "PAGE_WALK_L0_STAGE1_HIT", 165 "BriefDescription": "Page walk, L0 stage-1 hit" 166 }, 167 { 168 "PublicDescription": "Page walk cache level-1 stage-1 hit", 169 "EventCode": "0x113", 170 "EventName": "PAGE_WALK_L1_STAGE1_HIT", 171 "BriefDescription": "Page walk, L1 stage-1 hit" 172 }, 173 { 174 "PublicDescription": "Page walk cache level-2 stage-1 hit", 175 "EventCode": "0x114", 176 "EventName": "PAGE_WALK_L2_STAGE1_HIT", 177 "BriefDescription": "Page walk, L2 stage-1 hit" 178 }, 179 { 180 "PublicDescription": "Page walk cache level-1 stage-2 hit", 181 "EventCode": "0x115", 182 "EventName": "PAGE_WALK_L1_STAGE2_HIT", 183 "BriefDescription": "Page walk, L1 stage-2 hit" 184 }, 185 { 186 "PublicDescription": "Page walk cache level-2 stage-2 hit", 187 "EventCode": "0x116", 188 "EventName": "PAGE_WALK_L2_STAGE2_HIT", 189 "BriefDescription": "Page walk, L2 stage-2 hit" 190 } 191] 192