1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_MDSS_H 6 #define _DPU_HW_MDSS_H 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 11 #include "msm_drv.h" 12 13 #define DPU_DBG_NAME "dpu" 14 15 #define DPU_NONE 0 16 17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 18 #define DPU_CSC_MATRIX_COEFF_SIZE 9 19 #endif 20 21 #ifndef DPU_CSC_CLAMP_SIZE 22 #define DPU_CSC_CLAMP_SIZE 6 23 #endif 24 25 #ifndef DPU_CSC_BIAS_SIZE 26 #define DPU_CSC_BIAS_SIZE 3 27 #endif 28 29 #ifndef DPU_MAX_PLANES 30 #define DPU_MAX_PLANES 4 31 #endif 32 33 #define PIPES_PER_STAGE 2 34 #ifndef DPU_MAX_DE_CURVES 35 #define DPU_MAX_DE_CURVES 3 36 #endif 37 38 enum dpu_format_flags { 39 DPU_FORMAT_FLAG_YUV_BIT, 40 DPU_FORMAT_FLAG_DX_BIT, 41 DPU_FORMAT_FLAG_COMPRESSED_BIT, 42 DPU_FORMAT_FLAG_BIT_MAX, 43 }; 44 45 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 46 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 47 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 48 #define DPU_FORMAT_IS_YUV(X) \ 49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 50 #define DPU_FORMAT_IS_DX(X) \ 51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 53 #define DPU_FORMAT_IS_TILE(X) \ 54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 56 #define DPU_FORMAT_IS_UBWC(X) \ 57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 59 60 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 61 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 64 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 65 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 66 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 67 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 68 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 69 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 72 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 73 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 74 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 75 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 76 77 #define DPU_VSYNC0_SOURCE_GPIO 0 78 #define DPU_VSYNC1_SOURCE_GPIO 1 79 #define DPU_VSYNC2_SOURCE_GPIO 2 80 #define DPU_VSYNC_SOURCE_INTF_0 3 81 #define DPU_VSYNC_SOURCE_INTF_1 4 82 #define DPU_VSYNC_SOURCE_INTF_2 5 83 #define DPU_VSYNC_SOURCE_INTF_3 6 84 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 85 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 86 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 87 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 88 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 89 90 enum dpu_hw_blk_type { 91 DPU_HW_BLK_TOP = 0, 92 DPU_HW_BLK_SSPP, 93 DPU_HW_BLK_LM, 94 DPU_HW_BLK_CTL, 95 DPU_HW_BLK_PINGPONG, 96 DPU_HW_BLK_INTF, 97 DPU_HW_BLK_WB, 98 DPU_HW_BLK_DSPP, 99 DPU_HW_BLK_MAX, 100 }; 101 102 enum dpu_mdp { 103 MDP_TOP = 0x1, 104 MDP_MAX, 105 }; 106 107 enum dpu_sspp { 108 SSPP_NONE, 109 SSPP_VIG0, 110 SSPP_VIG1, 111 SSPP_VIG2, 112 SSPP_VIG3, 113 SSPP_RGB0, 114 SSPP_RGB1, 115 SSPP_RGB2, 116 SSPP_RGB3, 117 SSPP_DMA0, 118 SSPP_DMA1, 119 SSPP_DMA2, 120 SSPP_DMA3, 121 SSPP_CURSOR0, 122 SSPP_CURSOR1, 123 SSPP_MAX 124 }; 125 126 enum dpu_sspp_type { 127 SSPP_TYPE_VIG, 128 SSPP_TYPE_RGB, 129 SSPP_TYPE_DMA, 130 SSPP_TYPE_CURSOR, 131 SSPP_TYPE_MAX 132 }; 133 134 enum dpu_lm { 135 LM_0 = 1, 136 LM_1, 137 LM_2, 138 LM_3, 139 LM_4, 140 LM_5, 141 LM_6, 142 LM_MAX 143 }; 144 145 enum dpu_stage { 146 DPU_STAGE_BASE = 0, 147 DPU_STAGE_0, 148 DPU_STAGE_1, 149 DPU_STAGE_2, 150 DPU_STAGE_3, 151 DPU_STAGE_4, 152 DPU_STAGE_5, 153 DPU_STAGE_6, 154 DPU_STAGE_7, 155 DPU_STAGE_8, 156 DPU_STAGE_9, 157 DPU_STAGE_10, 158 DPU_STAGE_MAX 159 }; 160 enum dpu_dspp { 161 DSPP_0 = 1, 162 DSPP_1, 163 DSPP_2, 164 DSPP_3, 165 DSPP_MAX 166 }; 167 168 enum dpu_ctl { 169 CTL_0 = 1, 170 CTL_1, 171 CTL_2, 172 CTL_3, 173 CTL_4, 174 CTL_MAX 175 }; 176 177 enum dpu_pingpong { 178 PINGPONG_0 = 1, 179 PINGPONG_1, 180 PINGPONG_2, 181 PINGPONG_3, 182 PINGPONG_4, 183 PINGPONG_S0, 184 PINGPONG_MAX 185 }; 186 187 enum dpu_intf { 188 INTF_0 = 1, 189 INTF_1, 190 INTF_2, 191 INTF_3, 192 INTF_4, 193 INTF_5, 194 INTF_6, 195 INTF_MAX 196 }; 197 198 enum dpu_intf_type { 199 INTF_NONE = 0x0, 200 INTF_DSI = 0x1, 201 INTF_HDMI = 0x3, 202 INTF_LCDC = 0x5, 203 INTF_EDP = 0x9, 204 INTF_DP = 0xa, 205 INTF_TYPE_MAX, 206 207 /* virtual interfaces */ 208 INTF_WB = 0x100, 209 }; 210 211 enum dpu_intf_mode { 212 INTF_MODE_NONE = 0, 213 INTF_MODE_CMD, 214 INTF_MODE_VIDEO, 215 INTF_MODE_WB_BLOCK, 216 INTF_MODE_WB_LINE, 217 INTF_MODE_MAX 218 }; 219 220 enum dpu_wb { 221 WB_0 = 1, 222 WB_1, 223 WB_2, 224 WB_3, 225 WB_MAX 226 }; 227 228 enum dpu_cwb { 229 CWB_0 = 0x1, 230 CWB_1, 231 CWB_2, 232 CWB_3, 233 CWB_MAX 234 }; 235 236 enum dpu_wd_timer { 237 WD_TIMER_0 = 0x1, 238 WD_TIMER_1, 239 WD_TIMER_2, 240 WD_TIMER_3, 241 WD_TIMER_4, 242 WD_TIMER_5, 243 WD_TIMER_MAX 244 }; 245 246 enum dpu_vbif { 247 VBIF_0, 248 VBIF_1, 249 VBIF_MAX, 250 VBIF_RT = VBIF_0, 251 VBIF_NRT = VBIF_1 252 }; 253 254 /** 255 * DPU HW,Component order color map 256 */ 257 enum { 258 C0_G_Y = 0, 259 C1_B_Cb = 1, 260 C2_R_Cr = 2, 261 C3_ALPHA = 3 262 }; 263 264 /** 265 * enum dpu_plane_type - defines how the color component pixel packing 266 * @DPU_PLANE_INTERLEAVED : Color components in single plane 267 * @DPU_PLANE_PLANAR : Color component in separate planes 268 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 269 */ 270 enum dpu_plane_type { 271 DPU_PLANE_INTERLEAVED, 272 DPU_PLANE_PLANAR, 273 DPU_PLANE_PSEUDO_PLANAR, 274 }; 275 276 /** 277 * enum dpu_chroma_samp_type - chroma sub-samplng type 278 * @DPU_CHROMA_RGB : No chroma subsampling 279 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 280 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 281 * @DPU_CHROMA_420 : 420 subsampling 282 */ 283 enum dpu_chroma_samp_type { 284 DPU_CHROMA_RGB, 285 DPU_CHROMA_H2V1, 286 DPU_CHROMA_H1V2, 287 DPU_CHROMA_420 288 }; 289 290 /** 291 * dpu_fetch_type - Defines How DPU HW fetches data 292 * @DPU_FETCH_LINEAR : fetch is line by line 293 * @DPU_FETCH_TILE : fetches data in Z order from a tile 294 * @DPU_FETCH_UBWC : fetch and decompress data 295 */ 296 enum dpu_fetch_type { 297 DPU_FETCH_LINEAR, 298 DPU_FETCH_TILE, 299 DPU_FETCH_UBWC 300 }; 301 302 /** 303 * Value of enum chosen to fit the number of bits 304 * expected by the HW programming. 305 */ 306 enum { 307 COLOR_ALPHA_1BIT = 0, 308 COLOR_ALPHA_4BIT = 1, 309 COLOR_4BIT = 0, 310 COLOR_5BIT = 1, /* No 5-bit Alpha */ 311 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 312 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 313 }; 314 315 /** 316 * enum dpu_3d_blend_mode 317 * Desribes how the 3d data is blended 318 * @BLEND_3D_NONE : 3d blending not enabled 319 * @BLEND_3D_FRAME_INT : Frame interleaving 320 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 321 * @BLEND_3D_V_ROW_INT : vertical row interleaving 322 * @BLEND_3D_COL_INT : column interleaving 323 * @BLEND_3D_MAX : 324 */ 325 enum dpu_3d_blend_mode { 326 BLEND_3D_NONE = 0, 327 BLEND_3D_FRAME_INT, 328 BLEND_3D_H_ROW_INT, 329 BLEND_3D_V_ROW_INT, 330 BLEND_3D_COL_INT, 331 BLEND_3D_MAX 332 }; 333 334 /** struct dpu_format - defines the format configuration which 335 * allows DPU HW to correctly fetch and decode the format 336 * @base: base msm_format struture containing fourcc code 337 * @fetch_planes: how the color components are packed in pixel format 338 * @element: element color ordering 339 * @bits: element bit widths 340 * @chroma_sample: chroma sub-samplng type 341 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 342 * @unpack_tight: 0 for loose, 1 for tight 343 * @unpack_count: 0 = 1 component, 1 = 2 component 344 * @bpp: bytes per pixel 345 * @alpha_enable: whether the format has an alpha channel 346 * @num_planes: number of planes (including meta data planes) 347 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 348 * @flag: usage bit flags 349 * @tile_width: format tile width 350 * @tile_height: format tile height 351 */ 352 struct dpu_format { 353 struct msm_format base; 354 enum dpu_plane_type fetch_planes; 355 u8 element[DPU_MAX_PLANES]; 356 u8 bits[DPU_MAX_PLANES]; 357 enum dpu_chroma_samp_type chroma_sample; 358 u8 unpack_align_msb; 359 u8 unpack_tight; 360 u8 unpack_count; 361 u8 bpp; 362 u8 alpha_enable; 363 u8 num_planes; 364 enum dpu_fetch_type fetch_mode; 365 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 366 u16 tile_width; 367 u16 tile_height; 368 }; 369 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 370 371 /** 372 * struct dpu_hw_fmt_layout - format information of the source pixel data 373 * @format: pixel format parameters 374 * @num_planes: number of planes (including meta data planes) 375 * @width: image width 376 * @height: image height 377 * @total_size: total size in bytes 378 * @plane_addr: address of each plane 379 * @plane_size: length of each plane 380 * @plane_pitch: pitch of each plane 381 */ 382 struct dpu_hw_fmt_layout { 383 const struct dpu_format *format; 384 uint32_t num_planes; 385 uint32_t width; 386 uint32_t height; 387 uint32_t total_size; 388 uint32_t plane_addr[DPU_MAX_PLANES]; 389 uint32_t plane_size[DPU_MAX_PLANES]; 390 uint32_t plane_pitch[DPU_MAX_PLANES]; 391 }; 392 393 struct dpu_csc_cfg { 394 /* matrix coefficients in S15.16 format */ 395 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 396 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 397 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 398 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 399 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 400 }; 401 402 /** 403 * struct dpu_mdss_color - mdss color description 404 * color 0 : green 405 * color 1 : blue 406 * color 2 : red 407 * color 3 : alpha 408 */ 409 struct dpu_mdss_color { 410 u32 color_0; 411 u32 color_1; 412 u32 color_2; 413 u32 color_3; 414 }; 415 416 /* 417 * Define bit masks for h/w logging. 418 */ 419 #define DPU_DBG_MASK_NONE (1 << 0) 420 #define DPU_DBG_MASK_INTF (1 << 1) 421 #define DPU_DBG_MASK_LM (1 << 2) 422 #define DPU_DBG_MASK_CTL (1 << 3) 423 #define DPU_DBG_MASK_PINGPONG (1 << 4) 424 #define DPU_DBG_MASK_SSPP (1 << 5) 425 #define DPU_DBG_MASK_WB (1 << 6) 426 #define DPU_DBG_MASK_TOP (1 << 7) 427 #define DPU_DBG_MASK_VBIF (1 << 8) 428 #define DPU_DBG_MASK_ROT (1 << 9) 429 #define DPU_DBG_MASK_DSPP (1 << 10) 430 431 #endif /* _DPU_HW_MDSS_H */ 432