1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 17 #include "util.h" 18 19 #define RTW_MAX_MAC_ID_NUM 32 20 #define RTW_MAX_SEC_CAM_NUM 32 21 #define MAX_PG_CAM_BACKUP_NUM 8 22 23 #define RTW_MAX_PATTERN_NUM 12 24 #define RTW_MAX_PATTERN_MASK_SIZE 16 25 #define RTW_MAX_PATTERN_SIZE 128 26 27 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 28 29 #define RFREG_MASK 0xfffff 30 #define INV_RF_DATA 0xffffffff 31 #define TX_PAGE_SIZE_SHIFT 7 32 33 #define RTW_CHANNEL_WIDTH_MAX 3 34 #define RTW_RF_PATH_MAX 4 35 #define HW_FEATURE_LEN 13 36 37 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 38 39 extern bool rtw_bf_support; 40 extern unsigned int rtw_fw_lps_deep_mode; 41 extern unsigned int rtw_debug_mask; 42 extern const struct ieee80211_ops rtw_ops; 43 44 #define RTW_MAX_CHANNEL_NUM_2G 14 45 #define RTW_MAX_CHANNEL_NUM_5G 49 46 47 struct rtw_dev; 48 49 enum rtw_hci_type { 50 RTW_HCI_TYPE_PCIE, 51 RTW_HCI_TYPE_USB, 52 RTW_HCI_TYPE_SDIO, 53 54 RTW_HCI_TYPE_UNDEFINE, 55 }; 56 57 struct rtw_hci { 58 struct rtw_hci_ops *ops; 59 enum rtw_hci_type type; 60 61 u32 rpwm_addr; 62 u32 cpwm_addr; 63 64 u8 bulkout_num; 65 }; 66 67 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 68 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 69 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 70 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 71 72 #define IS_CH_5G_BAND_MID(channel) \ 73 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 74 75 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 76 #define IS_CH_5G_BAND(channel) \ 77 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 78 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 79 80 enum rtw_supported_band { 81 RTW_BAND_2G = 1 << 0, 82 RTW_BAND_5G = 1 << 1, 83 RTW_BAND_60G = 1 << 2, 84 85 RTW_BAND_MAX, 86 }; 87 88 /* now, support upto 80M bw */ 89 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 90 91 enum rtw_bandwidth { 92 RTW_CHANNEL_WIDTH_20 = 0, 93 RTW_CHANNEL_WIDTH_40 = 1, 94 RTW_CHANNEL_WIDTH_80 = 2, 95 RTW_CHANNEL_WIDTH_160 = 3, 96 RTW_CHANNEL_WIDTH_80_80 = 4, 97 RTW_CHANNEL_WIDTH_5 = 5, 98 RTW_CHANNEL_WIDTH_10 = 6, 99 }; 100 101 enum rtw_sc_offset { 102 RTW_SC_DONT_CARE = 0, 103 RTW_SC_20_UPPER = 1, 104 RTW_SC_20_LOWER = 2, 105 RTW_SC_20_UPMOST = 3, 106 RTW_SC_20_LOWEST = 4, 107 RTW_SC_40_UPPER = 9, 108 RTW_SC_40_LOWER = 10, 109 }; 110 111 enum rtw_net_type { 112 RTW_NET_NO_LINK = 0, 113 RTW_NET_AD_HOC = 1, 114 RTW_NET_MGD_LINKED = 2, 115 RTW_NET_AP_MODE = 3, 116 }; 117 118 enum rtw_rf_type { 119 RF_1T1R = 0, 120 RF_1T2R = 1, 121 RF_2T2R = 2, 122 RF_2T3R = 3, 123 RF_2T4R = 4, 124 RF_3T3R = 5, 125 RF_3T4R = 6, 126 RF_4T4R = 7, 127 RF_TYPE_MAX, 128 }; 129 130 enum rtw_rf_path { 131 RF_PATH_A = 0, 132 RF_PATH_B = 1, 133 RF_PATH_C = 2, 134 RF_PATH_D = 3, 135 }; 136 137 enum rtw_bb_path { 138 BB_PATH_A = BIT(0), 139 BB_PATH_B = BIT(1), 140 BB_PATH_C = BIT(2), 141 BB_PATH_D = BIT(3), 142 143 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 144 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 145 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 146 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 147 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 148 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 149 150 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 151 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 152 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 153 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 154 155 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 156 }; 157 158 enum rtw_rate_section { 159 RTW_RATE_SECTION_CCK = 0, 160 RTW_RATE_SECTION_OFDM, 161 RTW_RATE_SECTION_HT_1S, 162 RTW_RATE_SECTION_HT_2S, 163 RTW_RATE_SECTION_VHT_1S, 164 RTW_RATE_SECTION_VHT_2S, 165 166 /* keep last */ 167 RTW_RATE_SECTION_MAX, 168 }; 169 170 enum rtw_wireless_set { 171 WIRELESS_CCK = 0x00000001, 172 WIRELESS_OFDM = 0x00000002, 173 WIRELESS_HT = 0x00000004, 174 WIRELESS_VHT = 0x00000008, 175 }; 176 177 #define HT_STBC_EN BIT(0) 178 #define VHT_STBC_EN BIT(1) 179 #define HT_LDPC_EN BIT(0) 180 #define VHT_LDPC_EN BIT(1) 181 182 enum rtw_chip_type { 183 RTW_CHIP_TYPE_8822B, 184 RTW_CHIP_TYPE_8822C, 185 RTW_CHIP_TYPE_8723D, 186 RTW_CHIP_TYPE_8821C, 187 }; 188 189 enum rtw_tx_queue_type { 190 /* the order of AC queues matters */ 191 RTW_TX_QUEUE_BK = 0x0, 192 RTW_TX_QUEUE_BE = 0x1, 193 RTW_TX_QUEUE_VI = 0x2, 194 RTW_TX_QUEUE_VO = 0x3, 195 196 RTW_TX_QUEUE_BCN = 0x4, 197 RTW_TX_QUEUE_MGMT = 0x5, 198 RTW_TX_QUEUE_HI0 = 0x6, 199 RTW_TX_QUEUE_H2C = 0x7, 200 /* keep it last */ 201 RTK_MAX_TX_QUEUE_NUM 202 }; 203 204 enum rtw_rx_queue_type { 205 RTW_RX_QUEUE_MPDU = 0x0, 206 RTW_RX_QUEUE_C2H = 0x1, 207 /* keep it last */ 208 RTK_MAX_RX_QUEUE_NUM 209 }; 210 211 enum rtw_fw_type { 212 RTW_NORMAL_FW = 0x0, 213 RTW_WOWLAN_FW = 0x1, 214 }; 215 216 enum rtw_rate_index { 217 RTW_RATEID_BGN_40M_2SS = 0, 218 RTW_RATEID_BGN_40M_1SS = 1, 219 RTW_RATEID_BGN_20M_2SS = 2, 220 RTW_RATEID_BGN_20M_1SS = 3, 221 RTW_RATEID_GN_N2SS = 4, 222 RTW_RATEID_GN_N1SS = 5, 223 RTW_RATEID_BG = 6, 224 RTW_RATEID_G = 7, 225 RTW_RATEID_B_20M = 8, 226 RTW_RATEID_ARFR0_AC_2SS = 9, 227 RTW_RATEID_ARFR1_AC_1SS = 10, 228 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 229 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 230 RTW_RATEID_ARFR4_AC_3SS = 13, 231 RTW_RATEID_ARFR5_N_3SS = 14, 232 RTW_RATEID_ARFR7_N_4SS = 15, 233 RTW_RATEID_ARFR6_AC_4SS = 16 234 }; 235 236 enum rtw_trx_desc_rate { 237 DESC_RATE1M = 0x00, 238 DESC_RATE2M = 0x01, 239 DESC_RATE5_5M = 0x02, 240 DESC_RATE11M = 0x03, 241 242 DESC_RATE6M = 0x04, 243 DESC_RATE9M = 0x05, 244 DESC_RATE12M = 0x06, 245 DESC_RATE18M = 0x07, 246 DESC_RATE24M = 0x08, 247 DESC_RATE36M = 0x09, 248 DESC_RATE48M = 0x0a, 249 DESC_RATE54M = 0x0b, 250 251 DESC_RATEMCS0 = 0x0c, 252 DESC_RATEMCS1 = 0x0d, 253 DESC_RATEMCS2 = 0x0e, 254 DESC_RATEMCS3 = 0x0f, 255 DESC_RATEMCS4 = 0x10, 256 DESC_RATEMCS5 = 0x11, 257 DESC_RATEMCS6 = 0x12, 258 DESC_RATEMCS7 = 0x13, 259 DESC_RATEMCS8 = 0x14, 260 DESC_RATEMCS9 = 0x15, 261 DESC_RATEMCS10 = 0x16, 262 DESC_RATEMCS11 = 0x17, 263 DESC_RATEMCS12 = 0x18, 264 DESC_RATEMCS13 = 0x19, 265 DESC_RATEMCS14 = 0x1a, 266 DESC_RATEMCS15 = 0x1b, 267 DESC_RATEMCS16 = 0x1c, 268 DESC_RATEMCS17 = 0x1d, 269 DESC_RATEMCS18 = 0x1e, 270 DESC_RATEMCS19 = 0x1f, 271 DESC_RATEMCS20 = 0x20, 272 DESC_RATEMCS21 = 0x21, 273 DESC_RATEMCS22 = 0x22, 274 DESC_RATEMCS23 = 0x23, 275 DESC_RATEMCS24 = 0x24, 276 DESC_RATEMCS25 = 0x25, 277 DESC_RATEMCS26 = 0x26, 278 DESC_RATEMCS27 = 0x27, 279 DESC_RATEMCS28 = 0x28, 280 DESC_RATEMCS29 = 0x29, 281 DESC_RATEMCS30 = 0x2a, 282 DESC_RATEMCS31 = 0x2b, 283 284 DESC_RATEVHT1SS_MCS0 = 0x2c, 285 DESC_RATEVHT1SS_MCS1 = 0x2d, 286 DESC_RATEVHT1SS_MCS2 = 0x2e, 287 DESC_RATEVHT1SS_MCS3 = 0x2f, 288 DESC_RATEVHT1SS_MCS4 = 0x30, 289 DESC_RATEVHT1SS_MCS5 = 0x31, 290 DESC_RATEVHT1SS_MCS6 = 0x32, 291 DESC_RATEVHT1SS_MCS7 = 0x33, 292 DESC_RATEVHT1SS_MCS8 = 0x34, 293 DESC_RATEVHT1SS_MCS9 = 0x35, 294 295 DESC_RATEVHT2SS_MCS0 = 0x36, 296 DESC_RATEVHT2SS_MCS1 = 0x37, 297 DESC_RATEVHT2SS_MCS2 = 0x38, 298 DESC_RATEVHT2SS_MCS3 = 0x39, 299 DESC_RATEVHT2SS_MCS4 = 0x3a, 300 DESC_RATEVHT2SS_MCS5 = 0x3b, 301 DESC_RATEVHT2SS_MCS6 = 0x3c, 302 DESC_RATEVHT2SS_MCS7 = 0x3d, 303 DESC_RATEVHT2SS_MCS8 = 0x3e, 304 DESC_RATEVHT2SS_MCS9 = 0x3f, 305 306 DESC_RATEVHT3SS_MCS0 = 0x40, 307 DESC_RATEVHT3SS_MCS1 = 0x41, 308 DESC_RATEVHT3SS_MCS2 = 0x42, 309 DESC_RATEVHT3SS_MCS3 = 0x43, 310 DESC_RATEVHT3SS_MCS4 = 0x44, 311 DESC_RATEVHT3SS_MCS5 = 0x45, 312 DESC_RATEVHT3SS_MCS6 = 0x46, 313 DESC_RATEVHT3SS_MCS7 = 0x47, 314 DESC_RATEVHT3SS_MCS8 = 0x48, 315 DESC_RATEVHT3SS_MCS9 = 0x49, 316 317 DESC_RATEVHT4SS_MCS0 = 0x4a, 318 DESC_RATEVHT4SS_MCS1 = 0x4b, 319 DESC_RATEVHT4SS_MCS2 = 0x4c, 320 DESC_RATEVHT4SS_MCS3 = 0x4d, 321 DESC_RATEVHT4SS_MCS4 = 0x4e, 322 DESC_RATEVHT4SS_MCS5 = 0x4f, 323 DESC_RATEVHT4SS_MCS6 = 0x50, 324 DESC_RATEVHT4SS_MCS7 = 0x51, 325 DESC_RATEVHT4SS_MCS8 = 0x52, 326 DESC_RATEVHT4SS_MCS9 = 0x53, 327 328 DESC_RATE_MAX, 329 }; 330 331 enum rtw_regulatory_domains { 332 RTW_REGD_FCC = 0, 333 RTW_REGD_MKK = 1, 334 RTW_REGD_ETSI = 2, 335 RTW_REGD_IC = 3, 336 RTW_REGD_KCC = 4, 337 RTW_REGD_ACMA = 5, 338 RTW_REGD_CHILE = 6, 339 RTW_REGD_UKRAINE = 7, 340 RTW_REGD_MEXICO = 8, 341 RTW_REGD_CN = 9, 342 RTW_REGD_WW, 343 344 RTW_REGD_MAX 345 }; 346 347 enum rtw_txq_flags { 348 RTW_TXQ_AMPDU, 349 RTW_TXQ_BLOCK_BA, 350 }; 351 352 enum rtw_flags { 353 RTW_FLAG_RUNNING, 354 RTW_FLAG_FW_RUNNING, 355 RTW_FLAG_SCANNING, 356 RTW_FLAG_INACTIVE_PS, 357 RTW_FLAG_LEISURE_PS, 358 RTW_FLAG_LEISURE_PS_DEEP, 359 RTW_FLAG_DIG_DISABLE, 360 RTW_FLAG_BUSY_TRAFFIC, 361 RTW_FLAG_WOWLAN, 362 363 NUM_OF_RTW_FLAGS, 364 }; 365 366 enum rtw_evm { 367 RTW_EVM_OFDM = 0, 368 RTW_EVM_1SS, 369 RTW_EVM_2SS_A, 370 RTW_EVM_2SS_B, 371 /* keep it last */ 372 RTW_EVM_NUM 373 }; 374 375 enum rtw_snr { 376 RTW_SNR_OFDM_A = 0, 377 RTW_SNR_OFDM_B, 378 RTW_SNR_OFDM_C, 379 RTW_SNR_OFDM_D, 380 RTW_SNR_1SS_A, 381 RTW_SNR_1SS_B, 382 RTW_SNR_1SS_C, 383 RTW_SNR_1SS_D, 384 RTW_SNR_2SS_A, 385 RTW_SNR_2SS_B, 386 RTW_SNR_2SS_C, 387 RTW_SNR_2SS_D, 388 /* keep it last */ 389 RTW_SNR_NUM 390 }; 391 392 enum rtw_wow_flags { 393 RTW_WOW_FLAG_EN_MAGIC_PKT, 394 RTW_WOW_FLAG_EN_REKEY_PKT, 395 RTW_WOW_FLAG_EN_DISCONNECT, 396 397 /* keep it last */ 398 RTW_WOW_FLAG_MAX, 399 }; 400 401 /* the power index is represented by differences, which cck-1s & ht40-1s are 402 * the base values, so for 1s's differences, there are only ht20 & ofdm 403 */ 404 struct rtw_2g_1s_pwr_idx_diff { 405 #ifdef __LITTLE_ENDIAN 406 s8 ofdm:4; 407 s8 bw20:4; 408 #else 409 s8 bw20:4; 410 s8 ofdm:4; 411 #endif 412 } __packed; 413 414 struct rtw_2g_ns_pwr_idx_diff { 415 #ifdef __LITTLE_ENDIAN 416 s8 bw20:4; 417 s8 bw40:4; 418 s8 cck:4; 419 s8 ofdm:4; 420 #else 421 s8 ofdm:4; 422 s8 cck:4; 423 s8 bw40:4; 424 s8 bw20:4; 425 #endif 426 } __packed; 427 428 struct rtw_2g_txpwr_idx { 429 u8 cck_base[6]; 430 u8 bw40_base[5]; 431 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 432 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 433 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 434 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 435 }; 436 437 struct rtw_5g_ht_1s_pwr_idx_diff { 438 #ifdef __LITTLE_ENDIAN 439 s8 ofdm:4; 440 s8 bw20:4; 441 #else 442 s8 bw20:4; 443 s8 ofdm:4; 444 #endif 445 } __packed; 446 447 struct rtw_5g_ht_ns_pwr_idx_diff { 448 #ifdef __LITTLE_ENDIAN 449 s8 bw20:4; 450 s8 bw40:4; 451 #else 452 s8 bw40:4; 453 s8 bw20:4; 454 #endif 455 } __packed; 456 457 struct rtw_5g_ofdm_ns_pwr_idx_diff { 458 #ifdef __LITTLE_ENDIAN 459 s8 ofdm_3s:4; 460 s8 ofdm_2s:4; 461 s8 ofdm_4s:4; 462 s8 res:4; 463 #else 464 s8 res:4; 465 s8 ofdm_4s:4; 466 s8 ofdm_2s:4; 467 s8 ofdm_3s:4; 468 #endif 469 } __packed; 470 471 struct rtw_5g_vht_ns_pwr_idx_diff { 472 #ifdef __LITTLE_ENDIAN 473 s8 bw160:4; 474 s8 bw80:4; 475 #else 476 s8 bw80:4; 477 s8 bw160:4; 478 #endif 479 } __packed; 480 481 struct rtw_5g_txpwr_idx { 482 u8 bw40_base[14]; 483 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 484 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 485 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 486 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 487 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 488 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 489 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 490 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 491 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 492 }; 493 494 struct rtw_txpwr_idx { 495 struct rtw_2g_txpwr_idx pwr_idx_2g; 496 struct rtw_5g_txpwr_idx pwr_idx_5g; 497 }; 498 499 struct rtw_timer_list { 500 struct timer_list timer; 501 void (*function)(void *data); 502 void *args; 503 }; 504 505 struct rtw_channel_params { 506 u8 center_chan; 507 u8 bandwidth; 508 u8 primary_chan_idx; 509 /* center channel by different available bandwidth, 510 * val of (bw > current bandwidth) is invalid 511 */ 512 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 513 }; 514 515 struct rtw_hw_reg { 516 u32 addr; 517 u32 mask; 518 }; 519 520 struct rtw_ltecoex_addr { 521 u32 ctrl; 522 u32 wdata; 523 u32 rdata; 524 }; 525 526 struct rtw_reg_domain { 527 u32 addr; 528 u32 mask; 529 #define RTW_REG_DOMAIN_MAC32 0 530 #define RTW_REG_DOMAIN_MAC16 1 531 #define RTW_REG_DOMAIN_MAC8 2 532 #define RTW_REG_DOMAIN_RF_A 3 533 #define RTW_REG_DOMAIN_RF_B 4 534 #define RTW_REG_DOMAIN_NL 0xFF 535 u8 domain; 536 }; 537 538 struct rtw_rf_sipi_addr { 539 u32 hssi_1; 540 u32 hssi_2; 541 u32 lssi_read; 542 u32 lssi_read_pi; 543 }; 544 545 struct rtw_backup_info { 546 u8 len; 547 u32 reg; 548 u32 val; 549 }; 550 551 enum rtw_vif_port_set { 552 PORT_SET_MAC_ADDR = BIT(0), 553 PORT_SET_BSSID = BIT(1), 554 PORT_SET_NET_TYPE = BIT(2), 555 PORT_SET_AID = BIT(3), 556 PORT_SET_BCN_CTRL = BIT(4), 557 }; 558 559 struct rtw_vif_port { 560 struct rtw_hw_reg mac_addr; 561 struct rtw_hw_reg bssid; 562 struct rtw_hw_reg net_type; 563 struct rtw_hw_reg aid; 564 struct rtw_hw_reg bcn_ctrl; 565 }; 566 567 struct rtw_tx_pkt_info { 568 u32 tx_pkt_size; 569 u8 offset; 570 u8 pkt_offset; 571 u8 mac_id; 572 u8 rate_id; 573 u8 rate; 574 u8 qsel; 575 u8 bw; 576 u8 sec_type; 577 u8 sn; 578 bool ampdu_en; 579 u8 ampdu_factor; 580 u8 ampdu_density; 581 u16 seq; 582 bool stbc; 583 bool ldpc; 584 bool dis_rate_fallback; 585 bool bmc; 586 bool use_rate; 587 bool ls; 588 bool fs; 589 bool short_gi; 590 bool report; 591 bool rts; 592 bool dis_qselseq; 593 bool en_hwseq; 594 u8 hw_ssn_sel; 595 bool nav_use_hdr; 596 bool bt_null; 597 }; 598 599 struct rtw_rx_pkt_stat { 600 bool phy_status; 601 bool icv_err; 602 bool crc_err; 603 bool decrypted; 604 bool is_c2h; 605 606 s32 signal_power; 607 u16 pkt_len; 608 u8 bw; 609 u8 drv_info_sz; 610 u8 shift; 611 u8 rate; 612 u8 mac_id; 613 u8 cam_id; 614 u8 ppdu_cnt; 615 u32 tsf_low; 616 s8 rx_power[RTW_RF_PATH_MAX]; 617 u8 rssi; 618 u8 rxsc; 619 s8 rx_snr[RTW_RF_PATH_MAX]; 620 u8 rx_evm[RTW_RF_PATH_MAX]; 621 s8 cfo_tail[RTW_RF_PATH_MAX]; 622 623 struct rtw_sta_info *si; 624 struct ieee80211_vif *vif; 625 }; 626 627 DECLARE_EWMA(tp, 10, 2); 628 629 struct rtw_traffic_stats { 630 /* units in bytes */ 631 u64 tx_unicast; 632 u64 rx_unicast; 633 634 /* count for packets */ 635 u64 tx_cnt; 636 u64 rx_cnt; 637 638 /* units in Mbps */ 639 u32 tx_throughput; 640 u32 rx_throughput; 641 struct ewma_tp tx_ewma_tp; 642 struct ewma_tp rx_ewma_tp; 643 }; 644 645 enum rtw_lps_mode { 646 RTW_MODE_ACTIVE = 0, 647 RTW_MODE_LPS = 1, 648 RTW_MODE_WMM_PS = 2, 649 }; 650 651 enum rtw_lps_deep_mode { 652 LPS_DEEP_MODE_NONE = 0, 653 LPS_DEEP_MODE_LCLK = 1, 654 LPS_DEEP_MODE_PG = 2, 655 }; 656 657 enum rtw_pwr_state { 658 RTW_RF_OFF = 0x0, 659 RTW_RF_ON = 0x4, 660 RTW_ALL_ON = 0xc, 661 }; 662 663 struct rtw_lps_conf { 664 enum rtw_lps_mode mode; 665 enum rtw_lps_deep_mode deep_mode; 666 enum rtw_pwr_state state; 667 u8 awake_interval; 668 u8 rlbm; 669 u8 smart_ps; 670 u8 port_id; 671 bool sec_cam_backup; 672 bool pattern_cam_backup; 673 }; 674 675 enum rtw_hw_key_type { 676 RTW_CAM_NONE = 0, 677 RTW_CAM_WEP40 = 1, 678 RTW_CAM_TKIP = 2, 679 RTW_CAM_AES = 4, 680 RTW_CAM_WEP104 = 5, 681 }; 682 683 struct rtw_cam_entry { 684 bool valid; 685 bool group; 686 u8 addr[ETH_ALEN]; 687 u8 hw_key_type; 688 struct ieee80211_key_conf *key; 689 }; 690 691 struct rtw_sec_desc { 692 /* search strategy */ 693 bool default_key_search; 694 695 u32 total_cam_num; 696 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 697 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 698 }; 699 700 struct rtw_tx_report { 701 /* protect the tx report queue */ 702 spinlock_t q_lock; 703 struct sk_buff_head queue; 704 atomic_t sn; 705 struct timer_list purge_timer; 706 }; 707 708 struct rtw_ra_report { 709 struct rate_info txrate; 710 u32 bit_rate; 711 u8 desc_rate; 712 }; 713 714 struct rtw_txq { 715 struct list_head list; 716 717 unsigned long flags; 718 unsigned long last_push; 719 }; 720 721 #define RTW_BC_MC_MACID 1 722 DECLARE_EWMA(rssi, 10, 16); 723 724 struct rtw_sta_info { 725 struct ieee80211_sta *sta; 726 struct ieee80211_vif *vif; 727 728 struct ewma_rssi avg_rssi; 729 u8 rssi_level; 730 731 u8 mac_id; 732 u8 rate_id; 733 enum rtw_bandwidth bw_mode; 734 enum rtw_rf_type rf_type; 735 enum rtw_wireless_set wireless_set; 736 u8 stbc_en:2; 737 u8 ldpc_en:2; 738 bool sgi_enable; 739 bool vht_enable; 740 bool updated; 741 u8 init_ra_lv; 742 u64 ra_mask; 743 744 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 745 746 struct rtw_ra_report ra_report; 747 748 bool use_cfg_mask; 749 struct cfg80211_bitrate_mask *mask; 750 }; 751 752 enum rtw_bfee_role { 753 RTW_BFEE_NONE, 754 RTW_BFEE_SU, 755 RTW_BFEE_MU 756 }; 757 758 struct rtw_bfee { 759 enum rtw_bfee_role role; 760 761 u16 p_aid; 762 u8 g_id; 763 u8 mac_addr[ETH_ALEN]; 764 u8 sound_dim; 765 766 /* SU-MIMO */ 767 u8 su_reg_index; 768 769 /* MU-MIMO */ 770 u16 aid; 771 }; 772 773 struct rtw_bf_info { 774 u8 bfer_mu_cnt; 775 u8 bfer_su_cnt; 776 DECLARE_BITMAP(bfer_su_reg_maping, 2); 777 u8 cur_csi_rpt_rate; 778 }; 779 780 struct rtw_vif { 781 enum rtw_net_type net_type; 782 u16 aid; 783 u8 mac_addr[ETH_ALEN]; 784 u8 bssid[ETH_ALEN]; 785 u8 port; 786 u8 bcn_ctrl; 787 struct list_head rsvd_page_list; 788 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 789 const struct rtw_vif_port *conf; 790 791 struct rtw_traffic_stats stats; 792 793 struct rtw_bfee bfee; 794 }; 795 796 struct rtw_regulatory { 797 char alpha2[2]; 798 u8 chplan; 799 u8 txpwr_regd; 800 }; 801 802 struct rtw_chip_ops { 803 int (*mac_init)(struct rtw_dev *rtwdev); 804 void (*shutdown)(struct rtw_dev *rtwdev); 805 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 806 void (*phy_set_param)(struct rtw_dev *rtwdev); 807 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 808 u8 bandwidth, u8 primary_chan_idx); 809 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 810 struct rtw_rx_pkt_stat *pkt_stat, 811 struct ieee80211_rx_status *rx_status); 812 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 813 u32 addr, u32 mask); 814 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 815 u32 addr, u32 mask, u32 data); 816 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 817 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 818 u32 size); 819 int (*set_antenna)(struct rtw_dev *rtwdev, 820 u32 antenna_tx, 821 u32 antenna_rx); 822 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 823 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 824 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 825 void (*phy_calibration)(struct rtw_dev *rtwdev); 826 void (*dpk_track)(struct rtw_dev *rtwdev); 827 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 828 void (*pwr_track)(struct rtw_dev *rtwdev); 829 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 830 struct rtw_bfee *bfee, bool enable); 831 void (*set_gid_table)(struct rtw_dev *rtwdev, 832 struct ieee80211_vif *vif, 833 struct ieee80211_bss_conf *conf); 834 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 835 u8 fixrate_en, u8 *new_rate); 836 837 /* for coex */ 838 void (*coex_set_init)(struct rtw_dev *rtwdev); 839 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 840 u8 ctrl_type, u8 pos_type); 841 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 842 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 843 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 844 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 845 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 846 }; 847 848 #define RTW_PWR_POLLING_CNT 20000 849 850 #define RTW_PWR_CMD_READ 0x00 851 #define RTW_PWR_CMD_WRITE 0x01 852 #define RTW_PWR_CMD_POLLING 0x02 853 #define RTW_PWR_CMD_DELAY 0x03 854 #define RTW_PWR_CMD_END 0x04 855 856 /* define the base address of each block */ 857 #define RTW_PWR_ADDR_MAC 0x00 858 #define RTW_PWR_ADDR_USB 0x01 859 #define RTW_PWR_ADDR_PCIE 0x02 860 #define RTW_PWR_ADDR_SDIO 0x03 861 862 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 863 #define RTW_PWR_INTF_USB_MSK BIT(1) 864 #define RTW_PWR_INTF_PCI_MSK BIT(2) 865 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 866 867 #define RTW_PWR_CUT_TEST_MSK BIT(0) 868 #define RTW_PWR_CUT_A_MSK BIT(1) 869 #define RTW_PWR_CUT_B_MSK BIT(2) 870 #define RTW_PWR_CUT_C_MSK BIT(3) 871 #define RTW_PWR_CUT_D_MSK BIT(4) 872 #define RTW_PWR_CUT_E_MSK BIT(5) 873 #define RTW_PWR_CUT_F_MSK BIT(6) 874 #define RTW_PWR_CUT_G_MSK BIT(7) 875 #define RTW_PWR_CUT_ALL_MSK 0xFF 876 877 enum rtw_pwr_seq_cmd_delay_unit { 878 RTW_PWR_DELAY_US, 879 RTW_PWR_DELAY_MS, 880 }; 881 882 struct rtw_pwr_seq_cmd { 883 u16 offset; 884 u8 cut_mask; 885 u8 intf_mask; 886 u8 base:4; 887 u8 cmd:4; 888 u8 mask; 889 u8 value; 890 }; 891 892 enum rtw_chip_ver { 893 RTW_CHIP_VER_CUT_A = 0x00, 894 RTW_CHIP_VER_CUT_B = 0x01, 895 RTW_CHIP_VER_CUT_C = 0x02, 896 RTW_CHIP_VER_CUT_D = 0x03, 897 RTW_CHIP_VER_CUT_E = 0x04, 898 RTW_CHIP_VER_CUT_F = 0x05, 899 RTW_CHIP_VER_CUT_G = 0x06, 900 }; 901 902 #define RTW_INTF_PHY_PLATFORM_ALL 0 903 904 enum rtw_intf_phy_cut { 905 RTW_INTF_PHY_CUT_A = BIT(0), 906 RTW_INTF_PHY_CUT_B = BIT(1), 907 RTW_INTF_PHY_CUT_C = BIT(2), 908 RTW_INTF_PHY_CUT_D = BIT(3), 909 RTW_INTF_PHY_CUT_E = BIT(4), 910 RTW_INTF_PHY_CUT_F = BIT(5), 911 RTW_INTF_PHY_CUT_G = BIT(6), 912 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 913 }; 914 915 enum rtw_ip_sel { 916 RTW_IP_SEL_PHY = 0, 917 RTW_IP_SEL_MAC = 1, 918 RTW_IP_SEL_DBI = 2, 919 920 RTW_IP_SEL_UNDEF = 0xFFFF 921 }; 922 923 enum rtw_pq_map_id { 924 RTW_PQ_MAP_VO = 0x0, 925 RTW_PQ_MAP_VI = 0x1, 926 RTW_PQ_MAP_BE = 0x2, 927 RTW_PQ_MAP_BK = 0x3, 928 RTW_PQ_MAP_MG = 0x4, 929 RTW_PQ_MAP_HI = 0x5, 930 RTW_PQ_MAP_NUM = 0x6, 931 932 RTW_PQ_MAP_UNDEF, 933 }; 934 935 enum rtw_dma_mapping { 936 RTW_DMA_MAPPING_EXTRA = 0, 937 RTW_DMA_MAPPING_LOW = 1, 938 RTW_DMA_MAPPING_NORMAL = 2, 939 RTW_DMA_MAPPING_HIGH = 3, 940 941 RTW_DMA_MAPPING_MAX, 942 RTW_DMA_MAPPING_UNDEF, 943 }; 944 945 struct rtw_rqpn { 946 enum rtw_dma_mapping dma_map_vo; 947 enum rtw_dma_mapping dma_map_vi; 948 enum rtw_dma_mapping dma_map_be; 949 enum rtw_dma_mapping dma_map_bk; 950 enum rtw_dma_mapping dma_map_mg; 951 enum rtw_dma_mapping dma_map_hi; 952 }; 953 954 struct rtw_prioq_addr { 955 u32 rsvd; 956 u32 avail; 957 }; 958 959 struct rtw_prioq_addrs { 960 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 961 bool wsize; 962 }; 963 964 struct rtw_page_table { 965 u16 hq_num; 966 u16 nq_num; 967 u16 lq_num; 968 u16 exq_num; 969 u16 gapq_num; 970 }; 971 972 struct rtw_intf_phy_para { 973 u16 offset; 974 u16 value; 975 u16 ip_sel; 976 u16 cut_mask; 977 u16 platform; 978 }; 979 980 struct rtw_wow_pattern { 981 u16 crc; 982 u8 type; 983 u8 valid; 984 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 985 }; 986 987 struct rtw_pno_request { 988 bool inited; 989 u32 match_set_cnt; 990 struct cfg80211_match_set *match_sets; 991 u8 channel_cnt; 992 struct ieee80211_channel *channels; 993 struct cfg80211_sched_scan_plan scan_plan; 994 }; 995 996 struct rtw_wow_param { 997 struct ieee80211_vif *wow_vif; 998 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 999 u8 txpause; 1000 u8 pattern_cnt; 1001 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1002 1003 bool ips_enabled; 1004 struct rtw_pno_request pno_req; 1005 }; 1006 1007 struct rtw_intf_phy_para_table { 1008 const struct rtw_intf_phy_para *usb2_para; 1009 const struct rtw_intf_phy_para *usb3_para; 1010 const struct rtw_intf_phy_para *gen1_para; 1011 const struct rtw_intf_phy_para *gen2_para; 1012 u8 n_usb2_para; 1013 u8 n_usb3_para; 1014 u8 n_gen1_para; 1015 u8 n_gen2_para; 1016 }; 1017 1018 struct rtw_table { 1019 const void *data; 1020 const u32 size; 1021 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1022 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1023 u32 addr, u32 data); 1024 enum rtw_rf_path rf_path; 1025 }; 1026 1027 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1028 const struct rtw_table *tbl) 1029 { 1030 (*tbl->parse)(rtwdev, tbl); 1031 } 1032 1033 enum rtw_rfe_fem { 1034 RTW_RFE_IFEM, 1035 RTW_RFE_EFEM, 1036 RTW_RFE_IFEM2G_EFEM5G, 1037 RTW_RFE_NUM, 1038 }; 1039 1040 struct rtw_rfe_def { 1041 const struct rtw_table *phy_pg_tbl; 1042 const struct rtw_table *txpwr_lmt_tbl; 1043 }; 1044 1045 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1046 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1047 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1048 } 1049 1050 #define RTW_PWR_TRK_5G_1 0 1051 #define RTW_PWR_TRK_5G_2 1 1052 #define RTW_PWR_TRK_5G_3 2 1053 #define RTW_PWR_TRK_5G_NUM 3 1054 1055 #define RTW_PWR_TRK_TBL_SZ 30 1056 1057 /* This table stores the values of TX power that will be adjusted by power 1058 * tracking. 1059 * 1060 * For 5G bands, there are 3 different settings. 1061 * For 2G there are cck rate and ofdm rate with different settings. 1062 */ 1063 struct rtw_pwr_track_tbl { 1064 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1065 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1066 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1067 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1068 const u8 *pwrtrk_2gb_n; 1069 const u8 *pwrtrk_2gb_p; 1070 const u8 *pwrtrk_2ga_n; 1071 const u8 *pwrtrk_2ga_p; 1072 const u8 *pwrtrk_2g_cckb_n; 1073 const u8 *pwrtrk_2g_cckb_p; 1074 const u8 *pwrtrk_2g_ccka_n; 1075 const u8 *pwrtrk_2g_ccka_p; 1076 const s8 *pwrtrk_xtal_n; 1077 const s8 *pwrtrk_xtal_p; 1078 }; 1079 1080 enum rtw_wlan_cpu { 1081 RTW_WCPU_11AC, 1082 RTW_WCPU_11N, 1083 }; 1084 1085 /* hardware configuration for each IC */ 1086 struct rtw_chip_info { 1087 struct rtw_chip_ops *ops; 1088 u8 id; 1089 1090 const char *fw_name; 1091 enum rtw_wlan_cpu wlan_cpu; 1092 u8 tx_pkt_desc_sz; 1093 u8 tx_buf_desc_sz; 1094 u8 rx_pkt_desc_sz; 1095 u8 rx_buf_desc_sz; 1096 u32 phy_efuse_size; 1097 u32 log_efuse_size; 1098 u32 ptct_efuse_size; 1099 u32 txff_size; 1100 u32 rxff_size; 1101 u8 band; 1102 u8 page_size; 1103 u8 csi_buf_pg_num; 1104 u8 dig_max; 1105 u8 dig_min; 1106 u8 txgi_factor; 1107 bool is_pwr_by_rate_dec; 1108 bool rx_ldpc; 1109 u8 max_power_index; 1110 1111 bool ht_supported; 1112 bool vht_supported; 1113 u8 lps_deep_mode_supported; 1114 1115 /* init values */ 1116 u8 sys_func_en; 1117 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1118 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1119 const struct rtw_rqpn *rqpn_table; 1120 const struct rtw_prioq_addrs *prioq_addrs; 1121 const struct rtw_page_table *page_table; 1122 const struct rtw_intf_phy_para_table *intf_table; 1123 1124 const struct rtw_hw_reg *dig; 1125 const struct rtw_hw_reg *dig_cck; 1126 u32 rf_base_addr[2]; 1127 u32 rf_sipi_addr[2]; 1128 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1129 u8 fix_rf_phy_num; 1130 const struct rtw_ltecoex_addr *ltecoex_addr; 1131 1132 const struct rtw_table *mac_tbl; 1133 const struct rtw_table *agc_tbl; 1134 const struct rtw_table *bb_tbl; 1135 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1136 const struct rtw_table *rfk_init_tbl; 1137 1138 const struct rtw_rfe_def *rfe_defs; 1139 u32 rfe_defs_size; 1140 1141 bool en_dis_dpd; 1142 u16 dpd_ratemask; 1143 u8 iqk_threshold; 1144 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1145 1146 u8 bfer_su_max_num; 1147 u8 bfer_mu_max_num; 1148 1149 const char *wow_fw_name; 1150 const struct wiphy_wowlan_support *wowlan_stub; 1151 const u8 max_sched_scan_ssids; 1152 1153 /* for 8821c set channel */ 1154 u32 ch_param[3]; 1155 1156 /* coex paras */ 1157 u32 coex_para_ver; 1158 u8 bt_desired_ver; 1159 bool scbd_support; 1160 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1161 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1162 u8 bt_rssi_type; 1163 u8 ant_isolation; 1164 u8 rssi_tolerance; 1165 u8 table_sant_num; 1166 u8 table_nsant_num; 1167 u8 tdma_sant_num; 1168 u8 tdma_nsant_num; 1169 u8 bt_afh_span_bw20; 1170 u8 bt_afh_span_bw40; 1171 u8 afh_5g_num; 1172 u8 wl_rf_para_num; 1173 u8 coex_info_hw_regs_num; 1174 const u8 *bt_rssi_step; 1175 const u8 *wl_rssi_step; 1176 const struct coex_table_para *table_nsant; 1177 const struct coex_table_para *table_sant; 1178 const struct coex_tdma_para *tdma_sant; 1179 const struct coex_tdma_para *tdma_nsant; 1180 const struct coex_rf_para *wl_rf_para_tx; 1181 const struct coex_rf_para *wl_rf_para_rx; 1182 const struct coex_5g_afh_map *afh_5g; 1183 const struct rtw_hw_reg *btg_reg; 1184 const struct rtw_reg_domain *coex_info_hw_regs; 1185 }; 1186 1187 enum rtw_coex_bt_state_cnt { 1188 COEX_CNT_BT_RETRY, 1189 COEX_CNT_BT_REINIT, 1190 COEX_CNT_BT_REENABLE, 1191 COEX_CNT_BT_POPEVENT, 1192 COEX_CNT_BT_SETUPLINK, 1193 COEX_CNT_BT_IGNWLANACT, 1194 COEX_CNT_BT_INQ, 1195 COEX_CNT_BT_PAGE, 1196 COEX_CNT_BT_ROLESWITCH, 1197 COEX_CNT_BT_AFHUPDATE, 1198 COEX_CNT_BT_INFOUPDATE, 1199 COEX_CNT_BT_IQK, 1200 COEX_CNT_BT_IQKFAIL, 1201 1202 COEX_CNT_BT_MAX 1203 }; 1204 1205 enum rtw_coex_wl_state_cnt { 1206 COEX_CNT_WL_CONNPKT, 1207 COEX_CNT_WL_COEXRUN, 1208 COEX_CNT_WL_NOISY0, 1209 COEX_CNT_WL_NOISY1, 1210 COEX_CNT_WL_NOISY2, 1211 COEX_CNT_WL_5MS_NOEXTEND, 1212 COEX_CNT_WL_FW_NOTIFY, 1213 1214 COEX_CNT_WL_MAX 1215 }; 1216 1217 struct rtw_coex_rfe { 1218 bool ant_switch_exist; 1219 bool ant_switch_diversity; 1220 bool ant_switch_with_bt; 1221 u8 rfe_module_type; 1222 u8 ant_switch_polarity; 1223 1224 /* true if WLG at BTG, else at WLAG */ 1225 bool wlg_at_btg; 1226 }; 1227 1228 struct rtw_coex_dm { 1229 bool cur_ps_tdma_on; 1230 bool cur_wl_rx_low_gain_en; 1231 bool ignore_wl_act; 1232 1233 u8 reason; 1234 u8 bt_rssi_state[4]; 1235 u8 wl_rssi_state[4]; 1236 u8 wl_ch_info[3]; 1237 u8 cur_ps_tdma; 1238 u8 cur_table; 1239 u8 ps_tdma_para[5]; 1240 u8 cur_bt_pwr_lvl; 1241 u8 cur_bt_lna_lvl; 1242 u8 cur_wl_pwr_lvl; 1243 u8 bt_status; 1244 u32 cur_ant_pos_type; 1245 u32 cur_switch_status; 1246 u32 setting_tdma; 1247 }; 1248 1249 #define COEX_BTINFO_SRC_WL_FW 0x0 1250 #define COEX_BTINFO_SRC_BT_RSP 0x1 1251 #define COEX_BTINFO_SRC_BT_ACT 0x2 1252 #define COEX_BTINFO_SRC_BT_IQK 0x3 1253 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1254 #define COEX_BTINFO_SRC_MAX 0x5 1255 1256 #define COEX_INFO_FTP BIT(7) 1257 #define COEX_INFO_A2DP BIT(6) 1258 #define COEX_INFO_HID BIT(5) 1259 #define COEX_INFO_SCO_BUSY BIT(4) 1260 #define COEX_INFO_ACL_BUSY BIT(3) 1261 #define COEX_INFO_INQ_PAGE BIT(2) 1262 #define COEX_INFO_SCO_ESCO BIT(1) 1263 #define COEX_INFO_CONNECTION BIT(0) 1264 #define COEX_BTINFO_LENGTH_MAX 10 1265 1266 struct rtw_coex_stat { 1267 bool bt_disabled; 1268 bool bt_disabled_pre; 1269 bool bt_link_exist; 1270 bool bt_whck_test; 1271 bool bt_inq_page; 1272 bool bt_inq_remain; 1273 bool bt_inq; 1274 bool bt_page; 1275 bool bt_ble_voice; 1276 bool bt_ble_exist; 1277 bool bt_hfp_exist; 1278 bool bt_a2dp_exist; 1279 bool bt_hid_exist; 1280 bool bt_pan_exist; /* PAN or OPP */ 1281 bool bt_opp_exist; /* OPP only */ 1282 bool bt_acl_busy; 1283 bool bt_fix_2M; 1284 bool bt_setup_link; 1285 bool bt_multi_link; 1286 bool bt_a2dp_sink; 1287 bool bt_a2dp_active; 1288 bool bt_reenable; 1289 bool bt_ble_scan_en; 1290 bool bt_init_scan; 1291 bool bt_slave; 1292 bool bt_418_hid_exist; 1293 bool bt_mailbox_reply; 1294 1295 bool wl_under_lps; 1296 bool wl_under_ips; 1297 bool wl_hi_pri_task1; 1298 bool wl_hi_pri_task2; 1299 bool wl_force_lps_ctrl; 1300 bool wl_gl_busy; 1301 bool wl_linkscan_proc; 1302 bool wl_ps_state_fail; 1303 bool wl_tx_limit_en; 1304 bool wl_ampdu_limit_en; 1305 bool wl_connected; 1306 bool wl_slot_extend; 1307 bool wl_cck_lock; 1308 bool wl_cck_lock_pre; 1309 bool wl_cck_lock_ever; 1310 1311 u32 bt_supported_version; 1312 u32 bt_supported_feature; 1313 u32 patch_ver; 1314 u16 bt_reg_vendor_ae; 1315 u16 bt_reg_vendor_ac; 1316 s8 bt_rssi; 1317 u8 kt_ver; 1318 u8 gnt_workaround_state; 1319 u8 tdma_timer_base; 1320 u8 bt_profile_num; 1321 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1322 u8 bt_info_lb2; 1323 u8 bt_info_lb3; 1324 u8 bt_info_hb0; 1325 u8 bt_info_hb1; 1326 u8 bt_info_hb2; 1327 u8 bt_info_hb3; 1328 u8 bt_ble_scan_type; 1329 u8 bt_hid_pair_num; 1330 u8 bt_hid_slot; 1331 u8 bt_a2dp_bitpool; 1332 u8 bt_iqk_state; 1333 1334 u8 wl_noisy_level; 1335 u8 wl_fw_dbg_info[10]; 1336 u8 wl_fw_dbg_info_pre[10]; 1337 u8 wl_coex_mode; 1338 u8 ampdu_max_time; 1339 u8 wl_tput_dir; 1340 1341 u16 score_board; 1342 u16 retry_limit; 1343 1344 /* counters to record bt states */ 1345 u32 cnt_bt[COEX_CNT_BT_MAX]; 1346 1347 /* counters to record wifi states */ 1348 u32 cnt_wl[COEX_CNT_WL_MAX]; 1349 1350 u32 darfrc; 1351 u32 darfrch; 1352 }; 1353 1354 struct rtw_coex { 1355 /* protects coex info request section */ 1356 struct mutex mutex; 1357 struct sk_buff_head queue; 1358 wait_queue_head_t wait; 1359 1360 bool under_5g; 1361 bool stop_dm; 1362 bool freeze; 1363 bool freerun; 1364 bool wl_rf_off; 1365 1366 struct rtw_coex_stat stat; 1367 struct rtw_coex_dm dm; 1368 struct rtw_coex_rfe rfe; 1369 1370 struct delayed_work bt_relink_work; 1371 struct delayed_work bt_reenable_work; 1372 struct delayed_work defreeze_work; 1373 struct delayed_work wl_remain_work; 1374 struct delayed_work bt_remain_work; 1375 }; 1376 1377 #define DPK_RF_REG_NUM 7 1378 #define DPK_RF_PATH_NUM 2 1379 #define DPK_BB_REG_NUM 18 1380 #define DPK_CHANNEL_WIDTH_80 1 1381 1382 DECLARE_EWMA(thermal, 10, 4); 1383 1384 struct rtw_dpk_info { 1385 bool is_dpk_pwr_on; 1386 bool is_reload; 1387 1388 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1389 1390 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1391 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1392 1393 u32 gnt_control; 1394 u32 gnt_value; 1395 1396 u8 result[RTW_RF_PATH_MAX]; 1397 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1398 u32 coef[RTW_RF_PATH_MAX][20]; 1399 u16 dpk_gs[RTW_RF_PATH_MAX]; 1400 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1401 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1402 1403 u8 dpk_band; 1404 u8 dpk_ch; 1405 u8 dpk_bw; 1406 }; 1407 1408 struct rtw_phy_cck_pd_reg { 1409 u32 reg_pd; 1410 u32 mask_pd; 1411 u32 reg_cs; 1412 u32 mask_cs; 1413 }; 1414 1415 #define DACK_MSBK_BACKUP_NUM 0xf 1416 #define DACK_DCK_BACKUP_NUM 0x2 1417 1418 struct rtw_swing_table { 1419 const u8 *p[RTW_RF_PATH_MAX]; 1420 const u8 *n[RTW_RF_PATH_MAX]; 1421 }; 1422 1423 struct rtw_pkt_count { 1424 u16 num_bcn_pkt; 1425 u16 num_qry_pkt[DESC_RATE_MAX]; 1426 }; 1427 1428 DECLARE_EWMA(evm, 10, 4); 1429 DECLARE_EWMA(snr, 10, 4); 1430 1431 struct rtw_iqk_info { 1432 bool done; 1433 struct { 1434 u32 s1_x; 1435 u32 s1_y; 1436 u32 s0_x; 1437 u32 s0_y; 1438 } result; 1439 }; 1440 1441 struct rtw_dm_info { 1442 u32 cck_fa_cnt; 1443 u32 ofdm_fa_cnt; 1444 u32 total_fa_cnt; 1445 u32 cck_cca_cnt; 1446 u32 ofdm_cca_cnt; 1447 u32 total_cca_cnt; 1448 1449 u32 cck_ok_cnt; 1450 u32 cck_err_cnt; 1451 u32 ofdm_ok_cnt; 1452 u32 ofdm_err_cnt; 1453 u32 ht_ok_cnt; 1454 u32 ht_err_cnt; 1455 u32 vht_ok_cnt; 1456 u32 vht_err_cnt; 1457 1458 u8 min_rssi; 1459 u8 pre_min_rssi; 1460 u16 fa_history[4]; 1461 u8 igi_history[4]; 1462 u8 igi_bitmap; 1463 bool damping; 1464 u8 damping_cnt; 1465 u8 damping_rssi; 1466 1467 u8 cck_gi_u_bnd; 1468 u8 cck_gi_l_bnd; 1469 1470 u8 tx_rate; 1471 u8 thermal_avg[RTW_RF_PATH_MAX]; 1472 u8 thermal_meter_k; 1473 s8 delta_power_index[RTW_RF_PATH_MAX]; 1474 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1475 u8 default_ofdm_index; 1476 bool pwr_trk_triggered; 1477 bool pwr_trk_init_trigger; 1478 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1479 s8 txagc_remnant_cck; 1480 s8 txagc_remnant_ofdm; 1481 1482 /* backup dack results for each path and I/Q */ 1483 u32 dack_adck[RTW_RF_PATH_MAX]; 1484 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1485 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1486 1487 struct rtw_dpk_info dpk_info; 1488 1489 /* [bandwidth 0:20M/1:40M][number of path] */ 1490 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1491 u32 cck_fa_avg; 1492 u8 cck_pd_default; 1493 1494 /* save the last rx phy status for debug */ 1495 s8 rx_snr[RTW_RF_PATH_MAX]; 1496 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1497 s16 cfo_tail[RTW_RF_PATH_MAX]; 1498 u8 rssi[RTW_RF_PATH_MAX]; 1499 u8 curr_rx_rate; 1500 struct rtw_pkt_count cur_pkt_count; 1501 struct rtw_pkt_count last_pkt_count; 1502 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1503 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1504 1505 struct rtw_iqk_info iqk; 1506 }; 1507 1508 struct rtw_efuse { 1509 u32 size; 1510 u32 physical_size; 1511 u32 logical_size; 1512 u32 protect_size; 1513 1514 u8 addr[ETH_ALEN]; 1515 u8 channel_plan; 1516 u8 country_code[2]; 1517 u8 rf_board_option; 1518 u8 rfe_option; 1519 u8 power_track_type; 1520 u8 thermal_meter[RTW_RF_PATH_MAX]; 1521 u8 thermal_meter_k; 1522 u8 crystal_cap; 1523 u8 ant_div_cfg; 1524 u8 ant_div_type; 1525 u8 regd; 1526 u8 afe; 1527 1528 u8 lna_type_2g; 1529 u8 lna_type_5g; 1530 u8 glna_type; 1531 u8 alna_type; 1532 bool ext_lna_2g; 1533 bool ext_lna_5g; 1534 u8 pa_type_2g; 1535 u8 pa_type_5g; 1536 u8 gpa_type; 1537 u8 apa_type; 1538 bool ext_pa_2g; 1539 bool ext_pa_5g; 1540 u8 tx_bb_swing_setting_2g; 1541 u8 tx_bb_swing_setting_5g; 1542 1543 bool btcoex; 1544 /* bt share antenna with wifi */ 1545 bool share_ant; 1546 u8 bt_setting; 1547 1548 struct { 1549 u8 hci; 1550 u8 bw; 1551 u8 ptcl; 1552 u8 nss; 1553 u8 ant_num; 1554 } hw_cap; 1555 1556 struct rtw_txpwr_idx txpwr_idx_table[4]; 1557 }; 1558 1559 struct rtw_phy_cond { 1560 #ifdef __LITTLE_ENDIAN 1561 u32 rfe:8; 1562 u32 intf:4; 1563 u32 pkg:4; 1564 u32 plat:4; 1565 u32 intf_rsvd:4; 1566 u32 cut:4; 1567 u32 branch:2; 1568 u32 neg:1; 1569 u32 pos:1; 1570 #else 1571 u32 pos:1; 1572 u32 neg:1; 1573 u32 branch:2; 1574 u32 cut:4; 1575 u32 intf_rsvd:4; 1576 u32 plat:4; 1577 u32 pkg:4; 1578 u32 intf:4; 1579 u32 rfe:8; 1580 #endif 1581 /* for intf:4 */ 1582 #define INTF_PCIE BIT(0) 1583 #define INTF_USB BIT(1) 1584 #define INTF_SDIO BIT(2) 1585 /* for branch:2 */ 1586 #define BRANCH_IF 0 1587 #define BRANCH_ELIF 1 1588 #define BRANCH_ELSE 2 1589 #define BRANCH_ENDIF 3 1590 }; 1591 1592 struct rtw_fifo_conf { 1593 /* tx fifo information */ 1594 u16 rsvd_boundary; 1595 u16 rsvd_pg_num; 1596 u16 rsvd_drv_pg_num; 1597 u16 txff_pg_num; 1598 u16 acq_pg_num; 1599 u16 rsvd_drv_addr; 1600 u16 rsvd_h2c_info_addr; 1601 u16 rsvd_h2c_sta_info_addr; 1602 u16 rsvd_h2cq_addr; 1603 u16 rsvd_cpu_instr_addr; 1604 u16 rsvd_fw_txbuf_addr; 1605 u16 rsvd_csibuf_addr; 1606 const struct rtw_rqpn *rqpn; 1607 }; 1608 1609 struct rtw_fw_state { 1610 const struct firmware *firmware; 1611 struct rtw_dev *rtwdev; 1612 struct completion completion; 1613 u16 version; 1614 u8 sub_version; 1615 u8 sub_index; 1616 u16 h2c_version; 1617 }; 1618 1619 struct rtw_hal { 1620 u32 rcr; 1621 1622 u32 chip_version; 1623 u8 cut_version; 1624 u8 mp_chip; 1625 u8 oem_id; 1626 struct rtw_phy_cond phy_cond; 1627 1628 u8 ps_mode; 1629 u8 current_channel; 1630 u8 current_band_width; 1631 u8 current_band_type; 1632 1633 /* center channel for different available bandwidth, 1634 * val of (bw > current_band_width) is invalid 1635 */ 1636 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1637 1638 u8 sec_ch_offset; 1639 u8 rf_type; 1640 u8 rf_path_num; 1641 u8 rf_phy_num; 1642 u32 antenna_tx; 1643 u32 antenna_rx; 1644 u8 bfee_sts_cap; 1645 1646 /* protect tx power section */ 1647 struct mutex tx_power_mutex; 1648 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1649 [DESC_RATE_MAX]; 1650 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1651 [DESC_RATE_MAX]; 1652 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1653 [RTW_RATE_SECTION_MAX]; 1654 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1655 [RTW_RATE_SECTION_MAX]; 1656 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1657 [RTW_CHANNEL_WIDTH_MAX] 1658 [RTW_RATE_SECTION_MAX] 1659 [RTW_MAX_CHANNEL_NUM_2G]; 1660 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1661 [RTW_CHANNEL_WIDTH_MAX] 1662 [RTW_RATE_SECTION_MAX] 1663 [RTW_MAX_CHANNEL_NUM_5G]; 1664 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1665 [DESC_RATE_MAX]; 1666 }; 1667 1668 struct rtw_dev { 1669 struct ieee80211_hw *hw; 1670 struct device *dev; 1671 1672 struct rtw_hci hci; 1673 1674 struct rtw_chip_info *chip; 1675 struct rtw_hal hal; 1676 struct rtw_fifo_conf fifo; 1677 struct rtw_fw_state fw; 1678 struct rtw_efuse efuse; 1679 struct rtw_sec_desc sec; 1680 struct rtw_traffic_stats stats; 1681 struct rtw_regulatory regd; 1682 struct rtw_bf_info bf_info; 1683 1684 struct rtw_dm_info dm_info; 1685 struct rtw_coex coex; 1686 1687 /* ensures exclusive access from mac80211 callbacks */ 1688 struct mutex mutex; 1689 1690 /* read/write rf register */ 1691 spinlock_t rf_lock; 1692 1693 /* watch dog every 2 sec */ 1694 struct delayed_work watch_dog_work; 1695 u32 watch_dog_cnt; 1696 1697 struct list_head rsvd_page_list; 1698 1699 /* c2h cmd queue & handler work */ 1700 struct sk_buff_head c2h_queue; 1701 struct work_struct c2h_work; 1702 1703 /* used to protect txqs list */ 1704 spinlock_t txq_lock; 1705 struct list_head txqs; 1706 struct tasklet_struct tx_tasklet; 1707 struct work_struct ba_work; 1708 1709 struct rtw_tx_report tx_report; 1710 1711 struct { 1712 /* incicate the mail box to use with fw */ 1713 u8 last_box_num; 1714 /* protect to send h2c to fw */ 1715 spinlock_t lock; 1716 u32 seq; 1717 } h2c; 1718 1719 /* lps power state & handler work */ 1720 struct rtw_lps_conf lps_conf; 1721 bool ps_enabled; 1722 1723 struct dentry *debugfs; 1724 1725 u8 sta_cnt; 1726 u32 rts_threshold; 1727 1728 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1729 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1730 1731 u8 mp_mode; 1732 1733 struct rtw_fw_state wow_fw; 1734 struct rtw_wow_param wow; 1735 1736 bool need_rfk; 1737 1738 /* hci related data, must be last */ 1739 u8 priv[] __aligned(sizeof(void *)); 1740 }; 1741 1742 #include "hci.h" 1743 1744 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1745 { 1746 return !!rtwdev->sta_cnt; 1747 } 1748 1749 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1750 { 1751 void *p = rtwtxq; 1752 1753 return container_of(p, struct ieee80211_txq, drv_priv); 1754 } 1755 1756 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1757 { 1758 void *p = rtwvif; 1759 1760 return container_of(p, struct ieee80211_vif, drv_priv); 1761 } 1762 1763 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1764 struct cfg80211_ssid *b) 1765 { 1766 if (!a || !b || a->ssid_len != b->ssid_len) 1767 return false; 1768 1769 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1770 return false; 1771 1772 return true; 1773 } 1774 1775 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1776 { 1777 if (rtwdev->chip->ops->efuse_grant) 1778 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1779 } 1780 1781 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1782 { 1783 if (rtwdev->chip->ops->efuse_grant) 1784 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1785 } 1786 1787 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1788 { 1789 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1790 } 1791 1792 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1793 { 1794 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 1795 } 1796 1797 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 1798 { 1799 return rtwdev->chip->rx_ldpc; 1800 } 1801 1802 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1803 struct rtw_channel_params *ch_param); 1804 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1805 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1806 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1807 void rtw_restore_reg(struct rtw_dev *rtwdev, 1808 struct rtw_backup_info *bckp, u32 num); 1809 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1810 void rtw_set_channel(struct rtw_dev *rtwdev); 1811 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 1812 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1813 u32 config); 1814 void rtw_tx_report_purge_timer(struct timer_list *t); 1815 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1816 int rtw_core_start(struct rtw_dev *rtwdev); 1817 void rtw_core_stop(struct rtw_dev *rtwdev); 1818 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1819 int rtw_core_init(struct rtw_dev *rtwdev); 1820 void rtw_core_deinit(struct rtw_dev *rtwdev); 1821 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1822 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1823 u16 rtw_desc_to_bitrate(u8 desc_rate); 1824 1825 #endif 1826