1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #ifndef _GVT_INTERRUPT_H_ 33 #define _GVT_INTERRUPT_H_ 34 35 #include <linux/types.h> 36 37 enum intel_gvt_event_type { 38 RCS_MI_USER_INTERRUPT = 0, 39 RCS_DEBUG, 40 RCS_MMIO_SYNC_FLUSH, 41 RCS_CMD_STREAMER_ERR, 42 RCS_PIPE_CONTROL, 43 RCS_L3_PARITY_ERR, 44 RCS_WATCHDOG_EXCEEDED, 45 RCS_PAGE_DIRECTORY_FAULT, 46 RCS_AS_CONTEXT_SWITCH, 47 RCS_MONITOR_BUFF_HALF_FULL, 48 49 VCS_MI_USER_INTERRUPT, 50 VCS_MMIO_SYNC_FLUSH, 51 VCS_CMD_STREAMER_ERR, 52 VCS_MI_FLUSH_DW, 53 VCS_WATCHDOG_EXCEEDED, 54 VCS_PAGE_DIRECTORY_FAULT, 55 VCS_AS_CONTEXT_SWITCH, 56 57 VCS2_MI_USER_INTERRUPT, 58 VCS2_MI_FLUSH_DW, 59 VCS2_AS_CONTEXT_SWITCH, 60 61 BCS_MI_USER_INTERRUPT, 62 BCS_MMIO_SYNC_FLUSH, 63 BCS_CMD_STREAMER_ERR, 64 BCS_MI_FLUSH_DW, 65 BCS_PAGE_DIRECTORY_FAULT, 66 BCS_AS_CONTEXT_SWITCH, 67 68 VECS_MI_USER_INTERRUPT, 69 VECS_MI_FLUSH_DW, 70 VECS_AS_CONTEXT_SWITCH, 71 72 PIPE_A_FIFO_UNDERRUN, 73 PIPE_B_FIFO_UNDERRUN, 74 PIPE_A_CRC_ERR, 75 PIPE_B_CRC_ERR, 76 PIPE_A_CRC_DONE, 77 PIPE_B_CRC_DONE, 78 PIPE_A_ODD_FIELD, 79 PIPE_B_ODD_FIELD, 80 PIPE_A_EVEN_FIELD, 81 PIPE_B_EVEN_FIELD, 82 PIPE_A_LINE_COMPARE, 83 PIPE_B_LINE_COMPARE, 84 PIPE_C_LINE_COMPARE, 85 PIPE_A_VBLANK, 86 PIPE_B_VBLANK, 87 PIPE_C_VBLANK, 88 PIPE_A_VSYNC, 89 PIPE_B_VSYNC, 90 PIPE_C_VSYNC, 91 PRIMARY_A_FLIP_DONE, 92 PRIMARY_B_FLIP_DONE, 93 PRIMARY_C_FLIP_DONE, 94 SPRITE_A_FLIP_DONE, 95 SPRITE_B_FLIP_DONE, 96 SPRITE_C_FLIP_DONE, 97 98 PCU_THERMAL, 99 PCU_PCODE2DRIVER_MAILBOX, 100 101 DPST_PHASE_IN, 102 DPST_HISTOGRAM, 103 GSE, 104 DP_A_HOTPLUG, 105 AUX_CHANNEL_A, 106 PERF_COUNTER, 107 POISON, 108 GTT_FAULT, 109 ERROR_INTERRUPT_COMBINED, 110 111 FDI_RX_INTERRUPTS_TRANSCODER_A, 112 AUDIO_CP_CHANGE_TRANSCODER_A, 113 AUDIO_CP_REQUEST_TRANSCODER_A, 114 FDI_RX_INTERRUPTS_TRANSCODER_B, 115 AUDIO_CP_CHANGE_TRANSCODER_B, 116 AUDIO_CP_REQUEST_TRANSCODER_B, 117 FDI_RX_INTERRUPTS_TRANSCODER_C, 118 AUDIO_CP_CHANGE_TRANSCODER_C, 119 AUDIO_CP_REQUEST_TRANSCODER_C, 120 ERR_AND_DBG, 121 GMBUS, 122 SDVO_B_HOTPLUG, 123 CRT_HOTPLUG, 124 DP_B_HOTPLUG, 125 DP_C_HOTPLUG, 126 DP_D_HOTPLUG, 127 AUX_CHANNEL_B, 128 AUX_CHANNEL_C, 129 AUX_CHANNEL_D, 130 AUDIO_POWER_STATE_CHANGE_B, 131 AUDIO_POWER_STATE_CHANGE_C, 132 AUDIO_POWER_STATE_CHANGE_D, 133 134 INTEL_GVT_EVENT_RESERVED, 135 INTEL_GVT_EVENT_MAX, 136 }; 137 138 struct intel_gvt_irq; 139 struct intel_gvt; 140 struct intel_vgpu; 141 142 typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq, 143 enum intel_gvt_event_type event, struct intel_vgpu *vgpu); 144 145 struct intel_gvt_irq_ops { 146 void (*init_irq)(struct intel_gvt_irq *irq); 147 void (*check_pending_irq)(struct intel_vgpu *vgpu); 148 }; 149 150 /* the list of physical interrupt control register groups */ 151 enum intel_gvt_irq_type { 152 INTEL_GVT_IRQ_INFO_GT, 153 INTEL_GVT_IRQ_INFO_DPY, 154 INTEL_GVT_IRQ_INFO_PCH, 155 INTEL_GVT_IRQ_INFO_PM, 156 157 INTEL_GVT_IRQ_INFO_MASTER, 158 INTEL_GVT_IRQ_INFO_GT0, 159 INTEL_GVT_IRQ_INFO_GT1, 160 INTEL_GVT_IRQ_INFO_GT2, 161 INTEL_GVT_IRQ_INFO_GT3, 162 INTEL_GVT_IRQ_INFO_DE_PIPE_A, 163 INTEL_GVT_IRQ_INFO_DE_PIPE_B, 164 INTEL_GVT_IRQ_INFO_DE_PIPE_C, 165 INTEL_GVT_IRQ_INFO_DE_PORT, 166 INTEL_GVT_IRQ_INFO_DE_MISC, 167 INTEL_GVT_IRQ_INFO_AUD, 168 INTEL_GVT_IRQ_INFO_PCU, 169 170 INTEL_GVT_IRQ_INFO_MAX, 171 }; 172 173 #define INTEL_GVT_IRQ_BITWIDTH 32 174 175 /* device specific interrupt bit definitions */ 176 struct intel_gvt_irq_info { 177 char *name; 178 i915_reg_t reg_base; 179 enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; 180 unsigned long warned; 181 int group; 182 DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); 183 bool has_upstream_irq; 184 }; 185 186 /* per-event information */ 187 struct intel_gvt_event_info { 188 int bit; /* map to register bit */ 189 int policy; /* forwarding policy */ 190 struct intel_gvt_irq_info *info; /* register info */ 191 gvt_event_virt_handler_t v_handler; /* for v_event */ 192 }; 193 194 struct intel_gvt_irq_map { 195 int up_irq_group; 196 int up_irq_bit; 197 int down_irq_group; 198 u32 down_irq_bitmask; 199 }; 200 201 struct intel_gvt_vblank_timer { 202 struct hrtimer timer; 203 u64 period; 204 }; 205 206 /* structure containing device specific IRQ state */ 207 struct intel_gvt_irq { 208 struct intel_gvt_irq_ops *ops; 209 struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX]; 210 DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX); 211 struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX]; 212 DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX); 213 struct intel_gvt_irq_map *irq_map; 214 struct intel_gvt_vblank_timer vblank_timer; 215 }; 216 217 int intel_gvt_init_irq(struct intel_gvt *gvt); 218 void intel_gvt_clean_irq(struct intel_gvt *gvt); 219 220 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 221 enum intel_gvt_event_type event); 222 223 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 224 void *p_data, unsigned int bytes); 225 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 226 unsigned int reg, void *p_data, unsigned int bytes); 227 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 228 unsigned int reg, void *p_data, unsigned int bytes); 229 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 230 unsigned int reg, void *p_data, unsigned int bytes); 231 232 int gvt_ring_id_to_pipe_control_notify_event(int ring_id); 233 int gvt_ring_id_to_mi_flush_dw_event(int ring_id); 234 int gvt_ring_id_to_mi_user_interrupt_event(int ring_id); 235 236 #endif /* _GVT_INTERRUPT_H_ */ 237