1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/i915_drm.h> 40 #include <drm/intel_lpe_audio.h> 41 42 #include "i915_debugfs.h" 43 #include "i915_drv.h" 44 #include "intel_atomic.h" 45 #include "intel_audio.h" 46 #include "intel_connector.h" 47 #include "intel_ddi.h" 48 #include "intel_display_types.h" 49 #include "intel_dp.h" 50 #include "intel_dpio_phy.h" 51 #include "intel_fifo_underrun.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdcp.h" 54 #include "intel_hdmi.h" 55 #include "intel_hotplug.h" 56 #include "intel_lspcon.h" 57 #include "intel_panel.h" 58 #include "intel_sdvo.h" 59 #include "intel_sideband.h" 60 61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 62 { 63 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 64 } 65 66 static void 67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 68 { 69 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 70 struct drm_i915_private *dev_priv = to_i915(dev); 71 u32 enabled_bits; 72 73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 74 75 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 76 "HDMI port enabled, expecting disabled\n"); 77 } 78 79 static void 80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 81 enum transcoder cpu_transcoder) 82 { 83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 84 TRANS_DDI_FUNC_ENABLE, 85 "HDMI transcoder function enabled, expecting disabled\n"); 86 } 87 88 struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) 89 { 90 struct intel_digital_port *intel_dig_port = 91 container_of(&encoder->base, struct intel_digital_port, 92 base.base); 93 return &intel_dig_port->hdmi; 94 } 95 96 static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) 97 { 98 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 99 } 100 101 static u32 g4x_infoframe_index(unsigned int type) 102 { 103 switch (type) { 104 case HDMI_PACKET_TYPE_GAMUT_METADATA: 105 return VIDEO_DIP_SELECT_GAMUT; 106 case HDMI_INFOFRAME_TYPE_AVI: 107 return VIDEO_DIP_SELECT_AVI; 108 case HDMI_INFOFRAME_TYPE_SPD: 109 return VIDEO_DIP_SELECT_SPD; 110 case HDMI_INFOFRAME_TYPE_VENDOR: 111 return VIDEO_DIP_SELECT_VENDOR; 112 default: 113 MISSING_CASE(type); 114 return 0; 115 } 116 } 117 118 static u32 g4x_infoframe_enable(unsigned int type) 119 { 120 switch (type) { 121 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 122 return VIDEO_DIP_ENABLE_GCP; 123 case HDMI_PACKET_TYPE_GAMUT_METADATA: 124 return VIDEO_DIP_ENABLE_GAMUT; 125 case DP_SDP_VSC: 126 return 0; 127 case HDMI_INFOFRAME_TYPE_AVI: 128 return VIDEO_DIP_ENABLE_AVI; 129 case HDMI_INFOFRAME_TYPE_SPD: 130 return VIDEO_DIP_ENABLE_SPD; 131 case HDMI_INFOFRAME_TYPE_VENDOR: 132 return VIDEO_DIP_ENABLE_VENDOR; 133 case HDMI_INFOFRAME_TYPE_DRM: 134 return 0; 135 default: 136 MISSING_CASE(type); 137 return 0; 138 } 139 } 140 141 static u32 hsw_infoframe_enable(unsigned int type) 142 { 143 switch (type) { 144 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 145 return VIDEO_DIP_ENABLE_GCP_HSW; 146 case HDMI_PACKET_TYPE_GAMUT_METADATA: 147 return VIDEO_DIP_ENABLE_GMP_HSW; 148 case DP_SDP_VSC: 149 return VIDEO_DIP_ENABLE_VSC_HSW; 150 case DP_SDP_PPS: 151 return VDIP_ENABLE_PPS; 152 case HDMI_INFOFRAME_TYPE_AVI: 153 return VIDEO_DIP_ENABLE_AVI_HSW; 154 case HDMI_INFOFRAME_TYPE_SPD: 155 return VIDEO_DIP_ENABLE_SPD_HSW; 156 case HDMI_INFOFRAME_TYPE_VENDOR: 157 return VIDEO_DIP_ENABLE_VS_HSW; 158 case HDMI_INFOFRAME_TYPE_DRM: 159 return VIDEO_DIP_ENABLE_DRM_GLK; 160 default: 161 MISSING_CASE(type); 162 return 0; 163 } 164 } 165 166 static i915_reg_t 167 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 168 enum transcoder cpu_transcoder, 169 unsigned int type, 170 int i) 171 { 172 switch (type) { 173 case HDMI_PACKET_TYPE_GAMUT_METADATA: 174 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 175 case DP_SDP_VSC: 176 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 177 case DP_SDP_PPS: 178 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 179 case HDMI_INFOFRAME_TYPE_AVI: 180 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 181 case HDMI_INFOFRAME_TYPE_SPD: 182 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 183 case HDMI_INFOFRAME_TYPE_VENDOR: 184 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 185 case HDMI_INFOFRAME_TYPE_DRM: 186 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 187 default: 188 MISSING_CASE(type); 189 return INVALID_MMIO_REG; 190 } 191 } 192 193 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 194 unsigned int type) 195 { 196 switch (type) { 197 case DP_SDP_VSC: 198 return VIDEO_DIP_VSC_DATA_SIZE; 199 case DP_SDP_PPS: 200 return VIDEO_DIP_PPS_DATA_SIZE; 201 case HDMI_PACKET_TYPE_GAMUT_METADATA: 202 if (INTEL_GEN(dev_priv) >= 11) 203 return VIDEO_DIP_GMP_DATA_SIZE; 204 else 205 return VIDEO_DIP_DATA_SIZE; 206 default: 207 return VIDEO_DIP_DATA_SIZE; 208 } 209 } 210 211 static void g4x_write_infoframe(struct intel_encoder *encoder, 212 const struct intel_crtc_state *crtc_state, 213 unsigned int type, 214 const void *frame, ssize_t len) 215 { 216 const u32 *data = frame; 217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 218 u32 val = I915_READ(VIDEO_DIP_CTL); 219 int i; 220 221 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 222 223 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 224 val |= g4x_infoframe_index(type); 225 226 val &= ~g4x_infoframe_enable(type); 227 228 I915_WRITE(VIDEO_DIP_CTL, val); 229 230 for (i = 0; i < len; i += 4) { 231 I915_WRITE(VIDEO_DIP_DATA, *data); 232 data++; 233 } 234 /* Write every possible data byte to force correct ECC calculation. */ 235 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 236 I915_WRITE(VIDEO_DIP_DATA, 0); 237 238 val |= g4x_infoframe_enable(type); 239 val &= ~VIDEO_DIP_FREQ_MASK; 240 val |= VIDEO_DIP_FREQ_VSYNC; 241 242 I915_WRITE(VIDEO_DIP_CTL, val); 243 POSTING_READ(VIDEO_DIP_CTL); 244 } 245 246 static void g4x_read_infoframe(struct intel_encoder *encoder, 247 const struct intel_crtc_state *crtc_state, 248 unsigned int type, 249 void *frame, ssize_t len) 250 { 251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 252 u32 val, *data = frame; 253 int i; 254 255 val = I915_READ(VIDEO_DIP_CTL); 256 257 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 258 val |= g4x_infoframe_index(type); 259 260 I915_WRITE(VIDEO_DIP_CTL, val); 261 262 for (i = 0; i < len; i += 4) 263 *data++ = I915_READ(VIDEO_DIP_DATA); 264 } 265 266 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 267 const struct intel_crtc_state *pipe_config) 268 { 269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 270 u32 val = I915_READ(VIDEO_DIP_CTL); 271 272 if ((val & VIDEO_DIP_ENABLE) == 0) 273 return 0; 274 275 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 276 return 0; 277 278 return val & (VIDEO_DIP_ENABLE_AVI | 279 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 280 } 281 282 static void ibx_write_infoframe(struct intel_encoder *encoder, 283 const struct intel_crtc_state *crtc_state, 284 unsigned int type, 285 const void *frame, ssize_t len) 286 { 287 const u32 *data = frame; 288 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 290 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 291 u32 val = I915_READ(reg); 292 int i; 293 294 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 295 296 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 297 val |= g4x_infoframe_index(type); 298 299 val &= ~g4x_infoframe_enable(type); 300 301 I915_WRITE(reg, val); 302 303 for (i = 0; i < len; i += 4) { 304 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 305 data++; 306 } 307 /* Write every possible data byte to force correct ECC calculation. */ 308 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 309 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 310 311 val |= g4x_infoframe_enable(type); 312 val &= ~VIDEO_DIP_FREQ_MASK; 313 val |= VIDEO_DIP_FREQ_VSYNC; 314 315 I915_WRITE(reg, val); 316 POSTING_READ(reg); 317 } 318 319 static void ibx_read_infoframe(struct intel_encoder *encoder, 320 const struct intel_crtc_state *crtc_state, 321 unsigned int type, 322 void *frame, ssize_t len) 323 { 324 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 326 u32 val, *data = frame; 327 int i; 328 329 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); 330 331 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 332 val |= g4x_infoframe_index(type); 333 334 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); 335 336 for (i = 0; i < len; i += 4) 337 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); 338 } 339 340 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 341 const struct intel_crtc_state *pipe_config) 342 { 343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 344 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 345 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 346 u32 val = I915_READ(reg); 347 348 if ((val & VIDEO_DIP_ENABLE) == 0) 349 return 0; 350 351 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 352 return 0; 353 354 return val & (VIDEO_DIP_ENABLE_AVI | 355 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 356 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 357 } 358 359 static void cpt_write_infoframe(struct intel_encoder *encoder, 360 const struct intel_crtc_state *crtc_state, 361 unsigned int type, 362 const void *frame, ssize_t len) 363 { 364 const u32 *data = frame; 365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 367 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 368 u32 val = I915_READ(reg); 369 int i; 370 371 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 372 373 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 374 val |= g4x_infoframe_index(type); 375 376 /* The DIP control register spec says that we need to update the AVI 377 * infoframe without clearing its enable bit */ 378 if (type != HDMI_INFOFRAME_TYPE_AVI) 379 val &= ~g4x_infoframe_enable(type); 380 381 I915_WRITE(reg, val); 382 383 for (i = 0; i < len; i += 4) { 384 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 385 data++; 386 } 387 /* Write every possible data byte to force correct ECC calculation. */ 388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 389 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 390 391 val |= g4x_infoframe_enable(type); 392 val &= ~VIDEO_DIP_FREQ_MASK; 393 val |= VIDEO_DIP_FREQ_VSYNC; 394 395 I915_WRITE(reg, val); 396 POSTING_READ(reg); 397 } 398 399 static void cpt_read_infoframe(struct intel_encoder *encoder, 400 const struct intel_crtc_state *crtc_state, 401 unsigned int type, 402 void *frame, ssize_t len) 403 { 404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 405 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 406 u32 val, *data = frame; 407 int i; 408 409 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); 410 411 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 412 val |= g4x_infoframe_index(type); 413 414 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); 415 416 for (i = 0; i < len; i += 4) 417 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); 418 } 419 420 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 421 const struct intel_crtc_state *pipe_config) 422 { 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 425 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 426 427 if ((val & VIDEO_DIP_ENABLE) == 0) 428 return 0; 429 430 return val & (VIDEO_DIP_ENABLE_AVI | 431 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 432 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 433 } 434 435 static void vlv_write_infoframe(struct intel_encoder *encoder, 436 const struct intel_crtc_state *crtc_state, 437 unsigned int type, 438 const void *frame, ssize_t len) 439 { 440 const u32 *data = frame; 441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 443 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 444 u32 val = I915_READ(reg); 445 int i; 446 447 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 448 449 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 450 val |= g4x_infoframe_index(type); 451 452 val &= ~g4x_infoframe_enable(type); 453 454 I915_WRITE(reg, val); 455 456 for (i = 0; i < len; i += 4) { 457 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 458 data++; 459 } 460 /* Write every possible data byte to force correct ECC calculation. */ 461 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 462 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 463 464 val |= g4x_infoframe_enable(type); 465 val &= ~VIDEO_DIP_FREQ_MASK; 466 val |= VIDEO_DIP_FREQ_VSYNC; 467 468 I915_WRITE(reg, val); 469 POSTING_READ(reg); 470 } 471 472 static void vlv_read_infoframe(struct intel_encoder *encoder, 473 const struct intel_crtc_state *crtc_state, 474 unsigned int type, 475 void *frame, ssize_t len) 476 { 477 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 479 u32 val, *data = frame; 480 int i; 481 482 val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); 483 484 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 485 val |= g4x_infoframe_index(type); 486 487 I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 488 489 for (i = 0; i < len; i += 4) 490 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); 491 } 492 493 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 494 const struct intel_crtc_state *pipe_config) 495 { 496 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 497 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 498 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 499 500 if ((val & VIDEO_DIP_ENABLE) == 0) 501 return 0; 502 503 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 504 return 0; 505 506 return val & (VIDEO_DIP_ENABLE_AVI | 507 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 508 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 509 } 510 511 static void hsw_write_infoframe(struct intel_encoder *encoder, 512 const struct intel_crtc_state *crtc_state, 513 unsigned int type, 514 const void *frame, ssize_t len) 515 { 516 const u32 *data = frame; 517 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 518 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 519 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 520 int data_size; 521 int i; 522 u32 val = I915_READ(ctl_reg); 523 524 data_size = hsw_dip_data_size(dev_priv, type); 525 526 WARN_ON(len > data_size); 527 528 val &= ~hsw_infoframe_enable(type); 529 I915_WRITE(ctl_reg, val); 530 531 for (i = 0; i < len; i += 4) { 532 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 533 type, i >> 2), *data); 534 data++; 535 } 536 /* Write every possible data byte to force correct ECC calculation. */ 537 for (; i < data_size; i += 4) 538 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 539 type, i >> 2), 0); 540 541 val |= hsw_infoframe_enable(type); 542 I915_WRITE(ctl_reg, val); 543 POSTING_READ(ctl_reg); 544 } 545 546 static void hsw_read_infoframe(struct intel_encoder *encoder, 547 const struct intel_crtc_state *crtc_state, 548 unsigned int type, 549 void *frame, ssize_t len) 550 { 551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 553 u32 val, *data = frame; 554 int i; 555 556 val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); 557 558 for (i = 0; i < len; i += 4) 559 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, 560 type, i >> 2)); 561 } 562 563 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 564 const struct intel_crtc_state *pipe_config) 565 { 566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 567 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 568 u32 mask; 569 570 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 571 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 572 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 573 574 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 575 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 576 577 return val & mask; 578 } 579 580 static const u8 infoframe_type_to_idx[] = { 581 HDMI_PACKET_TYPE_GENERAL_CONTROL, 582 HDMI_PACKET_TYPE_GAMUT_METADATA, 583 DP_SDP_VSC, 584 HDMI_INFOFRAME_TYPE_AVI, 585 HDMI_INFOFRAME_TYPE_SPD, 586 HDMI_INFOFRAME_TYPE_VENDOR, 587 HDMI_INFOFRAME_TYPE_DRM, 588 }; 589 590 u32 intel_hdmi_infoframe_enable(unsigned int type) 591 { 592 int i; 593 594 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 595 if (infoframe_type_to_idx[i] == type) 596 return BIT(i); 597 } 598 599 return 0; 600 } 601 602 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 603 const struct intel_crtc_state *crtc_state) 604 { 605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 606 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 607 u32 val, ret = 0; 608 int i; 609 610 val = dig_port->infoframes_enabled(encoder, crtc_state); 611 612 /* map from hardware bits to dip idx */ 613 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 614 unsigned int type = infoframe_type_to_idx[i]; 615 616 if (HAS_DDI(dev_priv)) { 617 if (val & hsw_infoframe_enable(type)) 618 ret |= BIT(i); 619 } else { 620 if (val & g4x_infoframe_enable(type)) 621 ret |= BIT(i); 622 } 623 } 624 625 return ret; 626 } 627 628 /* 629 * The data we write to the DIP data buffer registers is 1 byte bigger than the 630 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 631 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 632 * used for both technologies. 633 * 634 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 635 * DW1: DB3 | DB2 | DB1 | DB0 636 * DW2: DB7 | DB6 | DB5 | DB4 637 * DW3: ... 638 * 639 * (HB is Header Byte, DB is Data Byte) 640 * 641 * The hdmi pack() functions don't know about that hardware specific hole so we 642 * trick them by giving an offset into the buffer and moving back the header 643 * bytes by one. 644 */ 645 static void intel_write_infoframe(struct intel_encoder *encoder, 646 const struct intel_crtc_state *crtc_state, 647 enum hdmi_infoframe_type type, 648 const union hdmi_infoframe *frame) 649 { 650 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 651 u8 buffer[VIDEO_DIP_DATA_SIZE]; 652 ssize_t len; 653 654 if ((crtc_state->infoframes.enable & 655 intel_hdmi_infoframe_enable(type)) == 0) 656 return; 657 658 if (WARN_ON(frame->any.type != type)) 659 return; 660 661 /* see comment above for the reason for this offset */ 662 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 663 if (WARN_ON(len < 0)) 664 return; 665 666 /* Insert the 'hole' (see big comment above) at position 3 */ 667 memmove(&buffer[0], &buffer[1], 3); 668 buffer[3] = 0; 669 len++; 670 671 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 672 } 673 674 void intel_read_infoframe(struct intel_encoder *encoder, 675 const struct intel_crtc_state *crtc_state, 676 enum hdmi_infoframe_type type, 677 union hdmi_infoframe *frame) 678 { 679 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 680 u8 buffer[VIDEO_DIP_DATA_SIZE]; 681 int ret; 682 683 if ((crtc_state->infoframes.enable & 684 intel_hdmi_infoframe_enable(type)) == 0) 685 return; 686 687 intel_dig_port->read_infoframe(encoder, crtc_state, 688 type, buffer, sizeof(buffer)); 689 690 /* Fill the 'hole' (see big comment above) at position 3 */ 691 memmove(&buffer[1], &buffer[0], 3); 692 693 /* see comment above for the reason for this offset */ 694 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 695 if (ret) { 696 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); 697 return; 698 } 699 700 if (frame->any.type != type) 701 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 702 frame->any.type, type); 703 } 704 705 static bool 706 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 707 struct intel_crtc_state *crtc_state, 708 struct drm_connector_state *conn_state) 709 { 710 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 711 const struct drm_display_mode *adjusted_mode = 712 &crtc_state->hw.adjusted_mode; 713 struct drm_connector *connector = conn_state->connector; 714 int ret; 715 716 if (!crtc_state->has_infoframe) 717 return true; 718 719 crtc_state->infoframes.enable |= 720 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 721 722 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 723 adjusted_mode); 724 if (ret) 725 return false; 726 727 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 728 frame->colorspace = HDMI_COLORSPACE_YUV420; 729 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 730 frame->colorspace = HDMI_COLORSPACE_YUV444; 731 else 732 frame->colorspace = HDMI_COLORSPACE_RGB; 733 734 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 735 736 /* nonsense combination */ 737 WARN_ON(crtc_state->limited_color_range && 738 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 739 740 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 741 drm_hdmi_avi_infoframe_quant_range(frame, connector, 742 adjusted_mode, 743 crtc_state->limited_color_range ? 744 HDMI_QUANTIZATION_RANGE_LIMITED : 745 HDMI_QUANTIZATION_RANGE_FULL); 746 } else { 747 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 748 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 749 } 750 751 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 752 753 /* TODO: handle pixel repetition for YCBCR420 outputs */ 754 755 ret = hdmi_avi_infoframe_check(frame); 756 if (WARN_ON(ret)) 757 return false; 758 759 return true; 760 } 761 762 static bool 763 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 764 struct intel_crtc_state *crtc_state, 765 struct drm_connector_state *conn_state) 766 { 767 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 768 int ret; 769 770 if (!crtc_state->has_infoframe) 771 return true; 772 773 crtc_state->infoframes.enable |= 774 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 775 776 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 777 if (WARN_ON(ret)) 778 return false; 779 780 frame->sdi = HDMI_SPD_SDI_PC; 781 782 ret = hdmi_spd_infoframe_check(frame); 783 if (WARN_ON(ret)) 784 return false; 785 786 return true; 787 } 788 789 static bool 790 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 791 struct intel_crtc_state *crtc_state, 792 struct drm_connector_state *conn_state) 793 { 794 struct hdmi_vendor_infoframe *frame = 795 &crtc_state->infoframes.hdmi.vendor.hdmi; 796 const struct drm_display_info *info = 797 &conn_state->connector->display_info; 798 int ret; 799 800 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 801 return true; 802 803 crtc_state->infoframes.enable |= 804 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 805 806 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 807 conn_state->connector, 808 &crtc_state->hw.adjusted_mode); 809 if (WARN_ON(ret)) 810 return false; 811 812 ret = hdmi_vendor_infoframe_check(frame); 813 if (WARN_ON(ret)) 814 return false; 815 816 return true; 817 } 818 819 static bool 820 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 821 struct intel_crtc_state *crtc_state, 822 struct drm_connector_state *conn_state) 823 { 824 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 825 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 826 int ret; 827 828 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) 829 return true; 830 831 if (!crtc_state->has_infoframe) 832 return true; 833 834 if (!conn_state->hdr_output_metadata) 835 return true; 836 837 crtc_state->infoframes.enable |= 838 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 839 840 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 841 if (ret < 0) { 842 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); 843 return false; 844 } 845 846 ret = hdmi_drm_infoframe_check(frame); 847 if (WARN_ON(ret)) 848 return false; 849 850 return true; 851 } 852 853 static void g4x_set_infoframes(struct intel_encoder *encoder, 854 bool enable, 855 const struct intel_crtc_state *crtc_state, 856 const struct drm_connector_state *conn_state) 857 { 858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 859 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 860 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 861 i915_reg_t reg = VIDEO_DIP_CTL; 862 u32 val = I915_READ(reg); 863 u32 port = VIDEO_DIP_PORT(encoder->port); 864 865 assert_hdmi_port_disabled(intel_hdmi); 866 867 /* If the registers were not initialized yet, they might be zeroes, 868 * which means we're selecting the AVI DIP and we're setting its 869 * frequency to once. This seems to really confuse the HW and make 870 * things stop working (the register spec says the AVI always needs to 871 * be sent every VSync). So here we avoid writing to the register more 872 * than we need and also explicitly select the AVI DIP and explicitly 873 * set its frequency to every VSync. Avoiding to write it twice seems to 874 * be enough to solve the problem, but being defensive shouldn't hurt us 875 * either. */ 876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 877 878 if (!enable) { 879 if (!(val & VIDEO_DIP_ENABLE)) 880 return; 881 if (port != (val & VIDEO_DIP_PORT_MASK)) { 882 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 883 (val & VIDEO_DIP_PORT_MASK) >> 29); 884 return; 885 } 886 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 887 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 888 I915_WRITE(reg, val); 889 POSTING_READ(reg); 890 return; 891 } 892 893 if (port != (val & VIDEO_DIP_PORT_MASK)) { 894 if (val & VIDEO_DIP_ENABLE) { 895 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 896 (val & VIDEO_DIP_PORT_MASK) >> 29); 897 return; 898 } 899 val &= ~VIDEO_DIP_PORT_MASK; 900 val |= port; 901 } 902 903 val |= VIDEO_DIP_ENABLE; 904 val &= ~(VIDEO_DIP_ENABLE_AVI | 905 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 906 907 I915_WRITE(reg, val); 908 POSTING_READ(reg); 909 910 intel_write_infoframe(encoder, crtc_state, 911 HDMI_INFOFRAME_TYPE_AVI, 912 &crtc_state->infoframes.avi); 913 intel_write_infoframe(encoder, crtc_state, 914 HDMI_INFOFRAME_TYPE_SPD, 915 &crtc_state->infoframes.spd); 916 intel_write_infoframe(encoder, crtc_state, 917 HDMI_INFOFRAME_TYPE_VENDOR, 918 &crtc_state->infoframes.hdmi); 919 } 920 921 /* 922 * Determine if default_phase=1 can be indicated in the GCP infoframe. 923 * 924 * From HDMI specification 1.4a: 925 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 926 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 927 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 928 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 929 * phase of 0 930 */ 931 static bool gcp_default_phase_possible(int pipe_bpp, 932 const struct drm_display_mode *mode) 933 { 934 unsigned int pixels_per_group; 935 936 switch (pipe_bpp) { 937 case 30: 938 /* 4 pixels in 5 clocks */ 939 pixels_per_group = 4; 940 break; 941 case 36: 942 /* 2 pixels in 3 clocks */ 943 pixels_per_group = 2; 944 break; 945 case 48: 946 /* 1 pixel in 2 clocks */ 947 pixels_per_group = 1; 948 break; 949 default: 950 /* phase information not relevant for 8bpc */ 951 return false; 952 } 953 954 return mode->crtc_hdisplay % pixels_per_group == 0 && 955 mode->crtc_htotal % pixels_per_group == 0 && 956 mode->crtc_hblank_start % pixels_per_group == 0 && 957 mode->crtc_hblank_end % pixels_per_group == 0 && 958 mode->crtc_hsync_start % pixels_per_group == 0 && 959 mode->crtc_hsync_end % pixels_per_group == 0 && 960 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 961 mode->crtc_htotal/2 % pixels_per_group == 0); 962 } 963 964 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 965 const struct intel_crtc_state *crtc_state, 966 const struct drm_connector_state *conn_state) 967 { 968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 969 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 970 i915_reg_t reg; 971 972 if ((crtc_state->infoframes.enable & 973 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 974 return false; 975 976 if (HAS_DDI(dev_priv)) 977 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 978 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 979 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 980 else if (HAS_PCH_SPLIT(dev_priv)) 981 reg = TVIDEO_DIP_GCP(crtc->pipe); 982 else 983 return false; 984 985 I915_WRITE(reg, crtc_state->infoframes.gcp); 986 987 return true; 988 } 989 990 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 991 struct intel_crtc_state *crtc_state) 992 { 993 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 994 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 995 i915_reg_t reg; 996 997 if ((crtc_state->infoframes.enable & 998 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 999 return; 1000 1001 if (HAS_DDI(dev_priv)) 1002 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1003 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1004 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1005 else if (HAS_PCH_SPLIT(dev_priv)) 1006 reg = TVIDEO_DIP_GCP(crtc->pipe); 1007 else 1008 return; 1009 1010 crtc_state->infoframes.gcp = I915_READ(reg); 1011 } 1012 1013 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1014 struct intel_crtc_state *crtc_state, 1015 struct drm_connector_state *conn_state) 1016 { 1017 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1018 1019 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1020 return; 1021 1022 crtc_state->infoframes.enable |= 1023 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1024 1025 /* Indicate color indication for deep color mode */ 1026 if (crtc_state->pipe_bpp > 24) 1027 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1028 1029 /* Enable default_phase whenever the display mode is suitably aligned */ 1030 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1031 &crtc_state->hw.adjusted_mode)) 1032 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1033 } 1034 1035 static void ibx_set_infoframes(struct intel_encoder *encoder, 1036 bool enable, 1037 const struct intel_crtc_state *crtc_state, 1038 const struct drm_connector_state *conn_state) 1039 { 1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1042 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1043 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1044 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1045 u32 val = I915_READ(reg); 1046 u32 port = VIDEO_DIP_PORT(encoder->port); 1047 1048 assert_hdmi_port_disabled(intel_hdmi); 1049 1050 /* See the big comment in g4x_set_infoframes() */ 1051 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1052 1053 if (!enable) { 1054 if (!(val & VIDEO_DIP_ENABLE)) 1055 return; 1056 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1057 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1058 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1059 I915_WRITE(reg, val); 1060 POSTING_READ(reg); 1061 return; 1062 } 1063 1064 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1065 WARN(val & VIDEO_DIP_ENABLE, 1066 "DIP already enabled on port %c\n", 1067 (val & VIDEO_DIP_PORT_MASK) >> 29); 1068 val &= ~VIDEO_DIP_PORT_MASK; 1069 val |= port; 1070 } 1071 1072 val |= VIDEO_DIP_ENABLE; 1073 val &= ~(VIDEO_DIP_ENABLE_AVI | 1074 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1075 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1076 1077 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1078 val |= VIDEO_DIP_ENABLE_GCP; 1079 1080 I915_WRITE(reg, val); 1081 POSTING_READ(reg); 1082 1083 intel_write_infoframe(encoder, crtc_state, 1084 HDMI_INFOFRAME_TYPE_AVI, 1085 &crtc_state->infoframes.avi); 1086 intel_write_infoframe(encoder, crtc_state, 1087 HDMI_INFOFRAME_TYPE_SPD, 1088 &crtc_state->infoframes.spd); 1089 intel_write_infoframe(encoder, crtc_state, 1090 HDMI_INFOFRAME_TYPE_VENDOR, 1091 &crtc_state->infoframes.hdmi); 1092 } 1093 1094 static void cpt_set_infoframes(struct intel_encoder *encoder, 1095 bool enable, 1096 const struct intel_crtc_state *crtc_state, 1097 const struct drm_connector_state *conn_state) 1098 { 1099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1101 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1102 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1103 u32 val = I915_READ(reg); 1104 1105 assert_hdmi_port_disabled(intel_hdmi); 1106 1107 /* See the big comment in g4x_set_infoframes() */ 1108 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1109 1110 if (!enable) { 1111 if (!(val & VIDEO_DIP_ENABLE)) 1112 return; 1113 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1114 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1115 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1116 I915_WRITE(reg, val); 1117 POSTING_READ(reg); 1118 return; 1119 } 1120 1121 /* Set both together, unset both together: see the spec. */ 1122 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1123 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1124 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1125 1126 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1127 val |= VIDEO_DIP_ENABLE_GCP; 1128 1129 I915_WRITE(reg, val); 1130 POSTING_READ(reg); 1131 1132 intel_write_infoframe(encoder, crtc_state, 1133 HDMI_INFOFRAME_TYPE_AVI, 1134 &crtc_state->infoframes.avi); 1135 intel_write_infoframe(encoder, crtc_state, 1136 HDMI_INFOFRAME_TYPE_SPD, 1137 &crtc_state->infoframes.spd); 1138 intel_write_infoframe(encoder, crtc_state, 1139 HDMI_INFOFRAME_TYPE_VENDOR, 1140 &crtc_state->infoframes.hdmi); 1141 } 1142 1143 static void vlv_set_infoframes(struct intel_encoder *encoder, 1144 bool enable, 1145 const struct intel_crtc_state *crtc_state, 1146 const struct drm_connector_state *conn_state) 1147 { 1148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1150 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1151 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1152 u32 val = I915_READ(reg); 1153 u32 port = VIDEO_DIP_PORT(encoder->port); 1154 1155 assert_hdmi_port_disabled(intel_hdmi); 1156 1157 /* See the big comment in g4x_set_infoframes() */ 1158 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1159 1160 if (!enable) { 1161 if (!(val & VIDEO_DIP_ENABLE)) 1162 return; 1163 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1164 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1165 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1166 I915_WRITE(reg, val); 1167 POSTING_READ(reg); 1168 return; 1169 } 1170 1171 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1172 WARN(val & VIDEO_DIP_ENABLE, 1173 "DIP already enabled on port %c\n", 1174 (val & VIDEO_DIP_PORT_MASK) >> 29); 1175 val &= ~VIDEO_DIP_PORT_MASK; 1176 val |= port; 1177 } 1178 1179 val |= VIDEO_DIP_ENABLE; 1180 val &= ~(VIDEO_DIP_ENABLE_AVI | 1181 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1182 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1183 1184 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1185 val |= VIDEO_DIP_ENABLE_GCP; 1186 1187 I915_WRITE(reg, val); 1188 POSTING_READ(reg); 1189 1190 intel_write_infoframe(encoder, crtc_state, 1191 HDMI_INFOFRAME_TYPE_AVI, 1192 &crtc_state->infoframes.avi); 1193 intel_write_infoframe(encoder, crtc_state, 1194 HDMI_INFOFRAME_TYPE_SPD, 1195 &crtc_state->infoframes.spd); 1196 intel_write_infoframe(encoder, crtc_state, 1197 HDMI_INFOFRAME_TYPE_VENDOR, 1198 &crtc_state->infoframes.hdmi); 1199 } 1200 1201 static void hsw_set_infoframes(struct intel_encoder *encoder, 1202 bool enable, 1203 const struct intel_crtc_state *crtc_state, 1204 const struct drm_connector_state *conn_state) 1205 { 1206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1207 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1208 u32 val = I915_READ(reg); 1209 1210 assert_hdmi_transcoder_func_disabled(dev_priv, 1211 crtc_state->cpu_transcoder); 1212 1213 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1214 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1215 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1216 VIDEO_DIP_ENABLE_DRM_GLK); 1217 1218 if (!enable) { 1219 I915_WRITE(reg, val); 1220 POSTING_READ(reg); 1221 return; 1222 } 1223 1224 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1225 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1226 1227 I915_WRITE(reg, val); 1228 POSTING_READ(reg); 1229 1230 intel_write_infoframe(encoder, crtc_state, 1231 HDMI_INFOFRAME_TYPE_AVI, 1232 &crtc_state->infoframes.avi); 1233 intel_write_infoframe(encoder, crtc_state, 1234 HDMI_INFOFRAME_TYPE_SPD, 1235 &crtc_state->infoframes.spd); 1236 intel_write_infoframe(encoder, crtc_state, 1237 HDMI_INFOFRAME_TYPE_VENDOR, 1238 &crtc_state->infoframes.hdmi); 1239 intel_write_infoframe(encoder, crtc_state, 1240 HDMI_INFOFRAME_TYPE_DRM, 1241 &crtc_state->infoframes.drm); 1242 } 1243 1244 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1245 { 1246 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1247 struct i2c_adapter *adapter = 1248 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1249 1250 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1251 return; 1252 1253 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 1254 enable ? "Enabling" : "Disabling"); 1255 1256 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 1257 adapter, enable); 1258 } 1259 1260 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, 1261 unsigned int offset, void *buffer, size_t size) 1262 { 1263 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1264 struct drm_i915_private *dev_priv = 1265 intel_dig_port->base.base.dev->dev_private; 1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, 1267 hdmi->ddc_bus); 1268 int ret; 1269 u8 start = offset & 0xff; 1270 struct i2c_msg msgs[] = { 1271 { 1272 .addr = DRM_HDCP_DDC_ADDR, 1273 .flags = 0, 1274 .len = 1, 1275 .buf = &start, 1276 }, 1277 { 1278 .addr = DRM_HDCP_DDC_ADDR, 1279 .flags = I2C_M_RD, 1280 .len = size, 1281 .buf = buffer 1282 } 1283 }; 1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1285 if (ret == ARRAY_SIZE(msgs)) 1286 return 0; 1287 return ret >= 0 ? -EIO : ret; 1288 } 1289 1290 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, 1291 unsigned int offset, void *buffer, size_t size) 1292 { 1293 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1294 struct drm_i915_private *dev_priv = 1295 intel_dig_port->base.base.dev->dev_private; 1296 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, 1297 hdmi->ddc_bus); 1298 int ret; 1299 u8 *write_buf; 1300 struct i2c_msg msg; 1301 1302 write_buf = kzalloc(size + 1, GFP_KERNEL); 1303 if (!write_buf) 1304 return -ENOMEM; 1305 1306 write_buf[0] = offset & 0xff; 1307 memcpy(&write_buf[1], buffer, size); 1308 1309 msg.addr = DRM_HDCP_DDC_ADDR; 1310 msg.flags = 0, 1311 msg.len = size + 1, 1312 msg.buf = write_buf; 1313 1314 ret = i2c_transfer(adapter, &msg, 1); 1315 if (ret == 1) 1316 ret = 0; 1317 else if (ret >= 0) 1318 ret = -EIO; 1319 1320 kfree(write_buf); 1321 return ret; 1322 } 1323 1324 static 1325 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, 1326 u8 *an) 1327 { 1328 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1329 struct drm_i915_private *dev_priv = 1330 intel_dig_port->base.base.dev->dev_private; 1331 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, 1332 hdmi->ddc_bus); 1333 int ret; 1334 1335 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, 1336 DRM_HDCP_AN_LEN); 1337 if (ret) { 1338 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); 1339 return ret; 1340 } 1341 1342 ret = intel_gmbus_output_aksv(adapter); 1343 if (ret < 0) { 1344 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); 1345 return ret; 1346 } 1347 return 0; 1348 } 1349 1350 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, 1351 u8 *bksv) 1352 { 1353 int ret; 1354 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, 1355 DRM_HDCP_KSV_LEN); 1356 if (ret) 1357 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); 1358 return ret; 1359 } 1360 1361 static 1362 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, 1363 u8 *bstatus) 1364 { 1365 int ret; 1366 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, 1367 bstatus, DRM_HDCP_BSTATUS_LEN); 1368 if (ret) 1369 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); 1370 return ret; 1371 } 1372 1373 static 1374 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, 1375 bool *repeater_present) 1376 { 1377 int ret; 1378 u8 val; 1379 1380 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1381 if (ret) { 1382 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1383 return ret; 1384 } 1385 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1386 return 0; 1387 } 1388 1389 static 1390 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, 1391 u8 *ri_prime) 1392 { 1393 int ret; 1394 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, 1395 ri_prime, DRM_HDCP_RI_LEN); 1396 if (ret) 1397 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); 1398 return ret; 1399 } 1400 1401 static 1402 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, 1403 bool *ksv_ready) 1404 { 1405 int ret; 1406 u8 val; 1407 1408 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1409 if (ret) { 1410 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1411 return ret; 1412 } 1413 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1414 return 0; 1415 } 1416 1417 static 1418 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, 1419 int num_downstream, u8 *ksv_fifo) 1420 { 1421 int ret; 1422 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, 1423 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1424 if (ret) { 1425 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); 1426 return ret; 1427 } 1428 return 0; 1429 } 1430 1431 static 1432 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, 1433 int i, u32 *part) 1434 { 1435 int ret; 1436 1437 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1438 return -EINVAL; 1439 1440 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), 1441 part, DRM_HDCP_V_PRIME_PART_LEN); 1442 if (ret) 1443 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); 1444 return ret; 1445 } 1446 1447 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) 1448 { 1449 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1450 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1451 struct drm_crtc *crtc = connector->base.state->crtc; 1452 struct intel_crtc *intel_crtc = container_of(crtc, 1453 struct intel_crtc, base); 1454 u32 scanline; 1455 int ret; 1456 1457 for (;;) { 1458 scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); 1459 if (scanline > 100 && scanline < 200) 1460 break; 1461 usleep_range(25, 50); 1462 } 1463 1464 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); 1465 if (ret) { 1466 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); 1467 return ret; 1468 } 1469 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); 1470 if (ret) { 1471 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); 1472 return ret; 1473 } 1474 1475 return 0; 1476 } 1477 1478 static 1479 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, 1480 bool enable) 1481 { 1482 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1483 struct intel_connector *connector = hdmi->attached_connector; 1484 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1485 int ret; 1486 1487 if (!enable) 1488 usleep_range(6, 60); /* Bspec says >= 6us */ 1489 1490 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); 1491 if (ret) { 1492 DRM_ERROR("%s HDCP signalling failed (%d)\n", 1493 enable ? "Enable" : "Disable", ret); 1494 return ret; 1495 } 1496 1497 /* 1498 * WA: To fix incorrect positioning of the window of 1499 * opportunity and enc_en signalling in KABYLAKE. 1500 */ 1501 if (IS_KABYLAKE(dev_priv) && enable) 1502 return kbl_repositioning_enc_en_signal(connector); 1503 1504 return 0; 1505 } 1506 1507 static 1508 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) 1509 { 1510 struct drm_i915_private *dev_priv = 1511 intel_dig_port->base.base.dev->dev_private; 1512 struct intel_connector *connector = 1513 intel_dig_port->hdmi.attached_connector; 1514 enum port port = intel_dig_port->base.port; 1515 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1516 int ret; 1517 union { 1518 u32 reg; 1519 u8 shim[DRM_HDCP_RI_LEN]; 1520 } ri; 1521 1522 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); 1523 if (ret) 1524 return false; 1525 1526 I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg); 1527 1528 /* Wait for Ri prime match */ 1529 if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) & 1530 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1531 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", 1532 I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, 1533 port))); 1534 return false; 1535 } 1536 return true; 1537 } 1538 1539 struct hdcp2_hdmi_msg_timeout { 1540 u8 msg_id; 1541 u16 timeout; 1542 }; 1543 1544 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1545 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1546 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1547 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1548 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1549 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1550 }; 1551 1552 static 1553 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, 1554 u8 *rx_status) 1555 { 1556 return intel_hdmi_hdcp_read(intel_dig_port, 1557 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1558 rx_status, 1559 HDCP_2_2_HDMI_RXSTATUS_LEN); 1560 } 1561 1562 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1563 { 1564 int i; 1565 1566 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1567 if (is_paired) 1568 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1569 else 1570 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1571 } 1572 1573 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1574 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1575 return hdcp2_msg_timeout[i].timeout; 1576 } 1577 1578 return -EINVAL; 1579 } 1580 1581 static inline 1582 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, 1583 u8 msg_id, bool *msg_ready, 1584 ssize_t *msg_sz) 1585 { 1586 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1587 int ret; 1588 1589 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); 1590 if (ret < 0) { 1591 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); 1592 return ret; 1593 } 1594 1595 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1596 rx_status[0]); 1597 1598 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1599 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1600 *msg_sz); 1601 else 1602 *msg_ready = *msg_sz; 1603 1604 return 0; 1605 } 1606 1607 static ssize_t 1608 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, 1609 u8 msg_id, bool paired) 1610 { 1611 bool msg_ready = false; 1612 int timeout, ret; 1613 ssize_t msg_sz = 0; 1614 1615 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1616 if (timeout < 0) 1617 return timeout; 1618 1619 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, 1620 msg_id, &msg_ready, 1621 &msg_sz), 1622 !ret && msg_ready && msg_sz, timeout * 1000, 1623 1000, 5 * 1000); 1624 if (ret) 1625 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", 1626 msg_id, ret, timeout); 1627 1628 return ret ? ret : msg_sz; 1629 } 1630 1631 static 1632 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, 1633 void *buf, size_t size) 1634 { 1635 unsigned int offset; 1636 1637 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1638 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); 1639 } 1640 1641 static 1642 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, 1643 u8 msg_id, void *buf, size_t size) 1644 { 1645 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1646 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1647 unsigned int offset; 1648 ssize_t ret; 1649 1650 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, 1651 hdcp->is_paired); 1652 if (ret < 0) 1653 return ret; 1654 1655 /* 1656 * Available msg size should be equal to or lesser than the 1657 * available buffer. 1658 */ 1659 if (ret > size) { 1660 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", 1661 ret, size); 1662 return -1; 1663 } 1664 1665 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1666 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); 1667 if (ret) 1668 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); 1669 1670 return ret; 1671 } 1672 1673 static 1674 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) 1675 { 1676 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1677 int ret; 1678 1679 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); 1680 if (ret) 1681 return ret; 1682 1683 /* 1684 * Re-auth request and Link Integrity Failures are represented by 1685 * same bit. i.e reauth_req. 1686 */ 1687 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1688 ret = HDCP_REAUTH_REQUEST; 1689 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1690 ret = HDCP_TOPOLOGY_CHANGE; 1691 1692 return ret; 1693 } 1694 1695 static 1696 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, 1697 bool *capable) 1698 { 1699 u8 hdcp2_version; 1700 int ret; 1701 1702 *capable = false; 1703 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1704 &hdcp2_version, sizeof(hdcp2_version)); 1705 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1706 *capable = true; 1707 1708 return ret; 1709 } 1710 1711 static inline 1712 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) 1713 { 1714 return HDCP_PROTOCOL_HDMI; 1715 } 1716 1717 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1718 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1719 .read_bksv = intel_hdmi_hdcp_read_bksv, 1720 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1721 .repeater_present = intel_hdmi_hdcp_repeater_present, 1722 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1723 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1724 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1725 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1726 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1727 .check_link = intel_hdmi_hdcp_check_link, 1728 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1729 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1730 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1731 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1732 .protocol = HDCP_PROTOCOL_HDMI, 1733 }; 1734 1735 static void intel_hdmi_prepare(struct intel_encoder *encoder, 1736 const struct intel_crtc_state *crtc_state) 1737 { 1738 struct drm_device *dev = encoder->base.dev; 1739 struct drm_i915_private *dev_priv = to_i915(dev); 1740 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1741 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1742 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1743 u32 hdmi_val; 1744 1745 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1746 1747 hdmi_val = SDVO_ENCODING_HDMI; 1748 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1749 hdmi_val |= HDMI_COLOR_RANGE_16_235; 1750 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1751 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 1752 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1753 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 1754 1755 if (crtc_state->pipe_bpp > 24) 1756 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 1757 else 1758 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 1759 1760 if (crtc_state->has_hdmi_sink) 1761 hdmi_val |= HDMI_MODE_SELECT_HDMI; 1762 1763 if (HAS_PCH_CPT(dev_priv)) 1764 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1765 else if (IS_CHERRYVIEW(dev_priv)) 1766 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 1767 else 1768 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 1769 1770 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 1771 POSTING_READ(intel_hdmi->hdmi_reg); 1772 } 1773 1774 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 1775 enum pipe *pipe) 1776 { 1777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1778 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1779 intel_wakeref_t wakeref; 1780 bool ret; 1781 1782 wakeref = intel_display_power_get_if_enabled(dev_priv, 1783 encoder->power_domain); 1784 if (!wakeref) 1785 return false; 1786 1787 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 1788 1789 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1790 1791 return ret; 1792 } 1793 1794 static void intel_hdmi_get_config(struct intel_encoder *encoder, 1795 struct intel_crtc_state *pipe_config) 1796 { 1797 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1798 struct drm_device *dev = encoder->base.dev; 1799 struct drm_i915_private *dev_priv = to_i915(dev); 1800 u32 tmp, flags = 0; 1801 int dotclock; 1802 1803 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 1804 1805 tmp = I915_READ(intel_hdmi->hdmi_reg); 1806 1807 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 1808 flags |= DRM_MODE_FLAG_PHSYNC; 1809 else 1810 flags |= DRM_MODE_FLAG_NHSYNC; 1811 1812 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 1813 flags |= DRM_MODE_FLAG_PVSYNC; 1814 else 1815 flags |= DRM_MODE_FLAG_NVSYNC; 1816 1817 if (tmp & HDMI_MODE_SELECT_HDMI) 1818 pipe_config->has_hdmi_sink = true; 1819 1820 pipe_config->infoframes.enable |= 1821 intel_hdmi_infoframes_enabled(encoder, pipe_config); 1822 1823 if (pipe_config->infoframes.enable) 1824 pipe_config->has_infoframe = true; 1825 1826 if (tmp & HDMI_AUDIO_ENABLE) 1827 pipe_config->has_audio = true; 1828 1829 if (!HAS_PCH_SPLIT(dev_priv) && 1830 tmp & HDMI_COLOR_RANGE_16_235) 1831 pipe_config->limited_color_range = true; 1832 1833 pipe_config->hw.adjusted_mode.flags |= flags; 1834 1835 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 1836 dotclock = pipe_config->port_clock * 2 / 3; 1837 else 1838 dotclock = pipe_config->port_clock; 1839 1840 if (pipe_config->pixel_multiplier) 1841 dotclock /= pipe_config->pixel_multiplier; 1842 1843 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1844 1845 pipe_config->lane_count = 4; 1846 1847 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 1848 1849 intel_read_infoframe(encoder, pipe_config, 1850 HDMI_INFOFRAME_TYPE_AVI, 1851 &pipe_config->infoframes.avi); 1852 intel_read_infoframe(encoder, pipe_config, 1853 HDMI_INFOFRAME_TYPE_SPD, 1854 &pipe_config->infoframes.spd); 1855 intel_read_infoframe(encoder, pipe_config, 1856 HDMI_INFOFRAME_TYPE_VENDOR, 1857 &pipe_config->infoframes.hdmi); 1858 } 1859 1860 static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1861 const struct intel_crtc_state *pipe_config, 1862 const struct drm_connector_state *conn_state) 1863 { 1864 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1865 1866 WARN_ON(!pipe_config->has_hdmi_sink); 1867 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 1868 pipe_name(crtc->pipe)); 1869 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1870 } 1871 1872 static void g4x_enable_hdmi(struct intel_encoder *encoder, 1873 const struct intel_crtc_state *pipe_config, 1874 const struct drm_connector_state *conn_state) 1875 { 1876 struct drm_device *dev = encoder->base.dev; 1877 struct drm_i915_private *dev_priv = to_i915(dev); 1878 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1879 u32 temp; 1880 1881 temp = I915_READ(intel_hdmi->hdmi_reg); 1882 1883 temp |= SDVO_ENABLE; 1884 if (pipe_config->has_audio) 1885 temp |= HDMI_AUDIO_ENABLE; 1886 1887 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1888 POSTING_READ(intel_hdmi->hdmi_reg); 1889 1890 if (pipe_config->has_audio) 1891 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1892 } 1893 1894 static void ibx_enable_hdmi(struct intel_encoder *encoder, 1895 const struct intel_crtc_state *pipe_config, 1896 const struct drm_connector_state *conn_state) 1897 { 1898 struct drm_device *dev = encoder->base.dev; 1899 struct drm_i915_private *dev_priv = to_i915(dev); 1900 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1901 u32 temp; 1902 1903 temp = I915_READ(intel_hdmi->hdmi_reg); 1904 1905 temp |= SDVO_ENABLE; 1906 if (pipe_config->has_audio) 1907 temp |= HDMI_AUDIO_ENABLE; 1908 1909 /* 1910 * HW workaround, need to write this twice for issue 1911 * that may result in first write getting masked. 1912 */ 1913 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1914 POSTING_READ(intel_hdmi->hdmi_reg); 1915 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1916 POSTING_READ(intel_hdmi->hdmi_reg); 1917 1918 /* 1919 * HW workaround, need to toggle enable bit off and on 1920 * for 12bpc with pixel repeat. 1921 * 1922 * FIXME: BSpec says this should be done at the end of 1923 * of the modeset sequence, so not sure if this isn't too soon. 1924 */ 1925 if (pipe_config->pipe_bpp > 24 && 1926 pipe_config->pixel_multiplier > 1) { 1927 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1928 POSTING_READ(intel_hdmi->hdmi_reg); 1929 1930 /* 1931 * HW workaround, need to write this twice for issue 1932 * that may result in first write getting masked. 1933 */ 1934 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1935 POSTING_READ(intel_hdmi->hdmi_reg); 1936 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1937 POSTING_READ(intel_hdmi->hdmi_reg); 1938 } 1939 1940 if (pipe_config->has_audio) 1941 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1942 } 1943 1944 static void cpt_enable_hdmi(struct intel_encoder *encoder, 1945 const struct intel_crtc_state *pipe_config, 1946 const struct drm_connector_state *conn_state) 1947 { 1948 struct drm_device *dev = encoder->base.dev; 1949 struct drm_i915_private *dev_priv = to_i915(dev); 1950 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1951 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1952 enum pipe pipe = crtc->pipe; 1953 u32 temp; 1954 1955 temp = I915_READ(intel_hdmi->hdmi_reg); 1956 1957 temp |= SDVO_ENABLE; 1958 if (pipe_config->has_audio) 1959 temp |= HDMI_AUDIO_ENABLE; 1960 1961 /* 1962 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1963 * 1964 * The procedure for 12bpc is as follows: 1965 * 1. disable HDMI clock gating 1966 * 2. enable HDMI with 8bpc 1967 * 3. enable HDMI with 12bpc 1968 * 4. enable HDMI clock gating 1969 */ 1970 1971 if (pipe_config->pipe_bpp > 24) { 1972 I915_WRITE(TRANS_CHICKEN1(pipe), 1973 I915_READ(TRANS_CHICKEN1(pipe)) | 1974 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1975 1976 temp &= ~SDVO_COLOR_FORMAT_MASK; 1977 temp |= SDVO_COLOR_FORMAT_8bpc; 1978 } 1979 1980 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1981 POSTING_READ(intel_hdmi->hdmi_reg); 1982 1983 if (pipe_config->pipe_bpp > 24) { 1984 temp &= ~SDVO_COLOR_FORMAT_MASK; 1985 temp |= HDMI_COLOR_FORMAT_12bpc; 1986 1987 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1988 POSTING_READ(intel_hdmi->hdmi_reg); 1989 1990 I915_WRITE(TRANS_CHICKEN1(pipe), 1991 I915_READ(TRANS_CHICKEN1(pipe)) & 1992 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1993 } 1994 1995 if (pipe_config->has_audio) 1996 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1997 } 1998 1999 static void vlv_enable_hdmi(struct intel_encoder *encoder, 2000 const struct intel_crtc_state *pipe_config, 2001 const struct drm_connector_state *conn_state) 2002 { 2003 } 2004 2005 static void intel_disable_hdmi(struct intel_encoder *encoder, 2006 const struct intel_crtc_state *old_crtc_state, 2007 const struct drm_connector_state *old_conn_state) 2008 { 2009 struct drm_device *dev = encoder->base.dev; 2010 struct drm_i915_private *dev_priv = to_i915(dev); 2011 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2012 struct intel_digital_port *intel_dig_port = 2013 hdmi_to_dig_port(intel_hdmi); 2014 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2015 u32 temp; 2016 2017 temp = I915_READ(intel_hdmi->hdmi_reg); 2018 2019 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 2020 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2021 POSTING_READ(intel_hdmi->hdmi_reg); 2022 2023 /* 2024 * HW workaround for IBX, we need to move the port 2025 * to transcoder A after disabling it to allow the 2026 * matching DP port to be enabled on transcoder A. 2027 */ 2028 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 2029 /* 2030 * We get CPU/PCH FIFO underruns on the other pipe when 2031 * doing the workaround. Sweep them under the rug. 2032 */ 2033 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2034 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2035 2036 temp &= ~SDVO_PIPE_SEL_MASK; 2037 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 2038 /* 2039 * HW workaround, need to write this twice for issue 2040 * that may result in first write getting masked. 2041 */ 2042 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2043 POSTING_READ(intel_hdmi->hdmi_reg); 2044 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2045 POSTING_READ(intel_hdmi->hdmi_reg); 2046 2047 temp &= ~SDVO_ENABLE; 2048 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2049 POSTING_READ(intel_hdmi->hdmi_reg); 2050 2051 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 2052 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2053 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2054 } 2055 2056 intel_dig_port->set_infoframes(encoder, 2057 false, 2058 old_crtc_state, old_conn_state); 2059 2060 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2061 } 2062 2063 static void g4x_disable_hdmi(struct intel_encoder *encoder, 2064 const struct intel_crtc_state *old_crtc_state, 2065 const struct drm_connector_state *old_conn_state) 2066 { 2067 if (old_crtc_state->has_audio) 2068 intel_audio_codec_disable(encoder, 2069 old_crtc_state, old_conn_state); 2070 2071 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2072 } 2073 2074 static void pch_disable_hdmi(struct intel_encoder *encoder, 2075 const struct intel_crtc_state *old_crtc_state, 2076 const struct drm_connector_state *old_conn_state) 2077 { 2078 if (old_crtc_state->has_audio) 2079 intel_audio_codec_disable(encoder, 2080 old_crtc_state, old_conn_state); 2081 } 2082 2083 static void pch_post_disable_hdmi(struct intel_encoder *encoder, 2084 const struct intel_crtc_state *old_crtc_state, 2085 const struct drm_connector_state *old_conn_state) 2086 { 2087 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2088 } 2089 2090 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 2091 { 2092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2093 const struct ddi_vbt_port_info *info = 2094 &dev_priv->vbt.ddi_port_info[encoder->port]; 2095 int max_tmds_clock; 2096 2097 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2098 max_tmds_clock = 594000; 2099 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 2100 max_tmds_clock = 300000; 2101 else if (INTEL_GEN(dev_priv) >= 5) 2102 max_tmds_clock = 225000; 2103 else 2104 max_tmds_clock = 165000; 2105 2106 if (info->max_tmds_clock) 2107 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 2108 2109 return max_tmds_clock; 2110 } 2111 2112 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 2113 bool respect_downstream_limits, 2114 bool force_dvi) 2115 { 2116 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2117 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 2118 2119 if (respect_downstream_limits) { 2120 struct intel_connector *connector = hdmi->attached_connector; 2121 const struct drm_display_info *info = &connector->base.display_info; 2122 2123 if (hdmi->dp_dual_mode.max_tmds_clock) 2124 max_tmds_clock = min(max_tmds_clock, 2125 hdmi->dp_dual_mode.max_tmds_clock); 2126 2127 if (info->max_tmds_clock) 2128 max_tmds_clock = min(max_tmds_clock, 2129 info->max_tmds_clock); 2130 else if (!hdmi->has_hdmi_sink || force_dvi) 2131 max_tmds_clock = min(max_tmds_clock, 165000); 2132 } 2133 2134 return max_tmds_clock; 2135 } 2136 2137 static enum drm_mode_status 2138 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 2139 int clock, bool respect_downstream_limits, 2140 bool force_dvi) 2141 { 2142 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 2143 2144 if (clock < 25000) 2145 return MODE_CLOCK_LOW; 2146 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) 2147 return MODE_CLOCK_HIGH; 2148 2149 /* BXT DPLL can't generate 223-240 MHz */ 2150 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 2151 return MODE_CLOCK_RANGE; 2152 2153 /* CHV DPLL can't generate 216-240 MHz */ 2154 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 2155 return MODE_CLOCK_RANGE; 2156 2157 return MODE_OK; 2158 } 2159 2160 static enum drm_mode_status 2161 intel_hdmi_mode_valid(struct drm_connector *connector, 2162 struct drm_display_mode *mode) 2163 { 2164 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2165 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 2166 struct drm_i915_private *dev_priv = to_i915(dev); 2167 enum drm_mode_status status; 2168 int clock; 2169 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 2170 bool force_dvi = 2171 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; 2172 2173 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2174 return MODE_NO_DBLESCAN; 2175 2176 clock = mode->clock; 2177 2178 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2179 clock *= 2; 2180 2181 if (clock > max_dotclk) 2182 return MODE_CLOCK_HIGH; 2183 2184 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2185 clock *= 2; 2186 2187 if (drm_mode_is_420_only(&connector->display_info, mode)) 2188 clock /= 2; 2189 2190 /* check if we can do 8bpc */ 2191 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); 2192 2193 if (hdmi->has_hdmi_sink && !force_dvi) { 2194 /* if we can't do 8bpc we may still be able to do 12bpc */ 2195 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 2196 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, 2197 true, force_dvi); 2198 2199 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 2200 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) 2201 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, 2202 true, force_dvi); 2203 } 2204 if (status != MODE_OK) 2205 return status; 2206 2207 return intel_mode_valid_max_plane_size(dev_priv, mode); 2208 } 2209 2210 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2211 int bpc) 2212 { 2213 struct drm_i915_private *dev_priv = 2214 to_i915(crtc_state->uapi.crtc->dev); 2215 struct drm_atomic_state *state = crtc_state->uapi.state; 2216 struct drm_connector_state *connector_state; 2217 struct drm_connector *connector; 2218 const struct drm_display_mode *adjusted_mode = 2219 &crtc_state->hw.adjusted_mode; 2220 int i; 2221 2222 if (HAS_GMCH(dev_priv)) 2223 return false; 2224 2225 if (bpc == 10 && INTEL_GEN(dev_priv) < 11) 2226 return false; 2227 2228 if (crtc_state->pipe_bpp < bpc * 3) 2229 return false; 2230 2231 if (!crtc_state->has_hdmi_sink) 2232 return false; 2233 2234 /* 2235 * HDMI deep color affects the clocks, so it's only possible 2236 * when not cloning with other encoder types. 2237 */ 2238 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) 2239 return false; 2240 2241 for_each_new_connector_in_state(state, connector, connector_state, i) { 2242 const struct drm_display_info *info = &connector->display_info; 2243 2244 if (connector_state->crtc != crtc_state->uapi.crtc) 2245 continue; 2246 2247 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2248 const struct drm_hdmi_info *hdmi = &info->hdmi; 2249 2250 if (bpc == 12 && !(hdmi->y420_dc_modes & 2251 DRM_EDID_YCBCR420_DC_36)) 2252 return false; 2253 else if (bpc == 10 && !(hdmi->y420_dc_modes & 2254 DRM_EDID_YCBCR420_DC_30)) 2255 return false; 2256 } else { 2257 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 2258 DRM_EDID_HDMI_DC_36)) 2259 return false; 2260 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 2261 DRM_EDID_HDMI_DC_30)) 2262 return false; 2263 } 2264 } 2265 2266 /* Display WA #1139: glk */ 2267 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && 2268 adjusted_mode->htotal > 5460) 2269 return false; 2270 2271 /* Display Wa_1405510057:icl */ 2272 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2273 bpc == 10 && INTEL_GEN(dev_priv) >= 11 && 2274 (adjusted_mode->crtc_hblank_end - 2275 adjusted_mode->crtc_hblank_start) % 8 == 2) 2276 return false; 2277 2278 return true; 2279 } 2280 2281 static bool 2282 intel_hdmi_ycbcr420_config(struct drm_connector *connector, 2283 struct intel_crtc_state *config) 2284 { 2285 struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc); 2286 2287 if (!connector->ycbcr_420_allowed) { 2288 DRM_ERROR("Platform doesn't support YCBCR420 output\n"); 2289 return false; 2290 } 2291 2292 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2293 2294 /* YCBCR 420 output conversion needs a scaler */ 2295 if (skl_update_scaler_crtc(config)) { 2296 DRM_DEBUG_KMS("Scaler allocation for output failed\n"); 2297 return false; 2298 } 2299 2300 intel_pch_panel_fitting(intel_crtc, config, 2301 DRM_MODE_SCALE_FULLSCREEN); 2302 2303 return true; 2304 } 2305 2306 static int intel_hdmi_port_clock(int clock, int bpc) 2307 { 2308 /* 2309 * Need to adjust the port link by: 2310 * 1.5x for 12bpc 2311 * 1.25x for 10bpc 2312 */ 2313 return clock * bpc / 8; 2314 } 2315 2316 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2317 struct intel_crtc_state *crtc_state, 2318 int clock, bool force_dvi) 2319 { 2320 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2321 int bpc; 2322 2323 for (bpc = 12; bpc >= 10; bpc -= 2) { 2324 if (hdmi_deep_color_possible(crtc_state, bpc) && 2325 hdmi_port_clock_valid(intel_hdmi, 2326 intel_hdmi_port_clock(clock, bpc), 2327 true, force_dvi) == MODE_OK) 2328 return bpc; 2329 } 2330 2331 return 8; 2332 } 2333 2334 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2335 struct intel_crtc_state *crtc_state, 2336 bool force_dvi) 2337 { 2338 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2339 const struct drm_display_mode *adjusted_mode = 2340 &crtc_state->hw.adjusted_mode; 2341 int bpc, clock = adjusted_mode->crtc_clock; 2342 2343 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2344 clock *= 2; 2345 2346 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2347 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2348 clock /= 2; 2349 2350 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, 2351 clock, force_dvi); 2352 2353 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2354 2355 /* 2356 * pipe_bpp could already be below 8bpc due to 2357 * FDI bandwidth constraints. We shouldn't bump it 2358 * back up to 8bpc in that case. 2359 */ 2360 if (crtc_state->pipe_bpp > bpc * 3) 2361 crtc_state->pipe_bpp = bpc * 3; 2362 2363 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n", 2364 bpc, crtc_state->pipe_bpp); 2365 2366 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2367 false, force_dvi) != MODE_OK) { 2368 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", 2369 crtc_state->port_clock); 2370 return -EINVAL; 2371 } 2372 2373 return 0; 2374 } 2375 2376 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2377 const struct drm_connector_state *conn_state) 2378 { 2379 const struct intel_digital_connector_state *intel_conn_state = 2380 to_intel_digital_connector_state(conn_state); 2381 const struct drm_display_mode *adjusted_mode = 2382 &crtc_state->hw.adjusted_mode; 2383 2384 /* 2385 * Our YCbCr output is always limited range. 2386 * crtc_state->limited_color_range only applies to RGB, 2387 * and it must never be set for YCbCr or we risk setting 2388 * some conflicting bits in PIPECONF which will mess up 2389 * the colors on the monitor. 2390 */ 2391 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2392 return false; 2393 2394 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2395 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2396 return crtc_state->has_hdmi_sink && 2397 drm_default_rgb_quant_range(adjusted_mode) == 2398 HDMI_QUANTIZATION_RANGE_LIMITED; 2399 } else { 2400 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2401 } 2402 } 2403 2404 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2405 struct intel_crtc_state *pipe_config, 2406 struct drm_connector_state *conn_state) 2407 { 2408 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2410 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2411 struct drm_connector *connector = conn_state->connector; 2412 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2413 struct intel_digital_connector_state *intel_conn_state = 2414 to_intel_digital_connector_state(conn_state); 2415 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; 2416 int ret; 2417 2418 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2419 return -EINVAL; 2420 2421 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2422 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; 2423 2424 if (pipe_config->has_hdmi_sink) 2425 pipe_config->has_infoframe = true; 2426 2427 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2428 pipe_config->pixel_multiplier = 2; 2429 2430 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { 2431 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) { 2432 DRM_ERROR("Can't support YCBCR420 output\n"); 2433 return -EINVAL; 2434 } 2435 } 2436 2437 pipe_config->limited_color_range = 2438 intel_hdmi_limited_color_range(pipe_config, conn_state); 2439 2440 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2441 pipe_config->has_pch_encoder = true; 2442 2443 if (pipe_config->has_hdmi_sink) { 2444 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2445 pipe_config->has_audio = intel_hdmi->has_audio; 2446 else 2447 pipe_config->has_audio = 2448 intel_conn_state->force_audio == HDMI_AUDIO_ON; 2449 } 2450 2451 ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi); 2452 if (ret) 2453 return ret; 2454 2455 if (conn_state->picture_aspect_ratio) 2456 adjusted_mode->picture_aspect_ratio = 2457 conn_state->picture_aspect_ratio; 2458 2459 pipe_config->lane_count = 4; 2460 2461 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || 2462 IS_GEMINILAKE(dev_priv))) { 2463 if (scdc->scrambling.low_rates) 2464 pipe_config->hdmi_scrambling = true; 2465 2466 if (pipe_config->port_clock > 340000) { 2467 pipe_config->hdmi_scrambling = true; 2468 pipe_config->hdmi_high_tmds_clock_ratio = true; 2469 } 2470 } 2471 2472 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); 2473 2474 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2475 DRM_DEBUG_KMS("bad AVI infoframe\n"); 2476 return -EINVAL; 2477 } 2478 2479 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2480 DRM_DEBUG_KMS("bad SPD infoframe\n"); 2481 return -EINVAL; 2482 } 2483 2484 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2485 DRM_DEBUG_KMS("bad HDMI infoframe\n"); 2486 return -EINVAL; 2487 } 2488 2489 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2490 DRM_DEBUG_KMS("bad DRM infoframe\n"); 2491 return -EINVAL; 2492 } 2493 2494 return 0; 2495 } 2496 2497 static void 2498 intel_hdmi_unset_edid(struct drm_connector *connector) 2499 { 2500 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2501 2502 intel_hdmi->has_hdmi_sink = false; 2503 intel_hdmi->has_audio = false; 2504 2505 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2506 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2507 2508 kfree(to_intel_connector(connector)->detect_edid); 2509 to_intel_connector(connector)->detect_edid = NULL; 2510 } 2511 2512 static void 2513 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2514 { 2515 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2516 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2517 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2518 struct i2c_adapter *adapter = 2519 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2520 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 2521 2522 /* 2523 * Type 1 DVI adaptors are not required to implement any 2524 * registers, so we can't always detect their presence. 2525 * Ideally we should be able to check the state of the 2526 * CONFIG1 pin, but no such luck on our hardware. 2527 * 2528 * The only method left to us is to check the VBT to see 2529 * if the port is a dual mode capable DP port. But let's 2530 * only do that when we sucesfully read the EDID, to avoid 2531 * confusing log messages about DP dual mode adaptors when 2532 * there's nothing connected to the port. 2533 */ 2534 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2535 /* An overridden EDID imply that we want this port for testing. 2536 * Make sure not to set limits for that port. 2537 */ 2538 if (has_edid && !connector->override_edid && 2539 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2540 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 2541 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2542 } else { 2543 type = DRM_DP_DUAL_MODE_NONE; 2544 } 2545 } 2546 2547 if (type == DRM_DP_DUAL_MODE_NONE) 2548 return; 2549 2550 hdmi->dp_dual_mode.type = type; 2551 hdmi->dp_dual_mode.max_tmds_clock = 2552 drm_dp_dual_mode_max_tmds_clock(type, adapter); 2553 2554 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2555 drm_dp_get_dual_mode_type_name(type), 2556 hdmi->dp_dual_mode.max_tmds_clock); 2557 } 2558 2559 static bool 2560 intel_hdmi_set_edid(struct drm_connector *connector) 2561 { 2562 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2563 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2564 intel_wakeref_t wakeref; 2565 struct edid *edid; 2566 bool connected = false; 2567 struct i2c_adapter *i2c; 2568 2569 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2570 2571 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2572 2573 edid = drm_get_edid(connector, i2c); 2574 2575 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2576 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2577 intel_gmbus_force_bit(i2c, true); 2578 edid = drm_get_edid(connector, i2c); 2579 intel_gmbus_force_bit(i2c, false); 2580 } 2581 2582 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2583 2584 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2585 2586 to_intel_connector(connector)->detect_edid = edid; 2587 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2588 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2589 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2590 2591 connected = true; 2592 } 2593 2594 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2595 2596 return connected; 2597 } 2598 2599 static enum drm_connector_status 2600 intel_hdmi_detect(struct drm_connector *connector, bool force) 2601 { 2602 enum drm_connector_status status = connector_status_disconnected; 2603 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2604 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2605 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2606 intel_wakeref_t wakeref; 2607 2608 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2609 connector->base.id, connector->name); 2610 2611 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2612 2613 if (INTEL_GEN(dev_priv) >= 11 && 2614 !intel_digital_port_connected(encoder)) 2615 goto out; 2616 2617 intel_hdmi_unset_edid(connector); 2618 2619 if (intel_hdmi_set_edid(connector)) 2620 status = connector_status_connected; 2621 2622 out: 2623 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2624 2625 if (status != connector_status_connected) 2626 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2627 2628 /* 2629 * Make sure the refs for power wells enabled during detect are 2630 * dropped to avoid a new detect cycle triggered by HPD polling. 2631 */ 2632 intel_display_power_flush_work(dev_priv); 2633 2634 return status; 2635 } 2636 2637 static void 2638 intel_hdmi_force(struct drm_connector *connector) 2639 { 2640 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2641 connector->base.id, connector->name); 2642 2643 intel_hdmi_unset_edid(connector); 2644 2645 if (connector->status != connector_status_connected) 2646 return; 2647 2648 intel_hdmi_set_edid(connector); 2649 } 2650 2651 static int intel_hdmi_get_modes(struct drm_connector *connector) 2652 { 2653 struct edid *edid; 2654 2655 edid = to_intel_connector(connector)->detect_edid; 2656 if (edid == NULL) 2657 return 0; 2658 2659 return intel_connector_update_modes(connector, edid); 2660 } 2661 2662 static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 2663 const struct intel_crtc_state *pipe_config, 2664 const struct drm_connector_state *conn_state) 2665 { 2666 struct intel_digital_port *intel_dig_port = 2667 enc_to_dig_port(encoder); 2668 2669 intel_hdmi_prepare(encoder, pipe_config); 2670 2671 intel_dig_port->set_infoframes(encoder, 2672 pipe_config->has_infoframe, 2673 pipe_config, conn_state); 2674 } 2675 2676 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 2677 const struct intel_crtc_state *pipe_config, 2678 const struct drm_connector_state *conn_state) 2679 { 2680 struct intel_digital_port *dport = enc_to_dig_port(encoder); 2681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2682 2683 vlv_phy_pre_encoder_enable(encoder, pipe_config); 2684 2685 /* HDMI 1.0V-2dB */ 2686 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 2687 0x2b247878); 2688 2689 dport->set_infoframes(encoder, 2690 pipe_config->has_infoframe, 2691 pipe_config, conn_state); 2692 2693 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2694 2695 vlv_wait_port_ready(dev_priv, dport, 0x0); 2696 } 2697 2698 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2699 const struct intel_crtc_state *pipe_config, 2700 const struct drm_connector_state *conn_state) 2701 { 2702 intel_hdmi_prepare(encoder, pipe_config); 2703 2704 vlv_phy_pre_pll_enable(encoder, pipe_config); 2705 } 2706 2707 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2708 const struct intel_crtc_state *pipe_config, 2709 const struct drm_connector_state *conn_state) 2710 { 2711 intel_hdmi_prepare(encoder, pipe_config); 2712 2713 chv_phy_pre_pll_enable(encoder, pipe_config); 2714 } 2715 2716 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 2717 const struct intel_crtc_state *old_crtc_state, 2718 const struct drm_connector_state *old_conn_state) 2719 { 2720 chv_phy_post_pll_disable(encoder, old_crtc_state); 2721 } 2722 2723 static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 2724 const struct intel_crtc_state *old_crtc_state, 2725 const struct drm_connector_state *old_conn_state) 2726 { 2727 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 2728 vlv_phy_reset_lanes(encoder, old_crtc_state); 2729 } 2730 2731 static void chv_hdmi_post_disable(struct intel_encoder *encoder, 2732 const struct intel_crtc_state *old_crtc_state, 2733 const struct drm_connector_state *old_conn_state) 2734 { 2735 struct drm_device *dev = encoder->base.dev; 2736 struct drm_i915_private *dev_priv = to_i915(dev); 2737 2738 vlv_dpio_get(dev_priv); 2739 2740 /* Assert data lane reset */ 2741 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 2742 2743 vlv_dpio_put(dev_priv); 2744 } 2745 2746 static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 2747 const struct intel_crtc_state *pipe_config, 2748 const struct drm_connector_state *conn_state) 2749 { 2750 struct intel_digital_port *dport = enc_to_dig_port(encoder); 2751 struct drm_device *dev = encoder->base.dev; 2752 struct drm_i915_private *dev_priv = to_i915(dev); 2753 2754 chv_phy_pre_encoder_enable(encoder, pipe_config); 2755 2756 /* FIXME: Program the support xxx V-dB */ 2757 /* Use 800mV-0dB */ 2758 chv_set_phy_signal_level(encoder, 128, 102, false); 2759 2760 dport->set_infoframes(encoder, 2761 pipe_config->has_infoframe, 2762 pipe_config, conn_state); 2763 2764 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2765 2766 vlv_wait_port_ready(dev_priv, dport, 0x0); 2767 2768 /* Second common lane will stay alive on its own now */ 2769 chv_phy_release_cl2_override(encoder); 2770 } 2771 2772 static struct i2c_adapter * 2773 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2774 { 2775 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2776 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2777 2778 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2779 } 2780 2781 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2782 { 2783 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2784 struct kobject *i2c_kobj = &adapter->dev.kobj; 2785 struct kobject *connector_kobj = &connector->kdev->kobj; 2786 int ret; 2787 2788 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2789 if (ret) 2790 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); 2791 } 2792 2793 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2794 { 2795 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2796 struct kobject *i2c_kobj = &adapter->dev.kobj; 2797 struct kobject *connector_kobj = &connector->kdev->kobj; 2798 2799 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2800 } 2801 2802 static int 2803 intel_hdmi_connector_register(struct drm_connector *connector) 2804 { 2805 int ret; 2806 2807 ret = intel_connector_register(connector); 2808 if (ret) 2809 return ret; 2810 2811 i915_debugfs_connector_add(connector); 2812 2813 intel_hdmi_create_i2c_symlink(connector); 2814 2815 return ret; 2816 } 2817 2818 static void intel_hdmi_destroy(struct drm_connector *connector) 2819 { 2820 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2821 2822 cec_notifier_conn_unregister(n); 2823 2824 intel_connector_destroy(connector); 2825 } 2826 2827 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2828 { 2829 intel_hdmi_remove_i2c_symlink(connector); 2830 2831 intel_connector_unregister(connector); 2832 } 2833 2834 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2835 .detect = intel_hdmi_detect, 2836 .force = intel_hdmi_force, 2837 .fill_modes = drm_helper_probe_single_connector_modes, 2838 .atomic_get_property = intel_digital_connector_atomic_get_property, 2839 .atomic_set_property = intel_digital_connector_atomic_set_property, 2840 .late_register = intel_hdmi_connector_register, 2841 .early_unregister = intel_hdmi_connector_unregister, 2842 .destroy = intel_hdmi_destroy, 2843 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2844 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2845 }; 2846 2847 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2848 .get_modes = intel_hdmi_get_modes, 2849 .mode_valid = intel_hdmi_mode_valid, 2850 .atomic_check = intel_digital_connector_atomic_check, 2851 }; 2852 2853 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2854 .destroy = intel_encoder_destroy, 2855 }; 2856 2857 static void 2858 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2859 { 2860 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2861 struct intel_digital_port *intel_dig_port = 2862 hdmi_to_dig_port(intel_hdmi); 2863 2864 intel_attach_force_audio_property(connector); 2865 intel_attach_broadcast_rgb_property(connector); 2866 intel_attach_aspect_ratio_property(connector); 2867 2868 /* 2869 * Attach Colorspace property for Non LSPCON based device 2870 * ToDo: This needs to be extended for LSPCON implementation 2871 * as well. Will be implemented separately. 2872 */ 2873 if (!intel_dig_port->lspcon.active) 2874 intel_attach_colorspace_property(connector); 2875 2876 drm_connector_attach_content_type_property(connector); 2877 2878 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2879 drm_object_attach_property(&connector->base, 2880 connector->dev->mode_config.hdr_output_metadata_property, 0); 2881 2882 if (!HAS_GMCH(dev_priv)) 2883 drm_connector_attach_max_bpc_property(connector, 8, 12); 2884 } 2885 2886 /* 2887 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2888 * @encoder: intel_encoder 2889 * @connector: drm_connector 2890 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2891 * or reset the high tmds clock ratio for scrambling 2892 * @scrambling: bool to Indicate if the function needs to set or reset 2893 * sink scrambling 2894 * 2895 * This function handles scrambling on HDMI 2.0 capable sinks. 2896 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2897 * it enables scrambling. This should be called before enabling the HDMI 2898 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2899 * detect a scrambled clock within 100 ms. 2900 * 2901 * Returns: 2902 * True on success, false on failure. 2903 */ 2904 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2905 struct drm_connector *connector, 2906 bool high_tmds_clock_ratio, 2907 bool scrambling) 2908 { 2909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2910 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2911 struct drm_scrambling *sink_scrambling = 2912 &connector->display_info.hdmi.scdc.scrambling; 2913 struct i2c_adapter *adapter = 2914 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2915 2916 if (!sink_scrambling->supported) 2917 return true; 2918 2919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2920 connector->base.id, connector->name, 2921 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2922 2923 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2924 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2925 high_tmds_clock_ratio) && 2926 drm_scdc_set_scrambling(adapter, scrambling); 2927 } 2928 2929 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2930 { 2931 u8 ddc_pin; 2932 2933 switch (port) { 2934 case PORT_B: 2935 ddc_pin = GMBUS_PIN_DPB; 2936 break; 2937 case PORT_C: 2938 ddc_pin = GMBUS_PIN_DPC; 2939 break; 2940 case PORT_D: 2941 ddc_pin = GMBUS_PIN_DPD_CHV; 2942 break; 2943 default: 2944 MISSING_CASE(port); 2945 ddc_pin = GMBUS_PIN_DPB; 2946 break; 2947 } 2948 return ddc_pin; 2949 } 2950 2951 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2952 { 2953 u8 ddc_pin; 2954 2955 switch (port) { 2956 case PORT_B: 2957 ddc_pin = GMBUS_PIN_1_BXT; 2958 break; 2959 case PORT_C: 2960 ddc_pin = GMBUS_PIN_2_BXT; 2961 break; 2962 default: 2963 MISSING_CASE(port); 2964 ddc_pin = GMBUS_PIN_1_BXT; 2965 break; 2966 } 2967 return ddc_pin; 2968 } 2969 2970 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2971 enum port port) 2972 { 2973 u8 ddc_pin; 2974 2975 switch (port) { 2976 case PORT_B: 2977 ddc_pin = GMBUS_PIN_1_BXT; 2978 break; 2979 case PORT_C: 2980 ddc_pin = GMBUS_PIN_2_BXT; 2981 break; 2982 case PORT_D: 2983 ddc_pin = GMBUS_PIN_4_CNP; 2984 break; 2985 case PORT_F: 2986 ddc_pin = GMBUS_PIN_3_BXT; 2987 break; 2988 default: 2989 MISSING_CASE(port); 2990 ddc_pin = GMBUS_PIN_1_BXT; 2991 break; 2992 } 2993 return ddc_pin; 2994 } 2995 2996 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2997 { 2998 enum phy phy = intel_port_to_phy(dev_priv, port); 2999 3000 if (intel_phy_is_combo(dev_priv, phy)) 3001 return GMBUS_PIN_1_BXT + port; 3002 else if (intel_phy_is_tc(dev_priv, phy)) 3003 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 3004 3005 WARN(1, "Unknown port:%c\n", port_name(port)); 3006 return GMBUS_PIN_2_BXT; 3007 } 3008 3009 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3010 { 3011 enum phy phy = intel_port_to_phy(dev_priv, port); 3012 u8 ddc_pin; 3013 3014 switch (phy) { 3015 case PHY_A: 3016 ddc_pin = GMBUS_PIN_1_BXT; 3017 break; 3018 case PHY_B: 3019 ddc_pin = GMBUS_PIN_2_BXT; 3020 break; 3021 case PHY_C: 3022 ddc_pin = GMBUS_PIN_9_TC1_ICP; 3023 break; 3024 default: 3025 MISSING_CASE(phy); 3026 ddc_pin = GMBUS_PIN_1_BXT; 3027 break; 3028 } 3029 return ddc_pin; 3030 } 3031 3032 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3033 enum port port) 3034 { 3035 u8 ddc_pin; 3036 3037 switch (port) { 3038 case PORT_B: 3039 ddc_pin = GMBUS_PIN_DPB; 3040 break; 3041 case PORT_C: 3042 ddc_pin = GMBUS_PIN_DPC; 3043 break; 3044 case PORT_D: 3045 ddc_pin = GMBUS_PIN_DPD; 3046 break; 3047 default: 3048 MISSING_CASE(port); 3049 ddc_pin = GMBUS_PIN_DPB; 3050 break; 3051 } 3052 return ddc_pin; 3053 } 3054 3055 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 3056 enum port port) 3057 { 3058 const struct ddi_vbt_port_info *info = 3059 &dev_priv->vbt.ddi_port_info[port]; 3060 u8 ddc_pin; 3061 3062 if (info->alternate_ddc_pin) { 3063 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 3064 info->alternate_ddc_pin, port_name(port)); 3065 return info->alternate_ddc_pin; 3066 } 3067 3068 if (HAS_PCH_MCC(dev_priv)) 3069 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 3070 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3071 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 3072 else if (HAS_PCH_CNP(dev_priv)) 3073 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 3074 else if (IS_GEN9_LP(dev_priv)) 3075 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 3076 else if (IS_CHERRYVIEW(dev_priv)) 3077 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 3078 else 3079 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 3080 3081 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 3082 ddc_pin, port_name(port)); 3083 3084 return ddc_pin; 3085 } 3086 3087 void intel_infoframe_init(struct intel_digital_port *intel_dig_port) 3088 { 3089 struct drm_i915_private *dev_priv = 3090 to_i915(intel_dig_port->base.base.dev); 3091 3092 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3093 intel_dig_port->write_infoframe = vlv_write_infoframe; 3094 intel_dig_port->read_infoframe = vlv_read_infoframe; 3095 intel_dig_port->set_infoframes = vlv_set_infoframes; 3096 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; 3097 } else if (IS_G4X(dev_priv)) { 3098 intel_dig_port->write_infoframe = g4x_write_infoframe; 3099 intel_dig_port->read_infoframe = g4x_read_infoframe; 3100 intel_dig_port->set_infoframes = g4x_set_infoframes; 3101 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; 3102 } else if (HAS_DDI(dev_priv)) { 3103 if (intel_dig_port->lspcon.active) { 3104 intel_dig_port->write_infoframe = lspcon_write_infoframe; 3105 intel_dig_port->read_infoframe = lspcon_read_infoframe; 3106 intel_dig_port->set_infoframes = lspcon_set_infoframes; 3107 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3108 } else { 3109 intel_dig_port->write_infoframe = hsw_write_infoframe; 3110 intel_dig_port->read_infoframe = hsw_read_infoframe; 3111 intel_dig_port->set_infoframes = hsw_set_infoframes; 3112 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; 3113 } 3114 } else if (HAS_PCH_IBX(dev_priv)) { 3115 intel_dig_port->write_infoframe = ibx_write_infoframe; 3116 intel_dig_port->read_infoframe = ibx_read_infoframe; 3117 intel_dig_port->set_infoframes = ibx_set_infoframes; 3118 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; 3119 } else { 3120 intel_dig_port->write_infoframe = cpt_write_infoframe; 3121 intel_dig_port->read_infoframe = cpt_read_infoframe; 3122 intel_dig_port->set_infoframes = cpt_set_infoframes; 3123 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; 3124 } 3125 } 3126 3127 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 3128 struct intel_connector *intel_connector) 3129 { 3130 struct drm_connector *connector = &intel_connector->base; 3131 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3132 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3133 struct drm_device *dev = intel_encoder->base.dev; 3134 struct drm_i915_private *dev_priv = to_i915(dev); 3135 struct i2c_adapter *ddc; 3136 enum port port = intel_encoder->port; 3137 struct cec_connector_info conn_info; 3138 3139 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", 3140 intel_encoder->base.base.id, intel_encoder->base.name); 3141 3142 if (INTEL_GEN(dev_priv) < 12 && WARN_ON(port == PORT_A)) 3143 return; 3144 3145 if (WARN(intel_dig_port->max_lanes < 4, 3146 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3147 intel_dig_port->max_lanes, intel_encoder->base.base.id, 3148 intel_encoder->base.name)) 3149 return; 3150 3151 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); 3152 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3153 3154 drm_connector_init_with_ddc(dev, connector, 3155 &intel_hdmi_connector_funcs, 3156 DRM_MODE_CONNECTOR_HDMIA, 3157 ddc); 3158 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3159 3160 connector->interlace_allowed = 1; 3161 connector->doublescan_allowed = 0; 3162 connector->stereo_allowed = 1; 3163 3164 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3165 connector->ycbcr_420_allowed = true; 3166 3167 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 3168 3169 if (HAS_DDI(dev_priv)) 3170 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3171 else 3172 intel_connector->get_hw_state = intel_connector_get_hw_state; 3173 3174 intel_hdmi_add_properties(intel_hdmi, connector); 3175 3176 intel_connector_attach_encoder(intel_connector, intel_encoder); 3177 intel_hdmi->attached_connector = intel_connector; 3178 3179 if (is_hdcp_supported(dev_priv, port)) { 3180 int ret = intel_hdcp_init(intel_connector, 3181 &intel_hdmi_hdcp_shim); 3182 if (ret) 3183 DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); 3184 } 3185 3186 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3187 * 0xd. Failure to do so will result in spurious interrupts being 3188 * generated on the port when a cable is not attached. 3189 */ 3190 if (IS_G45(dev_priv)) { 3191 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3192 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3193 } 3194 3195 cec_fill_conn_info_from_drm(&conn_info, connector); 3196 3197 intel_hdmi->cec_notifier = 3198 cec_notifier_conn_register(dev->dev, port_identifier(port), 3199 &conn_info); 3200 if (!intel_hdmi->cec_notifier) 3201 DRM_DEBUG_KMS("CEC notifier get failed\n"); 3202 } 3203 3204 static enum intel_hotplug_state 3205 intel_hdmi_hotplug(struct intel_encoder *encoder, 3206 struct intel_connector *connector, bool irq_received) 3207 { 3208 enum intel_hotplug_state state; 3209 3210 state = intel_encoder_hotplug(encoder, connector, irq_received); 3211 3212 /* 3213 * On many platforms the HDMI live state signal is known to be 3214 * unreliable, so we can't use it to detect if a sink is connected or 3215 * not. Instead we detect if it's connected based on whether we can 3216 * read the EDID or not. That in turn has a problem during disconnect, 3217 * since the HPD interrupt may be raised before the DDC lines get 3218 * disconnected (due to how the required length of DDC vs. HPD 3219 * connector pins are specified) and so we'll still be able to get a 3220 * valid EDID. To solve this schedule another detection cycle if this 3221 * time around we didn't detect any change in the sink's connection 3222 * status. 3223 */ 3224 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) 3225 state = INTEL_HOTPLUG_RETRY; 3226 3227 return state; 3228 } 3229 3230 void intel_hdmi_init(struct drm_i915_private *dev_priv, 3231 i915_reg_t hdmi_reg, enum port port) 3232 { 3233 struct intel_digital_port *intel_dig_port; 3234 struct intel_encoder *intel_encoder; 3235 struct intel_connector *intel_connector; 3236 3237 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3238 if (!intel_dig_port) 3239 return; 3240 3241 intel_connector = intel_connector_alloc(); 3242 if (!intel_connector) { 3243 kfree(intel_dig_port); 3244 return; 3245 } 3246 3247 intel_encoder = &intel_dig_port->base; 3248 3249 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3250 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 3251 "HDMI %c", port_name(port)); 3252 3253 intel_encoder->hotplug = intel_hdmi_hotplug; 3254 intel_encoder->compute_config = intel_hdmi_compute_config; 3255 if (HAS_PCH_SPLIT(dev_priv)) { 3256 intel_encoder->disable = pch_disable_hdmi; 3257 intel_encoder->post_disable = pch_post_disable_hdmi; 3258 } else { 3259 intel_encoder->disable = g4x_disable_hdmi; 3260 } 3261 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 3262 intel_encoder->get_config = intel_hdmi_get_config; 3263 if (IS_CHERRYVIEW(dev_priv)) { 3264 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 3265 intel_encoder->pre_enable = chv_hdmi_pre_enable; 3266 intel_encoder->enable = vlv_enable_hdmi; 3267 intel_encoder->post_disable = chv_hdmi_post_disable; 3268 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 3269 } else if (IS_VALLEYVIEW(dev_priv)) { 3270 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 3271 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 3272 intel_encoder->enable = vlv_enable_hdmi; 3273 intel_encoder->post_disable = vlv_hdmi_post_disable; 3274 } else { 3275 intel_encoder->pre_enable = intel_hdmi_pre_enable; 3276 if (HAS_PCH_CPT(dev_priv)) 3277 intel_encoder->enable = cpt_enable_hdmi; 3278 else if (HAS_PCH_IBX(dev_priv)) 3279 intel_encoder->enable = ibx_enable_hdmi; 3280 else 3281 intel_encoder->enable = g4x_enable_hdmi; 3282 } 3283 3284 intel_encoder->type = INTEL_OUTPUT_HDMI; 3285 intel_encoder->power_domain = intel_port_to_power_domain(port); 3286 intel_encoder->port = port; 3287 if (IS_CHERRYVIEW(dev_priv)) { 3288 if (port == PORT_D) 3289 intel_encoder->pipe_mask = BIT(PIPE_C); 3290 else 3291 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 3292 } else { 3293 intel_encoder->pipe_mask = ~0; 3294 } 3295 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 3296 /* 3297 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 3298 * to work on real hardware. And since g4x can send infoframes to 3299 * only one port anyway, nothing is lost by allowing it. 3300 */ 3301 if (IS_G4X(dev_priv)) 3302 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 3303 3304 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 3305 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 3306 intel_dig_port->max_lanes = 4; 3307 3308 intel_infoframe_init(intel_dig_port); 3309 3310 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 3311 intel_hdmi_init_connector(intel_dig_port, intel_connector); 3312 } 3313