1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 #include "amdgpu_dm_crc.h" 54 55 /* Forward declarations */ 56 struct amdgpu_device; 57 struct drm_device; 58 struct amdgpu_dm_irq_handler_data; 59 struct dc; 60 struct amdgpu_bo; 61 struct dmub_srv; 62 63 struct common_irq_params { 64 struct amdgpu_device *adev; 65 enum dc_irq_source irq_src; 66 }; 67 68 /** 69 * struct irq_list_head - Linked-list for low context IRQ handlers. 70 * 71 * @head: The list_head within &struct handler_data 72 * @work: A work_struct containing the deferred handler work 73 */ 74 struct irq_list_head { 75 struct list_head head; 76 /* In case this interrupt needs post-processing, 'work' will be queued*/ 77 struct work_struct work; 78 }; 79 80 /** 81 * struct dm_compressor_info - Buffer info used by frame buffer compression 82 * @cpu_addr: MMIO cpu addr 83 * @bo_ptr: Pointer to the buffer object 84 * @gpu_addr: MMIO gpu addr 85 */ 86 struct dm_comressor_info { 87 void *cpu_addr; 88 struct amdgpu_bo *bo_ptr; 89 uint64_t gpu_addr; 90 }; 91 92 /** 93 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 94 * @min_input_signal: minimum possible input in range 0-255 95 * @max_input_signal: maximum possible input in range 0-255 96 * @caps_valid: true if these values are from the ACPI interface 97 */ 98 struct amdgpu_dm_backlight_caps { 99 int min_input_signal; 100 int max_input_signal; 101 bool caps_valid; 102 }; 103 104 /** 105 * struct amdgpu_display_manager - Central amdgpu display manager device 106 * 107 * @dc: Display Core control structure 108 * @adev: AMDGPU base driver structure 109 * @ddev: DRM base driver structure 110 * @display_indexes_num: Max number of display streams supported 111 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 112 * @backlight_dev: Backlight control device 113 * @backlight_link: Link on which to control backlight 114 * @backlight_caps: Capabilities of the backlight device 115 * @freesync_module: Module handling freesync calculations 116 * @fw_dmcu: Reference to DMCU firmware 117 * @dmcu_fw_version: Version of the DMCU firmware 118 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 119 * @cached_state: Caches device atomic state for suspend/resume 120 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 121 */ 122 struct amdgpu_display_manager { 123 124 struct dc *dc; 125 126 /** 127 * @dmub_srv: 128 * 129 * DMUB service, used for controlling the DMUB on hardware 130 * that supports it. The pointer to the dmub_srv will be 131 * NULL on hardware that does not support it. 132 */ 133 struct dmub_srv *dmub_srv; 134 135 /** 136 * @dmub_fb_info: 137 * 138 * Framebuffer regions for the DMUB. 139 */ 140 struct dmub_srv_fb_info *dmub_fb_info; 141 142 /** 143 * @dmub_fw: 144 * 145 * DMUB firmware, required on hardware that has DMUB support. 146 */ 147 const struct firmware *dmub_fw; 148 149 /** 150 * @dmub_bo: 151 * 152 * Buffer object for the DMUB. 153 */ 154 struct amdgpu_bo *dmub_bo; 155 156 /** 157 * @dmub_bo_gpu_addr: 158 * 159 * GPU virtual address for the DMUB buffer object. 160 */ 161 u64 dmub_bo_gpu_addr; 162 163 /** 164 * @dmub_bo_cpu_addr: 165 * 166 * CPU address for the DMUB buffer object. 167 */ 168 void *dmub_bo_cpu_addr; 169 170 /** 171 * @dmcub_fw_version: 172 * 173 * DMCUB firmware version. 174 */ 175 uint32_t dmcub_fw_version; 176 177 /** 178 * @cgs_device: 179 * 180 * The Common Graphics Services device. It provides an interface for 181 * accessing registers. 182 */ 183 struct cgs_device *cgs_device; 184 185 struct amdgpu_device *adev; 186 struct drm_device *ddev; 187 u16 display_indexes_num; 188 189 /** 190 * @atomic_obj: 191 * 192 * In combination with &dm_atomic_state it helps manage 193 * global atomic state that doesn't map cleanly into existing 194 * drm resources, like &dc_context. 195 */ 196 struct drm_private_obj atomic_obj; 197 198 /** 199 * @dc_lock: 200 * 201 * Guards access to DC functions that can issue register write 202 * sequences. 203 */ 204 struct mutex dc_lock; 205 206 /** 207 * @audio_lock: 208 * 209 * Guards access to audio instance changes. 210 */ 211 struct mutex audio_lock; 212 213 /** 214 * @audio_component: 215 * 216 * Used to notify ELD changes to sound driver. 217 */ 218 struct drm_audio_component *audio_component; 219 220 /** 221 * @audio_registered: 222 * 223 * True if the audio component has been registered 224 * successfully, false otherwise. 225 */ 226 bool audio_registered; 227 228 /** 229 * @irq_handler_list_low_tab: 230 * 231 * Low priority IRQ handler table. 232 * 233 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 234 * source. Low priority IRQ handlers are deferred to a workqueue to be 235 * processed. Hence, they can sleep. 236 * 237 * Note that handlers are called in the same order as they were 238 * registered (FIFO). 239 */ 240 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 241 242 /** 243 * @irq_handler_list_high_tab: 244 * 245 * High priority IRQ handler table. 246 * 247 * It is a n*m table, same as &irq_handler_list_low_tab. However, 248 * handlers in this table are not deferred and are called immediately. 249 */ 250 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 251 252 /** 253 * @pflip_params: 254 * 255 * Page flip IRQ parameters, passed to registered handlers when 256 * triggered. 257 */ 258 struct common_irq_params 259 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 260 261 /** 262 * @vblank_params: 263 * 264 * Vertical blanking IRQ parameters, passed to registered handlers when 265 * triggered. 266 */ 267 struct common_irq_params 268 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 269 270 /** 271 * @vupdate_params: 272 * 273 * Vertical update IRQ parameters, passed to registered handlers when 274 * triggered. 275 */ 276 struct common_irq_params 277 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 278 279 spinlock_t irq_handler_list_table_lock; 280 281 struct backlight_device *backlight_dev; 282 283 const struct dc_link *backlight_link; 284 struct amdgpu_dm_backlight_caps backlight_caps; 285 286 struct mod_freesync *freesync_module; 287 #ifdef CONFIG_DRM_AMD_DC_HDCP 288 struct hdcp_workqueue *hdcp_workqueue; 289 #endif 290 291 struct drm_atomic_state *cached_state; 292 293 struct dm_comressor_info compressor; 294 295 const struct firmware *fw_dmcu; 296 uint32_t dmcu_fw_version; 297 /** 298 * @soc_bounding_box: 299 * 300 * gpu_info FW provided soc bounding box struct or 0 if not 301 * available in FW 302 */ 303 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 304 }; 305 306 struct amdgpu_dm_connector { 307 308 struct drm_connector base; 309 uint32_t connector_id; 310 311 /* we need to mind the EDID between detect 312 and get modes due to analog/digital/tvencoder */ 313 struct edid *edid; 314 315 /* shared with amdgpu */ 316 struct amdgpu_hpd hpd; 317 318 /* number of modes generated from EDID at 'dc_sink' */ 319 int num_modes; 320 321 /* The 'old' sink - before an HPD. 322 * The 'current' sink is in dc_link->sink. */ 323 struct dc_sink *dc_sink; 324 struct dc_link *dc_link; 325 struct dc_sink *dc_em_sink; 326 327 /* DM only */ 328 struct drm_dp_mst_topology_mgr mst_mgr; 329 struct amdgpu_dm_dp_aux dm_dp_aux; 330 struct drm_dp_mst_port *port; 331 struct amdgpu_dm_connector *mst_port; 332 struct amdgpu_encoder *mst_encoder; 333 struct drm_dp_aux *dsc_aux; 334 335 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 336 struct amdgpu_i2c_adapter *i2c; 337 338 /* Monitor range limits */ 339 int min_vfreq ; 340 int max_vfreq ; 341 int pixel_clock_mhz; 342 343 /* Audio instance - protected by audio_lock. */ 344 int audio_inst; 345 346 struct mutex hpd_lock; 347 348 bool fake_enable; 349 #ifdef CONFIG_DEBUG_FS 350 uint32_t debugfs_dpcd_address; 351 uint32_t debugfs_dpcd_size; 352 #endif 353 bool force_yuv420_output; 354 }; 355 356 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 357 358 extern const struct amdgpu_ip_block_version dm_ip_block; 359 360 struct amdgpu_framebuffer; 361 struct amdgpu_display_manager; 362 struct dc_validation_set; 363 struct dc_plane_state; 364 365 struct dm_plane_state { 366 struct drm_plane_state base; 367 struct dc_plane_state *dc_state; 368 }; 369 370 struct dm_crtc_state { 371 struct drm_crtc_state base; 372 struct dc_stream_state *stream; 373 374 bool cm_has_degamma; 375 bool cm_is_degamma_srgb; 376 377 int update_type; 378 int active_planes; 379 bool interrupts_enabled; 380 381 int crc_skip_count; 382 enum amdgpu_dm_pipe_crc_source crc_src; 383 384 bool freesync_timing_changed; 385 bool freesync_vrr_info_changed; 386 387 bool vrr_supported; 388 struct mod_freesync_config freesync_config; 389 struct mod_vrr_params vrr_params; 390 struct dc_info_packet vrr_infopacket; 391 392 int abm_level; 393 }; 394 395 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 396 397 struct dm_atomic_state { 398 struct drm_private_state base; 399 400 struct dc_state *context; 401 }; 402 403 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 404 405 struct dm_connector_state { 406 struct drm_connector_state base; 407 408 enum amdgpu_rmx_type scaling; 409 uint8_t underscan_vborder; 410 uint8_t underscan_hborder; 411 bool underscan_enable; 412 bool freesync_capable; 413 uint8_t abm_level; 414 int vcpi_slots; 415 uint64_t pbn; 416 }; 417 418 #define to_dm_connector_state(x)\ 419 container_of((x), struct dm_connector_state, base) 420 421 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 422 struct drm_connector_state * 423 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 424 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 425 struct drm_connector_state *state, 426 struct drm_property *property, 427 uint64_t val); 428 429 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 430 const struct drm_connector_state *state, 431 struct drm_property *property, 432 uint64_t *val); 433 434 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 435 436 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 437 struct amdgpu_dm_connector *aconnector, 438 int connector_type, 439 struct dc_link *link, 440 int link_index); 441 442 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 443 struct drm_display_mode *mode); 444 445 void dm_restore_drm_connector_state(struct drm_device *dev, 446 struct drm_connector *connector); 447 448 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 449 struct edid *edid); 450 451 #define MAX_COLOR_LUT_ENTRIES 4096 452 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 453 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 454 455 void amdgpu_dm_init_color_mod(void); 456 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 457 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 458 struct dc_plane_state *dc_plane_state); 459 460 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 461 462 #endif /* __AMDGPU_DM_H__ */ 463