1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020 MediaTek Corporation 4 * Copyright (c) 2020 BayLibre SAS 5 * 6 * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com> 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/compiler.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/etherdevice.h> 14 #include <linux/kernel.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/mii.h> 17 #include <linux/module.h> 18 #include <linux/netdevice.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm.h> 24 #include <linux/regmap.h> 25 #include <linux/skbuff.h> 26 #include <linux/spinlock.h> 27 #include <linux/workqueue.h> 28 29 #define MTK_STAR_DRVNAME "mtk_star_emac" 30 31 #define MTK_STAR_WAIT_TIMEOUT 300 32 #define MTK_STAR_MAX_FRAME_SIZE 1514 33 #define MTK_STAR_SKB_ALIGNMENT 16 34 #define MTK_STAR_NAPI_WEIGHT 64 35 #define MTK_STAR_HASHTABLE_MC_LIMIT 256 36 #define MTK_STAR_HASHTABLE_SIZE_MAX 512 37 38 /* Normally we'd use NET_IP_ALIGN but on arm64 its value is 0 and it doesn't 39 * work for this controller. 40 */ 41 #define MTK_STAR_IP_ALIGN 2 42 43 static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; 44 #define MTK_STAR_NCLKS ARRAY_SIZE(mtk_star_clk_names) 45 46 /* PHY Control Register 0 */ 47 #define MTK_STAR_REG_PHY_CTRL0 0x0000 48 #define MTK_STAR_BIT_PHY_CTRL0_WTCMD BIT(13) 49 #define MTK_STAR_BIT_PHY_CTRL0_RDCMD BIT(14) 50 #define MTK_STAR_BIT_PHY_CTRL0_RWOK BIT(15) 51 #define MTK_STAR_MSK_PHY_CTRL0_PREG GENMASK(12, 8) 52 #define MTK_STAR_OFF_PHY_CTRL0_PREG 8 53 #define MTK_STAR_MSK_PHY_CTRL0_RWDATA GENMASK(31, 16) 54 #define MTK_STAR_OFF_PHY_CTRL0_RWDATA 16 55 56 /* PHY Control Register 1 */ 57 #define MTK_STAR_REG_PHY_CTRL1 0x0004 58 #define MTK_STAR_BIT_PHY_CTRL1_LINK_ST BIT(0) 59 #define MTK_STAR_BIT_PHY_CTRL1_AN_EN BIT(8) 60 #define MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD 9 61 #define MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_10M 0x00 62 #define MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_100M 0x01 63 #define MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_1000M 0x02 64 #define MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX BIT(11) 65 #define MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX BIT(12) 66 #define MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX BIT(13) 67 68 /* MAC Configuration Register */ 69 #define MTK_STAR_REG_MAC_CFG 0x0008 70 #define MTK_STAR_OFF_MAC_CFG_IPG 10 71 #define MTK_STAR_VAL_MAC_CFG_IPG_96BIT GENMASK(4, 0) 72 #define MTK_STAR_BIT_MAC_CFG_MAXLEN_1522 BIT(16) 73 #define MTK_STAR_BIT_MAC_CFG_AUTO_PAD BIT(19) 74 #define MTK_STAR_BIT_MAC_CFG_CRC_STRIP BIT(20) 75 #define MTK_STAR_BIT_MAC_CFG_VLAN_STRIP BIT(22) 76 #define MTK_STAR_BIT_MAC_CFG_NIC_PD BIT(31) 77 78 /* Flow-Control Configuration Register */ 79 #define MTK_STAR_REG_FC_CFG 0x000c 80 #define MTK_STAR_BIT_FC_CFG_BP_EN BIT(7) 81 #define MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR BIT(8) 82 #define MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH 16 83 #define MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH GENMASK(27, 16) 84 #define MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K 0x800 85 86 /* ARL Configuration Register */ 87 #define MTK_STAR_REG_ARL_CFG 0x0010 88 #define MTK_STAR_BIT_ARL_CFG_HASH_ALG BIT(0) 89 #define MTK_STAR_BIT_ARL_CFG_MISC_MODE BIT(4) 90 91 /* MAC High and Low Bytes Registers */ 92 #define MTK_STAR_REG_MY_MAC_H 0x0014 93 #define MTK_STAR_REG_MY_MAC_L 0x0018 94 95 /* Hash Table Control Register */ 96 #define MTK_STAR_REG_HASH_CTRL 0x001c 97 #define MTK_STAR_MSK_HASH_CTRL_HASH_BIT_ADDR GENMASK(8, 0) 98 #define MTK_STAR_BIT_HASH_CTRL_HASH_BIT_DATA BIT(12) 99 #define MTK_STAR_BIT_HASH_CTRL_ACC_CMD BIT(13) 100 #define MTK_STAR_BIT_HASH_CTRL_CMD_START BIT(14) 101 #define MTK_STAR_BIT_HASH_CTRL_BIST_OK BIT(16) 102 #define MTK_STAR_BIT_HASH_CTRL_BIST_DONE BIT(17) 103 #define MTK_STAR_BIT_HASH_CTRL_BIST_EN BIT(31) 104 105 /* TX DMA Control Register */ 106 #define MTK_STAR_REG_TX_DMA_CTRL 0x0034 107 #define MTK_STAR_BIT_TX_DMA_CTRL_START BIT(0) 108 #define MTK_STAR_BIT_TX_DMA_CTRL_STOP BIT(1) 109 #define MTK_STAR_BIT_TX_DMA_CTRL_RESUME BIT(2) 110 111 /* RX DMA Control Register */ 112 #define MTK_STAR_REG_RX_DMA_CTRL 0x0038 113 #define MTK_STAR_BIT_RX_DMA_CTRL_START BIT(0) 114 #define MTK_STAR_BIT_RX_DMA_CTRL_STOP BIT(1) 115 #define MTK_STAR_BIT_RX_DMA_CTRL_RESUME BIT(2) 116 117 /* DMA Address Registers */ 118 #define MTK_STAR_REG_TX_DPTR 0x003c 119 #define MTK_STAR_REG_RX_DPTR 0x0040 120 #define MTK_STAR_REG_TX_BASE_ADDR 0x0044 121 #define MTK_STAR_REG_RX_BASE_ADDR 0x0048 122 123 /* Interrupt Status Register */ 124 #define MTK_STAR_REG_INT_STS 0x0050 125 #define MTK_STAR_REG_INT_STS_PORT_STS_CHG BIT(2) 126 #define MTK_STAR_REG_INT_STS_MIB_CNT_TH BIT(3) 127 #define MTK_STAR_BIT_INT_STS_FNRC BIT(6) 128 #define MTK_STAR_BIT_INT_STS_TNTC BIT(8) 129 130 /* Interrupt Mask Register */ 131 #define MTK_STAR_REG_INT_MASK 0x0054 132 #define MTK_STAR_BIT_INT_MASK_FNRC BIT(6) 133 134 /* Misc. Config Register */ 135 #define MTK_STAR_REG_TEST1 0x005c 136 #define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31) 137 138 /* Extended Configuration Register */ 139 #define MTK_STAR_REG_EXT_CFG 0x0060 140 #define MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS 16 141 #define MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS GENMASK(26, 16) 142 #define MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K 0x400 143 144 /* EthSys Configuration Register */ 145 #define MTK_STAR_REG_SYS_CONF 0x0094 146 #define MTK_STAR_BIT_MII_PAD_OUT_ENABLE BIT(0) 147 #define MTK_STAR_BIT_EXT_MDC_MODE BIT(1) 148 #define MTK_STAR_BIT_SWC_MII_MODE BIT(2) 149 150 /* MAC Clock Configuration Register */ 151 #define MTK_STAR_REG_MAC_CLK_CONF 0x00ac 152 #define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0) 153 #define MTK_STAR_BIT_CLK_DIV_10 0x0a 154 155 /* Counter registers. */ 156 #define MTK_STAR_REG_C_RXOKPKT 0x0100 157 #define MTK_STAR_REG_C_RXOKBYTE 0x0104 158 #define MTK_STAR_REG_C_RXRUNT 0x0108 159 #define MTK_STAR_REG_C_RXLONG 0x010c 160 #define MTK_STAR_REG_C_RXDROP 0x0110 161 #define MTK_STAR_REG_C_RXCRC 0x0114 162 #define MTK_STAR_REG_C_RXARLDROP 0x0118 163 #define MTK_STAR_REG_C_RXVLANDROP 0x011c 164 #define MTK_STAR_REG_C_RXCSERR 0x0120 165 #define MTK_STAR_REG_C_RXPAUSE 0x0124 166 #define MTK_STAR_REG_C_TXOKPKT 0x0128 167 #define MTK_STAR_REG_C_TXOKBYTE 0x012c 168 #define MTK_STAR_REG_C_TXPAUSECOL 0x0130 169 #define MTK_STAR_REG_C_TXRTY 0x0134 170 #define MTK_STAR_REG_C_TXSKIP 0x0138 171 #define MTK_STAR_REG_C_TX_ARP 0x013c 172 #define MTK_STAR_REG_C_RX_RERR 0x01d8 173 #define MTK_STAR_REG_C_RX_UNI 0x01dc 174 #define MTK_STAR_REG_C_RX_MULTI 0x01e0 175 #define MTK_STAR_REG_C_RX_BROAD 0x01e4 176 #define MTK_STAR_REG_C_RX_ALIGNERR 0x01e8 177 #define MTK_STAR_REG_C_TX_UNI 0x01ec 178 #define MTK_STAR_REG_C_TX_MULTI 0x01f0 179 #define MTK_STAR_REG_C_TX_BROAD 0x01f4 180 #define MTK_STAR_REG_C_TX_TIMEOUT 0x01f8 181 #define MTK_STAR_REG_C_TX_LATECOL 0x01fc 182 #define MTK_STAR_REG_C_RX_LENGTHERR 0x0214 183 #define MTK_STAR_REG_C_RX_TWIST 0x0218 184 185 /* Ethernet CFG Control */ 186 #define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4 187 #define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0) 188 #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0) 189 190 /* Represents the actual structure of descriptors used by the MAC. We can 191 * reuse the same structure for both TX and RX - the layout is the same, only 192 * the flags differ slightly. 193 */ 194 struct mtk_star_ring_desc { 195 /* Contains both the status flags as well as packet length. */ 196 u32 status; 197 u32 data_ptr; 198 u32 vtag; 199 u32 reserved; 200 }; 201 202 #define MTK_STAR_DESC_MSK_LEN GENMASK(15, 0) 203 #define MTK_STAR_DESC_BIT_RX_CRCE BIT(24) 204 #define MTK_STAR_DESC_BIT_RX_OSIZE BIT(25) 205 #define MTK_STAR_DESC_BIT_INT BIT(27) 206 #define MTK_STAR_DESC_BIT_LS BIT(28) 207 #define MTK_STAR_DESC_BIT_FS BIT(29) 208 #define MTK_STAR_DESC_BIT_EOR BIT(30) 209 #define MTK_STAR_DESC_BIT_COWN BIT(31) 210 211 /* Helper structure for storing data read from/written to descriptors in order 212 * to limit reads from/writes to DMA memory. 213 */ 214 struct mtk_star_ring_desc_data { 215 unsigned int len; 216 unsigned int flags; 217 dma_addr_t dma_addr; 218 struct sk_buff *skb; 219 }; 220 221 #define MTK_STAR_RING_NUM_DESCS 128 222 #define MTK_STAR_NUM_TX_DESCS MTK_STAR_RING_NUM_DESCS 223 #define MTK_STAR_NUM_RX_DESCS MTK_STAR_RING_NUM_DESCS 224 #define MTK_STAR_NUM_DESCS_TOTAL (MTK_STAR_RING_NUM_DESCS * 2) 225 #define MTK_STAR_DMA_SIZE \ 226 (MTK_STAR_NUM_DESCS_TOTAL * sizeof(struct mtk_star_ring_desc)) 227 228 struct mtk_star_ring { 229 struct mtk_star_ring_desc *descs; 230 struct sk_buff *skbs[MTK_STAR_RING_NUM_DESCS]; 231 dma_addr_t dma_addrs[MTK_STAR_RING_NUM_DESCS]; 232 unsigned int head; 233 unsigned int tail; 234 }; 235 236 struct mtk_star_priv { 237 struct net_device *ndev; 238 239 struct regmap *regs; 240 struct regmap *pericfg; 241 242 struct clk_bulk_data clks[MTK_STAR_NCLKS]; 243 244 void *ring_base; 245 struct mtk_star_ring_desc *descs_base; 246 dma_addr_t dma_addr; 247 struct mtk_star_ring tx_ring; 248 struct mtk_star_ring rx_ring; 249 250 struct mii_bus *mii; 251 struct napi_struct napi; 252 253 struct device_node *phy_node; 254 phy_interface_t phy_intf; 255 struct phy_device *phydev; 256 unsigned int link; 257 int speed; 258 int duplex; 259 int pause; 260 261 /* Protects against concurrent descriptor access. */ 262 spinlock_t lock; 263 264 struct rtnl_link_stats64 stats; 265 struct work_struct stats_work; 266 }; 267 268 static struct device *mtk_star_get_dev(struct mtk_star_priv *priv) 269 { 270 return priv->ndev->dev.parent; 271 } 272 273 static const struct regmap_config mtk_star_regmap_config = { 274 .reg_bits = 32, 275 .val_bits = 32, 276 .reg_stride = 4, 277 .disable_locking = true, 278 }; 279 280 static void mtk_star_ring_init(struct mtk_star_ring *ring, 281 struct mtk_star_ring_desc *descs) 282 { 283 memset(ring, 0, sizeof(*ring)); 284 ring->descs = descs; 285 ring->head = 0; 286 ring->tail = 0; 287 } 288 289 static int mtk_star_ring_pop_tail(struct mtk_star_ring *ring, 290 struct mtk_star_ring_desc_data *desc_data) 291 { 292 struct mtk_star_ring_desc *desc = &ring->descs[ring->tail]; 293 unsigned int status; 294 295 status = READ_ONCE(desc->status); 296 dma_rmb(); /* Make sure we read the status bits before checking it. */ 297 298 if (!(status & MTK_STAR_DESC_BIT_COWN)) 299 return -1; 300 301 desc_data->len = status & MTK_STAR_DESC_MSK_LEN; 302 desc_data->flags = status & ~MTK_STAR_DESC_MSK_LEN; 303 desc_data->dma_addr = ring->dma_addrs[ring->tail]; 304 desc_data->skb = ring->skbs[ring->tail]; 305 306 ring->dma_addrs[ring->tail] = 0; 307 ring->skbs[ring->tail] = NULL; 308 309 status &= MTK_STAR_DESC_BIT_COWN | MTK_STAR_DESC_BIT_EOR; 310 311 WRITE_ONCE(desc->data_ptr, 0); 312 WRITE_ONCE(desc->status, status); 313 314 ring->tail = (ring->tail + 1) % MTK_STAR_RING_NUM_DESCS; 315 316 return 0; 317 } 318 319 static void mtk_star_ring_push_head(struct mtk_star_ring *ring, 320 struct mtk_star_ring_desc_data *desc_data, 321 unsigned int flags) 322 { 323 struct mtk_star_ring_desc *desc = &ring->descs[ring->head]; 324 unsigned int status; 325 326 status = READ_ONCE(desc->status); 327 328 ring->skbs[ring->head] = desc_data->skb; 329 ring->dma_addrs[ring->head] = desc_data->dma_addr; 330 331 status |= desc_data->len; 332 if (flags) 333 status |= flags; 334 335 WRITE_ONCE(desc->data_ptr, desc_data->dma_addr); 336 WRITE_ONCE(desc->status, status); 337 status &= ~MTK_STAR_DESC_BIT_COWN; 338 /* Flush previous modifications before ownership change. */ 339 dma_wmb(); 340 WRITE_ONCE(desc->status, status); 341 342 ring->head = (ring->head + 1) % MTK_STAR_RING_NUM_DESCS; 343 } 344 345 static void 346 mtk_star_ring_push_head_rx(struct mtk_star_ring *ring, 347 struct mtk_star_ring_desc_data *desc_data) 348 { 349 mtk_star_ring_push_head(ring, desc_data, 0); 350 } 351 352 static void 353 mtk_star_ring_push_head_tx(struct mtk_star_ring *ring, 354 struct mtk_star_ring_desc_data *desc_data) 355 { 356 static const unsigned int flags = MTK_STAR_DESC_BIT_FS | 357 MTK_STAR_DESC_BIT_LS | 358 MTK_STAR_DESC_BIT_INT; 359 360 mtk_star_ring_push_head(ring, desc_data, flags); 361 } 362 363 static unsigned int mtk_star_ring_num_used_descs(struct mtk_star_ring *ring) 364 { 365 return abs(ring->head - ring->tail); 366 } 367 368 static bool mtk_star_ring_full(struct mtk_star_ring *ring) 369 { 370 return mtk_star_ring_num_used_descs(ring) == MTK_STAR_RING_NUM_DESCS; 371 } 372 373 static bool mtk_star_ring_descs_available(struct mtk_star_ring *ring) 374 { 375 return mtk_star_ring_num_used_descs(ring) > 0; 376 } 377 378 static dma_addr_t mtk_star_dma_map_rx(struct mtk_star_priv *priv, 379 struct sk_buff *skb) 380 { 381 struct device *dev = mtk_star_get_dev(priv); 382 383 /* Data pointer for the RX DMA descriptor must be aligned to 4N + 2. */ 384 return dma_map_single(dev, skb_tail_pointer(skb) - 2, 385 skb_tailroom(skb), DMA_FROM_DEVICE); 386 } 387 388 static void mtk_star_dma_unmap_rx(struct mtk_star_priv *priv, 389 struct mtk_star_ring_desc_data *desc_data) 390 { 391 struct device *dev = mtk_star_get_dev(priv); 392 393 dma_unmap_single(dev, desc_data->dma_addr, 394 skb_tailroom(desc_data->skb), DMA_FROM_DEVICE); 395 } 396 397 static dma_addr_t mtk_star_dma_map_tx(struct mtk_star_priv *priv, 398 struct sk_buff *skb) 399 { 400 struct device *dev = mtk_star_get_dev(priv); 401 402 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 403 } 404 405 static void mtk_star_dma_unmap_tx(struct mtk_star_priv *priv, 406 struct mtk_star_ring_desc_data *desc_data) 407 { 408 struct device *dev = mtk_star_get_dev(priv); 409 410 return dma_unmap_single(dev, desc_data->dma_addr, 411 skb_headlen(desc_data->skb), DMA_TO_DEVICE); 412 } 413 414 static void mtk_star_nic_disable_pd(struct mtk_star_priv *priv) 415 { 416 regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG, 417 MTK_STAR_BIT_MAC_CFG_NIC_PD); 418 } 419 420 /* Unmask the three interrupts we care about, mask all others. */ 421 static void mtk_star_intr_enable(struct mtk_star_priv *priv) 422 { 423 unsigned int val = MTK_STAR_BIT_INT_STS_TNTC | 424 MTK_STAR_BIT_INT_STS_FNRC | 425 MTK_STAR_REG_INT_STS_MIB_CNT_TH; 426 427 regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~val); 428 } 429 430 static void mtk_star_intr_disable(struct mtk_star_priv *priv) 431 { 432 regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~0); 433 } 434 435 static void mtk_star_intr_enable_tx(struct mtk_star_priv *priv) 436 { 437 regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK, 438 MTK_STAR_BIT_INT_STS_TNTC); 439 } 440 441 static void mtk_star_intr_enable_rx(struct mtk_star_priv *priv) 442 { 443 regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK, 444 MTK_STAR_BIT_INT_STS_FNRC); 445 } 446 447 static void mtk_star_intr_enable_stats(struct mtk_star_priv *priv) 448 { 449 regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK, 450 MTK_STAR_REG_INT_STS_MIB_CNT_TH); 451 } 452 453 static void mtk_star_intr_disable_tx(struct mtk_star_priv *priv) 454 { 455 regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK, 456 MTK_STAR_BIT_INT_STS_TNTC); 457 } 458 459 static void mtk_star_intr_disable_rx(struct mtk_star_priv *priv) 460 { 461 regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK, 462 MTK_STAR_BIT_INT_STS_FNRC); 463 } 464 465 static void mtk_star_intr_disable_stats(struct mtk_star_priv *priv) 466 { 467 regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK, 468 MTK_STAR_REG_INT_STS_MIB_CNT_TH); 469 } 470 471 static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv) 472 { 473 unsigned int val; 474 475 regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); 476 477 return val; 478 } 479 480 static unsigned int mtk_star_intr_ack_all(struct mtk_star_priv *priv) 481 { 482 unsigned int val; 483 484 val = mtk_star_intr_read(priv); 485 regmap_write(priv->regs, MTK_STAR_REG_INT_STS, val); 486 487 return val; 488 } 489 490 static void mtk_star_dma_init(struct mtk_star_priv *priv) 491 { 492 struct mtk_star_ring_desc *desc; 493 unsigned int val; 494 int i; 495 496 priv->descs_base = (struct mtk_star_ring_desc *)priv->ring_base; 497 498 for (i = 0; i < MTK_STAR_NUM_DESCS_TOTAL; i++) { 499 desc = &priv->descs_base[i]; 500 501 memset(desc, 0, sizeof(*desc)); 502 desc->status = MTK_STAR_DESC_BIT_COWN; 503 if ((i == MTK_STAR_NUM_TX_DESCS - 1) || 504 (i == MTK_STAR_NUM_DESCS_TOTAL - 1)) 505 desc->status |= MTK_STAR_DESC_BIT_EOR; 506 } 507 508 mtk_star_ring_init(&priv->tx_ring, priv->descs_base); 509 mtk_star_ring_init(&priv->rx_ring, 510 priv->descs_base + MTK_STAR_NUM_TX_DESCS); 511 512 /* Set DMA pointers. */ 513 val = (unsigned int)priv->dma_addr; 514 regmap_write(priv->regs, MTK_STAR_REG_TX_BASE_ADDR, val); 515 regmap_write(priv->regs, MTK_STAR_REG_TX_DPTR, val); 516 517 val += sizeof(struct mtk_star_ring_desc) * MTK_STAR_NUM_TX_DESCS; 518 regmap_write(priv->regs, MTK_STAR_REG_RX_BASE_ADDR, val); 519 regmap_write(priv->regs, MTK_STAR_REG_RX_DPTR, val); 520 } 521 522 static void mtk_star_dma_start(struct mtk_star_priv *priv) 523 { 524 regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL, 525 MTK_STAR_BIT_TX_DMA_CTRL_START); 526 regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL, 527 MTK_STAR_BIT_RX_DMA_CTRL_START); 528 } 529 530 static void mtk_star_dma_stop(struct mtk_star_priv *priv) 531 { 532 regmap_write(priv->regs, MTK_STAR_REG_TX_DMA_CTRL, 533 MTK_STAR_BIT_TX_DMA_CTRL_STOP); 534 regmap_write(priv->regs, MTK_STAR_REG_RX_DMA_CTRL, 535 MTK_STAR_BIT_RX_DMA_CTRL_STOP); 536 } 537 538 static void mtk_star_dma_disable(struct mtk_star_priv *priv) 539 { 540 int i; 541 542 mtk_star_dma_stop(priv); 543 544 /* Take back all descriptors. */ 545 for (i = 0; i < MTK_STAR_NUM_DESCS_TOTAL; i++) 546 priv->descs_base[i].status |= MTK_STAR_DESC_BIT_COWN; 547 } 548 549 static void mtk_star_dma_resume_rx(struct mtk_star_priv *priv) 550 { 551 regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL, 552 MTK_STAR_BIT_RX_DMA_CTRL_RESUME); 553 } 554 555 static void mtk_star_dma_resume_tx(struct mtk_star_priv *priv) 556 { 557 regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL, 558 MTK_STAR_BIT_TX_DMA_CTRL_RESUME); 559 } 560 561 static void mtk_star_set_mac_addr(struct net_device *ndev) 562 { 563 struct mtk_star_priv *priv = netdev_priv(ndev); 564 u8 *mac_addr = ndev->dev_addr; 565 unsigned int high, low; 566 567 high = mac_addr[0] << 8 | mac_addr[1] << 0; 568 low = mac_addr[2] << 24 | mac_addr[3] << 16 | 569 mac_addr[4] << 8 | mac_addr[5]; 570 571 regmap_write(priv->regs, MTK_STAR_REG_MY_MAC_H, high); 572 regmap_write(priv->regs, MTK_STAR_REG_MY_MAC_L, low); 573 } 574 575 static void mtk_star_reset_counters(struct mtk_star_priv *priv) 576 { 577 static const unsigned int counter_regs[] = { 578 MTK_STAR_REG_C_RXOKPKT, 579 MTK_STAR_REG_C_RXOKBYTE, 580 MTK_STAR_REG_C_RXRUNT, 581 MTK_STAR_REG_C_RXLONG, 582 MTK_STAR_REG_C_RXDROP, 583 MTK_STAR_REG_C_RXCRC, 584 MTK_STAR_REG_C_RXARLDROP, 585 MTK_STAR_REG_C_RXVLANDROP, 586 MTK_STAR_REG_C_RXCSERR, 587 MTK_STAR_REG_C_RXPAUSE, 588 MTK_STAR_REG_C_TXOKPKT, 589 MTK_STAR_REG_C_TXOKBYTE, 590 MTK_STAR_REG_C_TXPAUSECOL, 591 MTK_STAR_REG_C_TXRTY, 592 MTK_STAR_REG_C_TXSKIP, 593 MTK_STAR_REG_C_TX_ARP, 594 MTK_STAR_REG_C_RX_RERR, 595 MTK_STAR_REG_C_RX_UNI, 596 MTK_STAR_REG_C_RX_MULTI, 597 MTK_STAR_REG_C_RX_BROAD, 598 MTK_STAR_REG_C_RX_ALIGNERR, 599 MTK_STAR_REG_C_TX_UNI, 600 MTK_STAR_REG_C_TX_MULTI, 601 MTK_STAR_REG_C_TX_BROAD, 602 MTK_STAR_REG_C_TX_TIMEOUT, 603 MTK_STAR_REG_C_TX_LATECOL, 604 MTK_STAR_REG_C_RX_LENGTHERR, 605 MTK_STAR_REG_C_RX_TWIST, 606 }; 607 608 unsigned int i, val; 609 610 for (i = 0; i < ARRAY_SIZE(counter_regs); i++) 611 regmap_read(priv->regs, counter_regs[i], &val); 612 } 613 614 static void mtk_star_update_stat(struct mtk_star_priv *priv, 615 unsigned int reg, u64 *stat) 616 { 617 unsigned int val; 618 619 regmap_read(priv->regs, reg, &val); 620 *stat += val; 621 } 622 623 /* Try to get as many stats as possible from the internal registers instead 624 * of tracking them ourselves. 625 */ 626 static void mtk_star_update_stats(struct mtk_star_priv *priv) 627 { 628 struct rtnl_link_stats64 *stats = &priv->stats; 629 630 /* OK packets and bytes. */ 631 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXOKPKT, &stats->rx_packets); 632 mtk_star_update_stat(priv, MTK_STAR_REG_C_TXOKPKT, &stats->tx_packets); 633 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXOKBYTE, &stats->rx_bytes); 634 mtk_star_update_stat(priv, MTK_STAR_REG_C_TXOKBYTE, &stats->tx_bytes); 635 636 /* RX & TX multicast. */ 637 mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_MULTI, &stats->multicast); 638 mtk_star_update_stat(priv, MTK_STAR_REG_C_TX_MULTI, &stats->multicast); 639 640 /* Collisions. */ 641 mtk_star_update_stat(priv, MTK_STAR_REG_C_TXPAUSECOL, 642 &stats->collisions); 643 mtk_star_update_stat(priv, MTK_STAR_REG_C_TX_LATECOL, 644 &stats->collisions); 645 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXRUNT, &stats->collisions); 646 647 /* RX Errors. */ 648 mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_LENGTHERR, 649 &stats->rx_length_errors); 650 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXLONG, 651 &stats->rx_over_errors); 652 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXCRC, &stats->rx_crc_errors); 653 mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_ALIGNERR, 654 &stats->rx_frame_errors); 655 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXDROP, 656 &stats->rx_fifo_errors); 657 /* Sum of the general RX error counter + all of the above. */ 658 mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_RERR, &stats->rx_errors); 659 stats->rx_errors += stats->rx_length_errors; 660 stats->rx_errors += stats->rx_over_errors; 661 stats->rx_errors += stats->rx_crc_errors; 662 stats->rx_errors += stats->rx_frame_errors; 663 stats->rx_errors += stats->rx_fifo_errors; 664 } 665 666 /* This runs in process context and parallel TX and RX paths executing in 667 * napi context may result in losing some stats data but this should happen 668 * seldom enough to be acceptable. 669 */ 670 static void mtk_star_update_stats_work(struct work_struct *work) 671 { 672 struct mtk_star_priv *priv = container_of(work, struct mtk_star_priv, 673 stats_work); 674 675 mtk_star_update_stats(priv); 676 mtk_star_reset_counters(priv); 677 mtk_star_intr_enable_stats(priv); 678 } 679 680 static struct sk_buff *mtk_star_alloc_skb(struct net_device *ndev) 681 { 682 uintptr_t tail, offset; 683 struct sk_buff *skb; 684 685 skb = dev_alloc_skb(MTK_STAR_MAX_FRAME_SIZE); 686 if (!skb) 687 return NULL; 688 689 /* Align to 16 bytes. */ 690 tail = (uintptr_t)skb_tail_pointer(skb); 691 if (tail & (MTK_STAR_SKB_ALIGNMENT - 1)) { 692 offset = tail & (MTK_STAR_SKB_ALIGNMENT - 1); 693 skb_reserve(skb, MTK_STAR_SKB_ALIGNMENT - offset); 694 } 695 696 /* Ensure 16-byte alignment of the skb pointer: eth_type_trans() will 697 * extract the Ethernet header (14 bytes) so we need two more bytes. 698 */ 699 skb_reserve(skb, MTK_STAR_IP_ALIGN); 700 701 return skb; 702 } 703 704 static int mtk_star_prepare_rx_skbs(struct net_device *ndev) 705 { 706 struct mtk_star_priv *priv = netdev_priv(ndev); 707 struct mtk_star_ring *ring = &priv->rx_ring; 708 struct device *dev = mtk_star_get_dev(priv); 709 struct mtk_star_ring_desc *desc; 710 struct sk_buff *skb; 711 dma_addr_t dma_addr; 712 int i; 713 714 for (i = 0; i < MTK_STAR_NUM_RX_DESCS; i++) { 715 skb = mtk_star_alloc_skb(ndev); 716 if (!skb) 717 return -ENOMEM; 718 719 dma_addr = mtk_star_dma_map_rx(priv, skb); 720 if (dma_mapping_error(dev, dma_addr)) { 721 dev_kfree_skb(skb); 722 return -ENOMEM; 723 } 724 725 desc = &ring->descs[i]; 726 desc->data_ptr = dma_addr; 727 desc->status |= skb_tailroom(skb) & MTK_STAR_DESC_MSK_LEN; 728 desc->status &= ~MTK_STAR_DESC_BIT_COWN; 729 ring->skbs[i] = skb; 730 ring->dma_addrs[i] = dma_addr; 731 } 732 733 return 0; 734 } 735 736 static void 737 mtk_star_ring_free_skbs(struct mtk_star_priv *priv, struct mtk_star_ring *ring, 738 void (*unmap_func)(struct mtk_star_priv *, 739 struct mtk_star_ring_desc_data *)) 740 { 741 struct mtk_star_ring_desc_data desc_data; 742 int i; 743 744 for (i = 0; i < MTK_STAR_RING_NUM_DESCS; i++) { 745 if (!ring->dma_addrs[i]) 746 continue; 747 748 desc_data.dma_addr = ring->dma_addrs[i]; 749 desc_data.skb = ring->skbs[i]; 750 751 unmap_func(priv, &desc_data); 752 dev_kfree_skb(desc_data.skb); 753 } 754 } 755 756 static void mtk_star_free_rx_skbs(struct mtk_star_priv *priv) 757 { 758 struct mtk_star_ring *ring = &priv->rx_ring; 759 760 mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_rx); 761 } 762 763 static void mtk_star_free_tx_skbs(struct mtk_star_priv *priv) 764 { 765 struct mtk_star_ring *ring = &priv->tx_ring; 766 767 mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_tx); 768 } 769 770 /* All processing for TX and RX happens in the napi poll callback. */ 771 static irqreturn_t mtk_star_handle_irq(int irq, void *data) 772 { 773 struct mtk_star_priv *priv; 774 struct net_device *ndev; 775 bool need_napi = false; 776 unsigned int status; 777 778 ndev = data; 779 priv = netdev_priv(ndev); 780 781 if (netif_running(ndev)) { 782 status = mtk_star_intr_read(priv); 783 784 if (status & MTK_STAR_BIT_INT_STS_TNTC) { 785 mtk_star_intr_disable_tx(priv); 786 need_napi = true; 787 } 788 789 if (status & MTK_STAR_BIT_INT_STS_FNRC) { 790 mtk_star_intr_disable_rx(priv); 791 need_napi = true; 792 } 793 794 if (need_napi) 795 napi_schedule(&priv->napi); 796 797 /* One of the counters reached 0x8000000 - update stats and 798 * reset all counters. 799 */ 800 if (unlikely(status & MTK_STAR_REG_INT_STS_MIB_CNT_TH)) { 801 mtk_star_intr_disable_stats(priv); 802 schedule_work(&priv->stats_work); 803 } 804 805 mtk_star_intr_ack_all(priv); 806 } 807 808 return IRQ_HANDLED; 809 } 810 811 /* Wait for the completion of any previous command - CMD_START bit must be 812 * cleared by hardware. 813 */ 814 static int mtk_star_hash_wait_cmd_start(struct mtk_star_priv *priv) 815 { 816 unsigned int val; 817 818 return regmap_read_poll_timeout_atomic(priv->regs, 819 MTK_STAR_REG_HASH_CTRL, val, 820 !(val & MTK_STAR_BIT_HASH_CTRL_CMD_START), 821 10, MTK_STAR_WAIT_TIMEOUT); 822 } 823 824 static int mtk_star_hash_wait_ok(struct mtk_star_priv *priv) 825 { 826 unsigned int val; 827 int ret; 828 829 /* Wait for BIST_DONE bit. */ 830 ret = regmap_read_poll_timeout_atomic(priv->regs, 831 MTK_STAR_REG_HASH_CTRL, val, 832 val & MTK_STAR_BIT_HASH_CTRL_BIST_DONE, 833 10, MTK_STAR_WAIT_TIMEOUT); 834 if (ret) 835 return ret; 836 837 /* Check the BIST_OK bit. */ 838 if (!regmap_test_bits(priv->regs, MTK_STAR_REG_HASH_CTRL, 839 MTK_STAR_BIT_HASH_CTRL_BIST_OK)) 840 return -EIO; 841 842 return 0; 843 } 844 845 static int mtk_star_set_hashbit(struct mtk_star_priv *priv, 846 unsigned int hash_addr) 847 { 848 unsigned int val; 849 int ret; 850 851 ret = mtk_star_hash_wait_cmd_start(priv); 852 if (ret) 853 return ret; 854 855 val = hash_addr & MTK_STAR_MSK_HASH_CTRL_HASH_BIT_ADDR; 856 val |= MTK_STAR_BIT_HASH_CTRL_ACC_CMD; 857 val |= MTK_STAR_BIT_HASH_CTRL_CMD_START; 858 val |= MTK_STAR_BIT_HASH_CTRL_BIST_EN; 859 val |= MTK_STAR_BIT_HASH_CTRL_HASH_BIT_DATA; 860 regmap_write(priv->regs, MTK_STAR_REG_HASH_CTRL, val); 861 862 return mtk_star_hash_wait_ok(priv); 863 } 864 865 static int mtk_star_reset_hash_table(struct mtk_star_priv *priv) 866 { 867 int ret; 868 869 ret = mtk_star_hash_wait_cmd_start(priv); 870 if (ret) 871 return ret; 872 873 regmap_set_bits(priv->regs, MTK_STAR_REG_HASH_CTRL, 874 MTK_STAR_BIT_HASH_CTRL_BIST_EN); 875 regmap_set_bits(priv->regs, MTK_STAR_REG_TEST1, 876 MTK_STAR_BIT_TEST1_RST_HASH_MBIST); 877 878 return mtk_star_hash_wait_ok(priv); 879 } 880 881 static void mtk_star_phy_config(struct mtk_star_priv *priv) 882 { 883 unsigned int val; 884 885 if (priv->speed == SPEED_1000) 886 val = MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_1000M; 887 else if (priv->speed == SPEED_100) 888 val = MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_100M; 889 else 890 val = MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_10M; 891 val <<= MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD; 892 893 val |= MTK_STAR_BIT_PHY_CTRL1_AN_EN; 894 val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; 895 val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; 896 /* Only full-duplex supported for now. */ 897 val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; 898 899 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); 900 901 if (priv->pause) { 902 val = MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; 903 val <<= MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; 904 val |= MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; 905 } else { 906 val = 0; 907 } 908 909 regmap_update_bits(priv->regs, MTK_STAR_REG_FC_CFG, 910 MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH | 911 MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR, val); 912 913 if (priv->pause) { 914 val = MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; 915 val <<= MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; 916 } else { 917 val = 0; 918 } 919 920 regmap_update_bits(priv->regs, MTK_STAR_REG_EXT_CFG, 921 MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS, val); 922 } 923 924 static void mtk_star_adjust_link(struct net_device *ndev) 925 { 926 struct mtk_star_priv *priv = netdev_priv(ndev); 927 struct phy_device *phydev = priv->phydev; 928 bool new_state = false; 929 930 if (phydev->link) { 931 if (!priv->link) { 932 priv->link = phydev->link; 933 new_state = true; 934 } 935 936 if (priv->speed != phydev->speed) { 937 priv->speed = phydev->speed; 938 new_state = true; 939 } 940 941 if (priv->pause != phydev->pause) { 942 priv->pause = phydev->pause; 943 new_state = true; 944 } 945 } else { 946 if (priv->link) { 947 priv->link = phydev->link; 948 new_state = true; 949 } 950 } 951 952 if (new_state) { 953 if (phydev->link) 954 mtk_star_phy_config(priv); 955 956 phy_print_status(ndev->phydev); 957 } 958 } 959 960 static void mtk_star_init_config(struct mtk_star_priv *priv) 961 { 962 unsigned int val; 963 964 val = (MTK_STAR_BIT_MII_PAD_OUT_ENABLE | 965 MTK_STAR_BIT_EXT_MDC_MODE | 966 MTK_STAR_BIT_SWC_MII_MODE); 967 968 regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val); 969 regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF, 970 MTK_STAR_MSK_MAC_CLK_CONF, 971 MTK_STAR_BIT_CLK_DIV_10); 972 } 973 974 static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) 975 { 976 regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON, 977 MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII, 978 MTK_PERICFG_BIT_NIC_CFG_CON_RMII); 979 } 980 981 static int mtk_star_enable(struct net_device *ndev) 982 { 983 struct mtk_star_priv *priv = netdev_priv(ndev); 984 unsigned int val; 985 int ret; 986 987 mtk_star_nic_disable_pd(priv); 988 mtk_star_intr_disable(priv); 989 mtk_star_dma_stop(priv); 990 991 mtk_star_set_mac_addr(ndev); 992 993 /* Configure the MAC */ 994 val = MTK_STAR_VAL_MAC_CFG_IPG_96BIT; 995 val <<= MTK_STAR_OFF_MAC_CFG_IPG; 996 val |= MTK_STAR_BIT_MAC_CFG_MAXLEN_1522; 997 val |= MTK_STAR_BIT_MAC_CFG_AUTO_PAD; 998 val |= MTK_STAR_BIT_MAC_CFG_CRC_STRIP; 999 regmap_write(priv->regs, MTK_STAR_REG_MAC_CFG, val); 1000 1001 /* Enable Hash Table BIST and reset it */ 1002 ret = mtk_star_reset_hash_table(priv); 1003 if (ret) 1004 return ret; 1005 1006 /* Setup the hashing algorithm */ 1007 regmap_clear_bits(priv->regs, MTK_STAR_REG_ARL_CFG, 1008 MTK_STAR_BIT_ARL_CFG_HASH_ALG | 1009 MTK_STAR_BIT_ARL_CFG_MISC_MODE); 1010 1011 /* Don't strip VLAN tags */ 1012 regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG, 1013 MTK_STAR_BIT_MAC_CFG_VLAN_STRIP); 1014 1015 /* Setup DMA */ 1016 mtk_star_dma_init(priv); 1017 1018 ret = mtk_star_prepare_rx_skbs(ndev); 1019 if (ret) 1020 goto err_out; 1021 1022 /* Request the interrupt */ 1023 ret = request_irq(ndev->irq, mtk_star_handle_irq, 1024 IRQF_TRIGGER_FALLING, ndev->name, ndev); 1025 if (ret) 1026 goto err_free_skbs; 1027 1028 napi_enable(&priv->napi); 1029 1030 mtk_star_intr_ack_all(priv); 1031 mtk_star_intr_enable(priv); 1032 1033 /* Connect to and start PHY */ 1034 priv->phydev = of_phy_connect(ndev, priv->phy_node, 1035 mtk_star_adjust_link, 0, priv->phy_intf); 1036 if (!priv->phydev) { 1037 netdev_err(ndev, "failed to connect to PHY\n"); 1038 goto err_free_irq; 1039 } 1040 1041 mtk_star_dma_start(priv); 1042 phy_start(priv->phydev); 1043 netif_start_queue(ndev); 1044 1045 return 0; 1046 1047 err_free_irq: 1048 free_irq(ndev->irq, ndev); 1049 err_free_skbs: 1050 mtk_star_free_rx_skbs(priv); 1051 err_out: 1052 return ret; 1053 } 1054 1055 static void mtk_star_disable(struct net_device *ndev) 1056 { 1057 struct mtk_star_priv *priv = netdev_priv(ndev); 1058 1059 netif_stop_queue(ndev); 1060 napi_disable(&priv->napi); 1061 mtk_star_intr_disable(priv); 1062 mtk_star_dma_disable(priv); 1063 mtk_star_intr_ack_all(priv); 1064 phy_stop(priv->phydev); 1065 phy_disconnect(priv->phydev); 1066 free_irq(ndev->irq, ndev); 1067 mtk_star_free_rx_skbs(priv); 1068 mtk_star_free_tx_skbs(priv); 1069 } 1070 1071 static int mtk_star_netdev_open(struct net_device *ndev) 1072 { 1073 return mtk_star_enable(ndev); 1074 } 1075 1076 static int mtk_star_netdev_stop(struct net_device *ndev) 1077 { 1078 mtk_star_disable(ndev); 1079 1080 return 0; 1081 } 1082 1083 static int mtk_star_netdev_ioctl(struct net_device *ndev, 1084 struct ifreq *req, int cmd) 1085 { 1086 if (!netif_running(ndev)) 1087 return -EINVAL; 1088 1089 return phy_mii_ioctl(ndev->phydev, req, cmd); 1090 } 1091 1092 static int mtk_star_netdev_start_xmit(struct sk_buff *skb, 1093 struct net_device *ndev) 1094 { 1095 struct mtk_star_priv *priv = netdev_priv(ndev); 1096 struct mtk_star_ring *ring = &priv->tx_ring; 1097 struct device *dev = mtk_star_get_dev(priv); 1098 struct mtk_star_ring_desc_data desc_data; 1099 1100 desc_data.dma_addr = mtk_star_dma_map_tx(priv, skb); 1101 if (dma_mapping_error(dev, desc_data.dma_addr)) 1102 goto err_drop_packet; 1103 1104 desc_data.skb = skb; 1105 desc_data.len = skb->len; 1106 1107 spin_lock_bh(&priv->lock); 1108 1109 mtk_star_ring_push_head_tx(ring, &desc_data); 1110 1111 netdev_sent_queue(ndev, skb->len); 1112 1113 if (mtk_star_ring_full(ring)) 1114 netif_stop_queue(ndev); 1115 1116 spin_unlock_bh(&priv->lock); 1117 1118 mtk_star_dma_resume_tx(priv); 1119 1120 return NETDEV_TX_OK; 1121 1122 err_drop_packet: 1123 dev_kfree_skb(skb); 1124 ndev->stats.tx_dropped++; 1125 return NETDEV_TX_BUSY; 1126 } 1127 1128 /* Returns the number of bytes sent or a negative number on the first 1129 * descriptor owned by DMA. 1130 */ 1131 static int mtk_star_tx_complete_one(struct mtk_star_priv *priv) 1132 { 1133 struct mtk_star_ring *ring = &priv->tx_ring; 1134 struct mtk_star_ring_desc_data desc_data; 1135 int ret; 1136 1137 ret = mtk_star_ring_pop_tail(ring, &desc_data); 1138 if (ret) 1139 return ret; 1140 1141 mtk_star_dma_unmap_tx(priv, &desc_data); 1142 ret = desc_data.skb->len; 1143 dev_kfree_skb_irq(desc_data.skb); 1144 1145 return ret; 1146 } 1147 1148 static void mtk_star_tx_complete_all(struct mtk_star_priv *priv) 1149 { 1150 struct mtk_star_ring *ring = &priv->tx_ring; 1151 struct net_device *ndev = priv->ndev; 1152 int ret, pkts_compl, bytes_compl; 1153 bool wake = false; 1154 1155 spin_lock(&priv->lock); 1156 1157 for (pkts_compl = 0, bytes_compl = 0;; 1158 pkts_compl++, bytes_compl += ret, wake = true) { 1159 if (!mtk_star_ring_descs_available(ring)) 1160 break; 1161 1162 ret = mtk_star_tx_complete_one(priv); 1163 if (ret < 0) 1164 break; 1165 } 1166 1167 netdev_completed_queue(ndev, pkts_compl, bytes_compl); 1168 1169 if (wake && netif_queue_stopped(ndev)) 1170 netif_wake_queue(ndev); 1171 1172 mtk_star_intr_enable_tx(priv); 1173 1174 spin_unlock(&priv->lock); 1175 } 1176 1177 static void mtk_star_netdev_get_stats64(struct net_device *ndev, 1178 struct rtnl_link_stats64 *stats) 1179 { 1180 struct mtk_star_priv *priv = netdev_priv(ndev); 1181 1182 mtk_star_update_stats(priv); 1183 1184 memcpy(stats, &priv->stats, sizeof(*stats)); 1185 } 1186 1187 static void mtk_star_set_rx_mode(struct net_device *ndev) 1188 { 1189 struct mtk_star_priv *priv = netdev_priv(ndev); 1190 struct netdev_hw_addr *hw_addr; 1191 unsigned int hash_addr, i; 1192 int ret; 1193 1194 if (ndev->flags & IFF_PROMISC) { 1195 regmap_set_bits(priv->regs, MTK_STAR_REG_ARL_CFG, 1196 MTK_STAR_BIT_ARL_CFG_MISC_MODE); 1197 } else if (netdev_mc_count(ndev) > MTK_STAR_HASHTABLE_MC_LIMIT || 1198 ndev->flags & IFF_ALLMULTI) { 1199 for (i = 0; i < MTK_STAR_HASHTABLE_SIZE_MAX; i++) { 1200 ret = mtk_star_set_hashbit(priv, i); 1201 if (ret) 1202 goto hash_fail; 1203 } 1204 } else { 1205 /* Clear previous settings. */ 1206 ret = mtk_star_reset_hash_table(priv); 1207 if (ret) 1208 goto hash_fail; 1209 1210 netdev_for_each_mc_addr(hw_addr, ndev) { 1211 hash_addr = (hw_addr->addr[0] & 0x01) << 8; 1212 hash_addr += hw_addr->addr[5]; 1213 ret = mtk_star_set_hashbit(priv, hash_addr); 1214 if (ret) 1215 goto hash_fail; 1216 } 1217 } 1218 1219 return; 1220 1221 hash_fail: 1222 if (ret == -ETIMEDOUT) 1223 netdev_err(ndev, "setting hash bit timed out\n"); 1224 else 1225 /* Should be -EIO */ 1226 netdev_err(ndev, "unable to set hash bit"); 1227 } 1228 1229 static const struct net_device_ops mtk_star_netdev_ops = { 1230 .ndo_open = mtk_star_netdev_open, 1231 .ndo_stop = mtk_star_netdev_stop, 1232 .ndo_start_xmit = mtk_star_netdev_start_xmit, 1233 .ndo_get_stats64 = mtk_star_netdev_get_stats64, 1234 .ndo_set_rx_mode = mtk_star_set_rx_mode, 1235 .ndo_do_ioctl = mtk_star_netdev_ioctl, 1236 .ndo_set_mac_address = eth_mac_addr, 1237 .ndo_validate_addr = eth_validate_addr, 1238 }; 1239 1240 static void mtk_star_get_drvinfo(struct net_device *dev, 1241 struct ethtool_drvinfo *info) 1242 { 1243 strlcpy(info->driver, MTK_STAR_DRVNAME, sizeof(info->driver)); 1244 } 1245 1246 /* TODO Add ethtool stats. */ 1247 static const struct ethtool_ops mtk_star_ethtool_ops = { 1248 .get_drvinfo = mtk_star_get_drvinfo, 1249 .get_link = ethtool_op_get_link, 1250 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1251 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1252 }; 1253 1254 static int mtk_star_receive_packet(struct mtk_star_priv *priv) 1255 { 1256 struct mtk_star_ring *ring = &priv->rx_ring; 1257 struct device *dev = mtk_star_get_dev(priv); 1258 struct mtk_star_ring_desc_data desc_data; 1259 struct net_device *ndev = priv->ndev; 1260 struct sk_buff *curr_skb, *new_skb; 1261 dma_addr_t new_dma_addr; 1262 int ret; 1263 1264 spin_lock(&priv->lock); 1265 ret = mtk_star_ring_pop_tail(ring, &desc_data); 1266 spin_unlock(&priv->lock); 1267 if (ret) 1268 return -1; 1269 1270 curr_skb = desc_data.skb; 1271 1272 if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || 1273 (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { 1274 /* Error packet -> drop and reuse skb. */ 1275 new_skb = curr_skb; 1276 goto push_new_skb; 1277 } 1278 1279 /* Prepare new skb before receiving the current one. Reuse the current 1280 * skb if we fail at any point. 1281 */ 1282 new_skb = mtk_star_alloc_skb(ndev); 1283 if (!new_skb) { 1284 ndev->stats.rx_dropped++; 1285 new_skb = curr_skb; 1286 goto push_new_skb; 1287 } 1288 1289 new_dma_addr = mtk_star_dma_map_rx(priv, new_skb); 1290 if (dma_mapping_error(dev, new_dma_addr)) { 1291 ndev->stats.rx_dropped++; 1292 dev_kfree_skb(new_skb); 1293 new_skb = curr_skb; 1294 netdev_err(ndev, "DMA mapping error of RX descriptor\n"); 1295 goto push_new_skb; 1296 } 1297 1298 desc_data.dma_addr = new_dma_addr; 1299 1300 /* We can't fail anymore at this point: it's safe to unmap the skb. */ 1301 mtk_star_dma_unmap_rx(priv, &desc_data); 1302 1303 skb_put(desc_data.skb, desc_data.len); 1304 desc_data.skb->ip_summed = CHECKSUM_NONE; 1305 desc_data.skb->protocol = eth_type_trans(desc_data.skb, ndev); 1306 desc_data.skb->dev = ndev; 1307 netif_receive_skb(desc_data.skb); 1308 1309 push_new_skb: 1310 desc_data.len = skb_tailroom(new_skb); 1311 desc_data.skb = new_skb; 1312 1313 spin_lock(&priv->lock); 1314 mtk_star_ring_push_head_rx(ring, &desc_data); 1315 spin_unlock(&priv->lock); 1316 1317 return 0; 1318 } 1319 1320 static int mtk_star_process_rx(struct mtk_star_priv *priv, int budget) 1321 { 1322 int received, ret; 1323 1324 for (received = 0, ret = 0; received < budget && ret == 0; received++) 1325 ret = mtk_star_receive_packet(priv); 1326 1327 mtk_star_dma_resume_rx(priv); 1328 1329 return received; 1330 } 1331 1332 static int mtk_star_poll(struct napi_struct *napi, int budget) 1333 { 1334 struct mtk_star_priv *priv; 1335 int received = 0; 1336 1337 priv = container_of(napi, struct mtk_star_priv, napi); 1338 1339 /* Clean-up all TX descriptors. */ 1340 mtk_star_tx_complete_all(priv); 1341 /* Receive up to $budget packets. */ 1342 received = mtk_star_process_rx(priv, budget); 1343 1344 if (received < budget) { 1345 napi_complete_done(napi, received); 1346 mtk_star_intr_enable_rx(priv); 1347 } 1348 1349 return received; 1350 } 1351 1352 static void mtk_star_mdio_rwok_clear(struct mtk_star_priv *priv) 1353 { 1354 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, 1355 MTK_STAR_BIT_PHY_CTRL0_RWOK); 1356 } 1357 1358 static int mtk_star_mdio_rwok_wait(struct mtk_star_priv *priv) 1359 { 1360 unsigned int val; 1361 1362 return regmap_read_poll_timeout(priv->regs, MTK_STAR_REG_PHY_CTRL0, 1363 val, val & MTK_STAR_BIT_PHY_CTRL0_RWOK, 1364 10, MTK_STAR_WAIT_TIMEOUT); 1365 } 1366 1367 static int mtk_star_mdio_read(struct mii_bus *mii, int phy_id, int regnum) 1368 { 1369 struct mtk_star_priv *priv = mii->priv; 1370 unsigned int val, data; 1371 int ret; 1372 1373 if (regnum & MII_ADDR_C45) 1374 return -EOPNOTSUPP; 1375 1376 mtk_star_mdio_rwok_clear(priv); 1377 1378 val = (regnum << MTK_STAR_OFF_PHY_CTRL0_PREG); 1379 val &= MTK_STAR_MSK_PHY_CTRL0_PREG; 1380 val |= MTK_STAR_BIT_PHY_CTRL0_RDCMD; 1381 1382 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, val); 1383 1384 ret = mtk_star_mdio_rwok_wait(priv); 1385 if (ret) 1386 return ret; 1387 1388 regmap_read(priv->regs, MTK_STAR_REG_PHY_CTRL0, &data); 1389 1390 data &= MTK_STAR_MSK_PHY_CTRL0_RWDATA; 1391 data >>= MTK_STAR_OFF_PHY_CTRL0_RWDATA; 1392 1393 return data; 1394 } 1395 1396 static int mtk_star_mdio_write(struct mii_bus *mii, int phy_id, 1397 int regnum, u16 data) 1398 { 1399 struct mtk_star_priv *priv = mii->priv; 1400 unsigned int val; 1401 1402 if (regnum & MII_ADDR_C45) 1403 return -EOPNOTSUPP; 1404 1405 mtk_star_mdio_rwok_clear(priv); 1406 1407 val = data; 1408 val <<= MTK_STAR_OFF_PHY_CTRL0_RWDATA; 1409 val &= MTK_STAR_MSK_PHY_CTRL0_RWDATA; 1410 regnum <<= MTK_STAR_OFF_PHY_CTRL0_PREG; 1411 regnum &= MTK_STAR_MSK_PHY_CTRL0_PREG; 1412 val |= regnum; 1413 val |= MTK_STAR_BIT_PHY_CTRL0_WTCMD; 1414 1415 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, val); 1416 1417 return mtk_star_mdio_rwok_wait(priv); 1418 } 1419 1420 static int mtk_star_mdio_init(struct net_device *ndev) 1421 { 1422 struct mtk_star_priv *priv = netdev_priv(ndev); 1423 struct device *dev = mtk_star_get_dev(priv); 1424 struct device_node *of_node, *mdio_node; 1425 int ret; 1426 1427 of_node = dev->of_node; 1428 1429 mdio_node = of_get_child_by_name(of_node, "mdio"); 1430 if (!mdio_node) 1431 return -ENODEV; 1432 1433 if (!of_device_is_available(mdio_node)) { 1434 ret = -ENODEV; 1435 goto out_put_node; 1436 } 1437 1438 priv->mii = devm_mdiobus_alloc(dev); 1439 if (!priv->mii) { 1440 ret = -ENOMEM; 1441 goto out_put_node; 1442 } 1443 1444 snprintf(priv->mii->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 1445 priv->mii->name = "mtk-mac-mdio"; 1446 priv->mii->parent = dev; 1447 priv->mii->read = mtk_star_mdio_read; 1448 priv->mii->write = mtk_star_mdio_write; 1449 priv->mii->priv = priv; 1450 1451 ret = of_mdiobus_register(priv->mii, mdio_node); 1452 1453 out_put_node: 1454 of_node_put(mdio_node); 1455 return ret; 1456 } 1457 1458 static __maybe_unused int mtk_star_suspend(struct device *dev) 1459 { 1460 struct mtk_star_priv *priv; 1461 struct net_device *ndev; 1462 1463 ndev = dev_get_drvdata(dev); 1464 priv = netdev_priv(ndev); 1465 1466 if (netif_running(ndev)) 1467 mtk_star_disable(ndev); 1468 1469 clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); 1470 1471 return 0; 1472 } 1473 1474 static __maybe_unused int mtk_star_resume(struct device *dev) 1475 { 1476 struct mtk_star_priv *priv; 1477 struct net_device *ndev; 1478 int ret; 1479 1480 ndev = dev_get_drvdata(dev); 1481 priv = netdev_priv(ndev); 1482 1483 ret = clk_bulk_prepare_enable(MTK_STAR_NCLKS, priv->clks); 1484 if (ret) 1485 return ret; 1486 1487 if (netif_running(ndev)) { 1488 ret = mtk_star_enable(ndev); 1489 if (ret) 1490 clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); 1491 } 1492 1493 return ret; 1494 } 1495 1496 static void mtk_star_clk_disable_unprepare(void *data) 1497 { 1498 struct mtk_star_priv *priv = data; 1499 1500 clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); 1501 } 1502 1503 static void mtk_star_mdiobus_unregister(void *data) 1504 { 1505 struct mtk_star_priv *priv = data; 1506 1507 mdiobus_unregister(priv->mii); 1508 } 1509 1510 static int mtk_star_probe(struct platform_device *pdev) 1511 { 1512 struct device_node *of_node; 1513 struct mtk_star_priv *priv; 1514 struct net_device *ndev; 1515 struct device *dev; 1516 void __iomem *base; 1517 int ret, i; 1518 1519 dev = &pdev->dev; 1520 of_node = dev->of_node; 1521 1522 ndev = devm_alloc_etherdev(dev, sizeof(*priv)); 1523 if (!ndev) 1524 return -ENOMEM; 1525 1526 priv = netdev_priv(ndev); 1527 priv->ndev = ndev; 1528 SET_NETDEV_DEV(ndev, dev); 1529 platform_set_drvdata(pdev, ndev); 1530 1531 ndev->min_mtu = ETH_ZLEN; 1532 ndev->max_mtu = MTK_STAR_MAX_FRAME_SIZE; 1533 1534 spin_lock_init(&priv->lock); 1535 INIT_WORK(&priv->stats_work, mtk_star_update_stats_work); 1536 1537 base = devm_platform_ioremap_resource(pdev, 0); 1538 if (IS_ERR(base)) 1539 return PTR_ERR(base); 1540 1541 /* We won't be checking the return values of regmap read & write 1542 * functions. They can only fail for mmio if there's a clock attached 1543 * to regmap which is not the case here. 1544 */ 1545 priv->regs = devm_regmap_init_mmio(dev, base, 1546 &mtk_star_regmap_config); 1547 if (IS_ERR(priv->regs)) 1548 return PTR_ERR(priv->regs); 1549 1550 priv->pericfg = syscon_regmap_lookup_by_phandle(of_node, 1551 "mediatek,pericfg"); 1552 if (IS_ERR(priv->pericfg)) { 1553 dev_err(dev, "Failed to lookup the PERICFG syscon\n"); 1554 return PTR_ERR(priv->pericfg); 1555 } 1556 1557 ndev->irq = platform_get_irq(pdev, 0); 1558 if (ndev->irq < 0) 1559 return ndev->irq; 1560 1561 for (i = 0; i < MTK_STAR_NCLKS; i++) 1562 priv->clks[i].id = mtk_star_clk_names[i]; 1563 ret = devm_clk_bulk_get(dev, MTK_STAR_NCLKS, priv->clks); 1564 if (ret) 1565 return ret; 1566 1567 ret = clk_bulk_prepare_enable(MTK_STAR_NCLKS, priv->clks); 1568 if (ret) 1569 return ret; 1570 1571 ret = devm_add_action_or_reset(dev, 1572 mtk_star_clk_disable_unprepare, priv); 1573 if (ret) 1574 return ret; 1575 1576 ret = of_get_phy_mode(of_node, &priv->phy_intf); 1577 if (ret) { 1578 return ret; 1579 } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII) { 1580 dev_err(dev, "unsupported phy mode: %s\n", 1581 phy_modes(priv->phy_intf)); 1582 return -EINVAL; 1583 } 1584 1585 priv->phy_node = of_parse_phandle(of_node, "phy-handle", 0); 1586 if (!priv->phy_node) { 1587 dev_err(dev, "failed to retrieve the phy handle from device tree\n"); 1588 return -ENODEV; 1589 } 1590 1591 mtk_star_set_mode_rmii(priv); 1592 1593 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1594 if (ret) { 1595 dev_err(dev, "unsupported DMA mask\n"); 1596 return ret; 1597 } 1598 1599 priv->ring_base = dmam_alloc_coherent(dev, MTK_STAR_DMA_SIZE, 1600 &priv->dma_addr, 1601 GFP_KERNEL | GFP_DMA); 1602 if (!priv->ring_base) 1603 return -ENOMEM; 1604 1605 mtk_star_nic_disable_pd(priv); 1606 mtk_star_init_config(priv); 1607 1608 ret = mtk_star_mdio_init(ndev); 1609 if (ret) 1610 return ret; 1611 1612 ret = devm_add_action_or_reset(dev, mtk_star_mdiobus_unregister, priv); 1613 if (ret) 1614 return ret; 1615 1616 ret = eth_platform_get_mac_address(dev, ndev->dev_addr); 1617 if (ret || !is_valid_ether_addr(ndev->dev_addr)) 1618 eth_hw_addr_random(ndev); 1619 1620 ndev->netdev_ops = &mtk_star_netdev_ops; 1621 ndev->ethtool_ops = &mtk_star_ethtool_ops; 1622 1623 netif_napi_add(ndev, &priv->napi, mtk_star_poll, MTK_STAR_NAPI_WEIGHT); 1624 1625 return devm_register_netdev(dev, ndev); 1626 } 1627 1628 static const struct of_device_id mtk_star_of_match[] = { 1629 { .compatible = "mediatek,mt8516-eth", }, 1630 { .compatible = "mediatek,mt8518-eth", }, 1631 { .compatible = "mediatek,mt8175-eth", }, 1632 { } 1633 }; 1634 MODULE_DEVICE_TABLE(of, mtk_star_of_match); 1635 1636 static SIMPLE_DEV_PM_OPS(mtk_star_pm_ops, 1637 mtk_star_suspend, mtk_star_resume); 1638 1639 static struct platform_driver mtk_star_driver = { 1640 .driver = { 1641 .name = MTK_STAR_DRVNAME, 1642 .pm = &mtk_star_pm_ops, 1643 .of_match_table = of_match_ptr(mtk_star_of_match), 1644 }, 1645 .probe = mtk_star_probe, 1646 }; 1647 module_platform_driver(mtk_star_driver); 1648 1649 MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>"); 1650 MODULE_DESCRIPTION("Mediatek STAR Ethernet MAC Driver"); 1651 MODULE_LICENSE("GPL"); 1652