1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Copyright (c) 2019 BayLibre, SAS. 5 * Author: Fabien Parent <fparent@baylibre.com> 6 */ 7 8#include <dt-bindings/clock/mt8516-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13#include "mt8516-pinfunc.h" 14 15/ { 16 compatible = "mediatek,mt8516"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cluster0_opp: opp-table-0 { 22 compatible = "operating-points-v2"; 23 opp-shared; 24 opp-598000000 { 25 opp-hz = /bits/ 64 <598000000>; 26 opp-microvolt = <1150000>; 27 }; 28 opp-747500000 { 29 opp-hz = /bits/ 64 <747500000>; 30 opp-microvolt = <1150000>; 31 }; 32 opp-1040000000 { 33 opp-hz = /bits/ 64 <1040000000>; 34 opp-microvolt = <1200000>; 35 }; 36 opp-1196000000 { 37 opp-hz = /bits/ 64 <1196000000>; 38 opp-microvolt = <1250000>; 39 }; 40 opp-1300000000 { 41 opp-hz = /bits/ 64 <1300000000>; 42 opp-microvolt = <1300000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a35"; 53 reg = <0x0>; 54 enable-method = "psci"; 55 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 56 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 58 <&topckgen CLK_TOP_MAINPLL_D2>; 59 clock-names = "cpu", "intermediate"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cpu1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a35"; 66 reg = <0x1>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 69 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 70 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 71 <&topckgen CLK_TOP_MAINPLL_D2>; 72 clock-names = "cpu", "intermediate"; 73 operating-points-v2 = <&cluster0_opp>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a35"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 82 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 83 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 84 <&topckgen CLK_TOP_MAINPLL_D2>; 85 clock-names = "cpu", "intermediate"; 86 operating-points-v2 = <&cluster0_opp>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a35"; 92 reg = <0x3>; 93 enable-method = "psci"; 94 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 95 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 96 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 97 <&topckgen CLK_TOP_MAINPLL_D2>; 98 clock-names = "cpu", "intermediate", "armpll"; 99 operating-points-v2 = <&cluster0_opp>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0_0: cpu-sleep-0-0 { 106 compatible = "arm,idle-state"; 107 entry-latency-us = <600>; 108 exit-latency-us = <600>; 109 min-residency-us = <1200>; 110 arm,psci-suspend-param = <0x0010000>; 111 }; 112 113 CLUSTER_SLEEP_0: cluster-sleep-0 { 114 compatible = "arm,idle-state"; 115 entry-latency-us = <800>; 116 exit-latency-us = <1000>; 117 min-residency-us = <2000>; 118 arm,psci-suspend-param = <0x2010000>; 119 }; 120 }; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 clk26m: clk26m { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <26000000>; 132 clock-output-names = "clk26m"; 133 }; 134 135 clk32k: clk32k { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <32000>; 139 clock-output-names = "clk32k"; 140 }; 141 142 reserved-memory { 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 147 /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ 148 bl31_secmon_reserved: secmon@43000000 { 149 no-map; 150 reg = <0 0x43000000 0 0x20000>; 151 }; 152 }; 153 154 timer { 155 compatible = "arm,armv8-timer"; 156 interrupt-parent = <&gic>; 157 interrupts = <GIC_PPI 13 158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 14 160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 11 162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 10 164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 165 }; 166 167 pmu { 168 compatible = "arm,armv8-pmuv3"; 169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, 170 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, 171 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, 172 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; 173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 174 }; 175 176 soc { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 compatible = "simple-bus"; 180 ranges; 181 182 topckgen: topckgen@10000000 { 183 compatible = "mediatek,mt8516-topckgen", "syscon"; 184 reg = <0 0x10000000 0 0x1000>; 185 #clock-cells = <1>; 186 }; 187 188 infracfg: infracfg@10001000 { 189 compatible = "mediatek,mt8516-infracfg", "syscon"; 190 reg = <0 0x10001000 0 0x1000>; 191 #clock-cells = <1>; 192 }; 193 194 apmixedsys: apmixedsys@10018000 { 195 compatible = "mediatek,mt8516-apmixedsys", "syscon"; 196 reg = <0 0x10018000 0 0x710>; 197 #clock-cells = <1>; 198 }; 199 200 toprgu: toprgu@10007000 { 201 compatible = "mediatek,mt8516-wdt", 202 "mediatek,mt6589-wdt"; 203 reg = <0 0x10007000 0 0x1000>; 204 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; 205 #reset-cells = <1>; 206 }; 207 208 timer: timer@10008000 { 209 compatible = "mediatek,mt8516-timer", 210 "mediatek,mt6577-timer"; 211 reg = <0 0x10008000 0 0x1000>; 212 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 213 clocks = <&topckgen CLK_TOP_CLK26M_D2>, 214 <&topckgen CLK_TOP_APXGPT>; 215 clock-names = "clk13m", "bus"; 216 }; 217 218 syscfg_pctl: syscfg-pctl@10005000 { 219 compatible = "syscon"; 220 reg = <0 0x10005000 0 0x1000>; 221 }; 222 223 pio: pinctrl@1000b000 { 224 compatible = "mediatek,mt8516-pinctrl"; 225 reg = <0 0x1000b000 0 0x1000>; 226 mediatek,pctl-regmap = <&syscfg_pctl>; 227 pins-are-numbered; 228 gpio-controller; 229 #gpio-cells = <2>; 230 interrupt-controller; 231 #interrupt-cells = <2>; 232 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 233 }; 234 235 pwrap: pwrap@1000f000 { 236 compatible = "mediatek,mt8516-pwrap"; 237 reg = <0 0x1000f000 0 0x1000>; 238 reg-names = "pwrap"; 239 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 240 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, 241 <&topckgen CLK_TOP_PMICWRAP_AP>; 242 clock-names = "spi", "wrap"; 243 }; 244 245 sysirq: interrupt-controller@10200620 { 246 compatible = "mediatek,mt8516-sysirq", 247 "mediatek,mt6577-sysirq"; 248 interrupt-controller; 249 #interrupt-cells = <3>; 250 interrupt-parent = <&gic>; 251 reg = <0 0x10200620 0 0x20>; 252 }; 253 254 gic: interrupt-controller@10310000 { 255 compatible = "arm,gic-400"; 256 #interrupt-cells = <3>; 257 interrupt-parent = <&gic>; 258 interrupt-controller; 259 reg = <0 0x10310000 0 0x1000>, 260 <0 0x10320000 0 0x1000>, 261 <0 0x10340000 0 0x2000>, 262 <0 0x10360000 0 0x2000>; 263 interrupts = <GIC_PPI 9 264 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 265 }; 266 267 uart0: serial@11005000 { 268 compatible = "mediatek,mt8516-uart", 269 "mediatek,mt6577-uart"; 270 reg = <0 0x11005000 0 0x1000>; 271 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 272 clocks = <&topckgen CLK_TOP_UART0_SEL>, 273 <&topckgen CLK_TOP_UART0>; 274 clock-names = "baud", "bus"; 275 status = "disabled"; 276 }; 277 278 uart1: serial@11006000 { 279 compatible = "mediatek,mt8516-uart", 280 "mediatek,mt6577-uart"; 281 reg = <0 0x11006000 0 0x1000>; 282 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 283 clocks = <&topckgen CLK_TOP_UART1_SEL>, 284 <&topckgen CLK_TOP_UART1>; 285 clock-names = "baud", "bus"; 286 status = "disabled"; 287 }; 288 289 uart2: serial@11007000 { 290 compatible = "mediatek,mt8516-uart", 291 "mediatek,mt6577-uart"; 292 reg = <0 0x11007000 0 0x1000>; 293 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; 294 clocks = <&topckgen CLK_TOP_UART2_SEL>, 295 <&topckgen CLK_TOP_UART2>; 296 clock-names = "baud", "bus"; 297 status = "disabled"; 298 }; 299 300 i2c0: i2c@11009000 { 301 compatible = "mediatek,mt8516-i2c", 302 "mediatek,mt2712-i2c"; 303 reg = <0 0x11009000 0 0x90>, 304 <0 0x11000180 0 0x80>; 305 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 306 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, 307 <&infracfg CLK_IFR_I2C0_SEL>, 308 <&topckgen CLK_TOP_I2C0>, 309 <&topckgen CLK_TOP_APDMA>; 310 clock-names = "main-source", 311 "main-sel", 312 "main", 313 "dma"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 319 i2c1: i2c@1100a000 { 320 compatible = "mediatek,mt8516-i2c", 321 "mediatek,mt2712-i2c"; 322 reg = <0 0x1100a000 0 0x90>, 323 <0 0x11000200 0 0x80>; 324 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 325 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, 326 <&infracfg CLK_IFR_I2C1_SEL>, 327 <&topckgen CLK_TOP_I2C1>, 328 <&topckgen CLK_TOP_APDMA>; 329 clock-names = "main-source", 330 "main-sel", 331 "main", 332 "dma"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 status = "disabled"; 336 }; 337 338 i2c2: i2c@1100b000 { 339 compatible = "mediatek,mt8516-i2c", 340 "mediatek,mt2712-i2c"; 341 reg = <0 0x1100b000 0 0x90>, 342 <0 0x11000280 0 0x80>; 343 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 344 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, 345 <&infracfg CLK_IFR_I2C2_SEL>, 346 <&topckgen CLK_TOP_I2C2>, 347 <&topckgen CLK_TOP_APDMA>; 348 clock-names = "main-source", 349 "main-sel", 350 "main", 351 "dma"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 spi: spi@1100c000 { 358 compatible = "mediatek,mt8516-spi", 359 "mediatek,mt2712-spi"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <0 0x1100c000 0 0x1000>; 363 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 364 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, 365 <&topckgen CLK_TOP_SPI_SEL>, 366 <&topckgen CLK_TOP_SPI>; 367 clock-names = "parent-clk", "sel-clk", "spi-clk"; 368 status = "disabled"; 369 }; 370 371 mmc0: mmc@11120000 { 372 compatible = "mediatek,mt8516-mmc"; 373 reg = <0 0x11120000 0 0x1000>; 374 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 375 clocks = <&topckgen CLK_TOP_MSDC0>, 376 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 377 <&topckgen CLK_TOP_MSDC0_INFRA>; 378 clock-names = "source", "hclk", "source_cg"; 379 status = "disabled"; 380 }; 381 382 mmc1: mmc@11130000 { 383 compatible = "mediatek,mt8516-mmc"; 384 reg = <0 0x11130000 0 0x1000>; 385 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 386 clocks = <&topckgen CLK_TOP_MSDC1>, 387 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 388 <&topckgen CLK_TOP_MSDC1_INFRA>; 389 clock-names = "source", "hclk", "source_cg"; 390 status = "disabled"; 391 }; 392 393 mmc2: mmc@11170000 { 394 compatible = "mediatek,mt8516-mmc"; 395 reg = <0 0x11170000 0 0x1000>; 396 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; 397 clocks = <&topckgen CLK_TOP_MSDC2>, 398 <&topckgen CLK_TOP_RG_MSDC2>, 399 <&topckgen CLK_TOP_MSDC2_INFRA>; 400 clock-names = "source", "hclk", "source_cg"; 401 status = "disabled"; 402 }; 403 404 rng: rng@1020c000 { 405 compatible = "mediatek,mt8516-rng", 406 "mediatek,mt7623-rng"; 407 reg = <0 0x1020c000 0 0x100>; 408 clocks = <&topckgen CLK_TOP_TRNG>; 409 clock-names = "rng"; 410 }; 411 412 pwm: pwm@11008000 { 413 compatible = "mediatek,mt8516-pwm"; 414 reg = <0 0x11008000 0 0x1000>; 415 #pwm-cells = <2>; 416 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 417 clocks = <&topckgen CLK_TOP_PWM>, 418 <&topckgen CLK_TOP_PWM_B>, 419 <&topckgen CLK_TOP_PWM1_FB>, 420 <&topckgen CLK_TOP_PWM2_FB>, 421 <&topckgen CLK_TOP_PWM3_FB>, 422 <&topckgen CLK_TOP_PWM4_FB>, 423 <&topckgen CLK_TOP_PWM5_FB>; 424 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 425 "pwm4", "pwm5"; 426 }; 427 428 usb0: usb@11100000 { 429 compatible = "mediatek,mtk-musb"; 430 reg = <0 0x11100000 0 0x1000>; 431 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 432 interrupt-names = "mc"; 433 phys = <&usb0_port PHY_TYPE_USB2>; 434 clocks = <&topckgen CLK_TOP_USB>, 435 <&topckgen CLK_TOP_USBIF>, 436 <&topckgen CLK_TOP_USB_1P>; 437 clock-names = "main","mcu","univpll"; 438 status = "disabled"; 439 }; 440 441 usb0_phy: usb@11110000 { 442 compatible = "mediatek,generic-tphy-v1"; 443 reg = <0 0x11110000 0 0x800>; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 ranges; 447 status = "disabled"; 448 449 usb0_port: usb-phy@11110800 { 450 reg = <0 0x11110800 0 0x100>; 451 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 452 clock-names = "ref"; 453 #phy-cells = <1>; 454 }; 455 }; 456 }; 457}; 458