1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019, Intel Corporation. */ 3 4 #include "ice_base.h" 5 #include "ice_dcb_lib.h" 6 7 /** 8 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI 9 * @qs_cfg: gathered variables needed for PF->VSI queues assignment 10 * 11 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 12 */ 13 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg) 14 { 15 int offset, i; 16 17 mutex_lock(qs_cfg->qs_mutex); 18 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size, 19 0, qs_cfg->q_count, 0); 20 if (offset >= qs_cfg->pf_map_size) { 21 mutex_unlock(qs_cfg->qs_mutex); 22 return -ENOMEM; 23 } 24 25 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count); 26 for (i = 0; i < qs_cfg->q_count; i++) 27 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = i + offset; 28 mutex_unlock(qs_cfg->qs_mutex); 29 30 return 0; 31 } 32 33 /** 34 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI 35 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 36 * 37 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 38 */ 39 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg) 40 { 41 int i, index = 0; 42 43 mutex_lock(qs_cfg->qs_mutex); 44 for (i = 0; i < qs_cfg->q_count; i++) { 45 index = find_next_zero_bit(qs_cfg->pf_map, 46 qs_cfg->pf_map_size, index); 47 if (index >= qs_cfg->pf_map_size) 48 goto err_scatter; 49 set_bit(index, qs_cfg->pf_map); 50 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = index; 51 } 52 mutex_unlock(qs_cfg->qs_mutex); 53 54 return 0; 55 err_scatter: 56 for (index = 0; index < i; index++) { 57 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map); 58 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0; 59 } 60 mutex_unlock(qs_cfg->qs_mutex); 61 62 return -ENOMEM; 63 } 64 65 /** 66 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 67 * @pf: the PF being configured 68 * @pf_q: the PF queue 69 * @ena: enable or disable state of the queue 70 * 71 * This routine will wait for the given Rx queue of the PF to reach the 72 * enabled or disabled state. 73 * Returns -ETIMEDOUT in case of failing to reach the requested state after 74 * multiple retries; else will return 0 in case of success. 75 */ 76 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena) 77 { 78 int i; 79 80 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) { 81 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) & 82 QRX_CTRL_QENA_STAT_M)) 83 return 0; 84 85 usleep_range(20, 40); 86 } 87 88 return -ETIMEDOUT; 89 } 90 91 /** 92 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 93 * @vsi: the VSI being configured 94 * @v_idx: index of the vector in the VSI struct 95 * 96 * We allocate one q_vector and set default value for ITR setting associated 97 * with this q_vector. If allocation fails we return -ENOMEM. 98 */ 99 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx) 100 { 101 struct ice_pf *pf = vsi->back; 102 struct ice_q_vector *q_vector; 103 104 /* allocate q_vector */ 105 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector), 106 GFP_KERNEL); 107 if (!q_vector) 108 return -ENOMEM; 109 110 q_vector->vsi = vsi; 111 q_vector->v_idx = v_idx; 112 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR; 113 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR; 114 if (vsi->type == ICE_VSI_VF) 115 goto out; 116 /* only set affinity_mask if the CPU is online */ 117 if (cpu_online(v_idx)) 118 cpumask_set_cpu(v_idx, &q_vector->affinity_mask); 119 120 /* This will not be called in the driver load path because the netdev 121 * will not be created yet. All other cases with register the NAPI 122 * handler here (i.e. resume, reset/rebuild, etc.) 123 */ 124 if (vsi->netdev) 125 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll, 126 NAPI_POLL_WEIGHT); 127 128 out: 129 /* tie q_vector and VSI together */ 130 vsi->q_vectors[v_idx] = q_vector; 131 132 return 0; 133 } 134 135 /** 136 * ice_free_q_vector - Free memory allocated for a specific interrupt vector 137 * @vsi: VSI having the memory freed 138 * @v_idx: index of the vector to be freed 139 */ 140 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx) 141 { 142 struct ice_q_vector *q_vector; 143 struct ice_pf *pf = vsi->back; 144 struct ice_ring *ring; 145 struct device *dev; 146 147 dev = ice_pf_to_dev(pf); 148 if (!vsi->q_vectors[v_idx]) { 149 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx); 150 return; 151 } 152 q_vector = vsi->q_vectors[v_idx]; 153 154 ice_for_each_ring(ring, q_vector->tx) 155 ring->q_vector = NULL; 156 ice_for_each_ring(ring, q_vector->rx) 157 ring->q_vector = NULL; 158 159 /* only VSI with an associated netdev is set up with NAPI */ 160 if (vsi->netdev) 161 netif_napi_del(&q_vector->napi); 162 163 devm_kfree(dev, q_vector); 164 vsi->q_vectors[v_idx] = NULL; 165 } 166 167 /** 168 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set 169 * @hw: board specific structure 170 */ 171 static void ice_cfg_itr_gran(struct ice_hw *hw) 172 { 173 u32 regval = rd32(hw, GLINT_CTL); 174 175 /* no need to update global register if ITR gran is already set */ 176 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 177 (((regval & GLINT_CTL_ITR_GRAN_200_M) >> 178 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) && 179 (((regval & GLINT_CTL_ITR_GRAN_100_M) >> 180 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) && 181 (((regval & GLINT_CTL_ITR_GRAN_50_M) >> 182 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) && 183 (((regval & GLINT_CTL_ITR_GRAN_25_M) >> 184 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US)) 185 return; 186 187 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & 188 GLINT_CTL_ITR_GRAN_200_M) | 189 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) & 190 GLINT_CTL_ITR_GRAN_100_M) | 191 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) & 192 GLINT_CTL_ITR_GRAN_50_M) | 193 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) & 194 GLINT_CTL_ITR_GRAN_25_M); 195 wr32(hw, GLINT_CTL, regval); 196 } 197 198 /** 199 * ice_calc_q_handle - calculate the queue handle 200 * @vsi: VSI that ring belongs to 201 * @ring: ring to get the absolute queue index 202 * @tc: traffic class number 203 */ 204 static u16 ice_calc_q_handle(struct ice_vsi *vsi, struct ice_ring *ring, u8 tc) 205 { 206 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n"); 207 208 /* Idea here for calculation is that we subtract the number of queue 209 * count from TC that ring belongs to from it's absolute queue index 210 * and as a result we get the queue's index within TC. 211 */ 212 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; 213 } 214 215 /** 216 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance 217 * @ring: The Tx ring to configure 218 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized 219 * @pf_q: queue index in the PF space 220 * 221 * Configure the Tx descriptor ring in TLAN context. 222 */ 223 static void 224 ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q) 225 { 226 struct ice_vsi *vsi = ring->vsi; 227 struct ice_hw *hw = &vsi->back->hw; 228 229 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; 230 231 tlan_ctx->port_num = vsi->port_info->lport; 232 233 /* Transmit Queue Length */ 234 tlan_ctx->qlen = ring->count; 235 236 ice_set_cgd_num(tlan_ctx, ring); 237 238 /* PF number */ 239 tlan_ctx->pf_num = hw->pf_id; 240 241 /* queue belongs to a specific VSI type 242 * VF / VM index should be programmed per vmvf_type setting: 243 * for vmvf_type = VF, it is VF number between 0-256 244 * for vmvf_type = VM, it is VM number between 0-767 245 * for PF or EMP this field should be set to zero 246 */ 247 switch (vsi->type) { 248 case ICE_VSI_LB: 249 case ICE_VSI_PF: 250 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; 251 break; 252 case ICE_VSI_VF: 253 /* Firmware expects vmvf_num to be absolute VF ID */ 254 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id; 255 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF; 256 break; 257 default: 258 return; 259 } 260 261 /* make sure the context is associated with the right VSI */ 262 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx); 263 264 tlan_ctx->tso_ena = ICE_TX_LEGACY; 265 tlan_ctx->tso_qnum = pf_q; 266 267 /* Legacy or Advanced Host Interface: 268 * 0: Advanced Host Interface 269 * 1: Legacy Host Interface 270 */ 271 tlan_ctx->legacy_int = ICE_TX_LEGACY; 272 } 273 274 /** 275 * ice_setup_rx_ctx - Configure a receive ring context 276 * @ring: The Rx ring to configure 277 * 278 * Configure the Rx descriptor ring in RLAN context. 279 */ 280 int ice_setup_rx_ctx(struct ice_ring *ring) 281 { 282 int chain_len = ICE_MAX_CHAINED_RX_BUFS; 283 struct ice_vsi *vsi = ring->vsi; 284 u32 rxdid = ICE_RXDID_FLEX_NIC; 285 struct ice_rlan_ctx rlan_ctx; 286 struct ice_hw *hw; 287 u32 regval; 288 u16 pf_q; 289 int err; 290 291 hw = &vsi->back->hw; 292 293 /* what is Rx queue number in global space of 2K Rx queues */ 294 pf_q = vsi->rxq_map[ring->q_index]; 295 296 /* clear the context structure first */ 297 memset(&rlan_ctx, 0, sizeof(rlan_ctx)); 298 299 ring->rx_buf_len = vsi->rx_buf_len; 300 301 if (ring->vsi->type == ICE_VSI_PF) { 302 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 303 /* coverity[check_return] */ 304 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 305 ring->q_index); 306 307 ring->xsk_umem = ice_xsk_umem(ring); 308 if (ring->xsk_umem) { 309 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 310 311 ring->rx_buf_len = ring->xsk_umem->chunk_size_nohr - 312 XDP_PACKET_HEADROOM; 313 /* For AF_XDP ZC, we disallow packets to span on 314 * multiple buffers, thus letting us skip that 315 * handling in the fast-path. 316 */ 317 chain_len = 1; 318 ring->zca.free = ice_zca_free; 319 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 320 MEM_TYPE_ZERO_COPY, 321 &ring->zca); 322 if (err) 323 return err; 324 325 dev_info(ice_pf_to_dev(vsi->back), "Registered XDP mem model MEM_TYPE_ZERO_COPY on Rx ring %d\n", 326 ring->q_index); 327 } else { 328 ring->zca.free = NULL; 329 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 330 /* coverity[check_return] */ 331 xdp_rxq_info_reg(&ring->xdp_rxq, 332 ring->netdev, 333 ring->q_index); 334 335 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 336 MEM_TYPE_PAGE_SHARED, 337 NULL); 338 if (err) 339 return err; 340 } 341 } 342 /* Receive Queue Base Address. 343 * Indicates the starting address of the descriptor queue defined in 344 * 128 Byte units. 345 */ 346 rlan_ctx.base = ring->dma >> 7; 347 348 rlan_ctx.qlen = ring->count; 349 350 /* Receive Packet Data Buffer Size. 351 * The Packet Data Buffer Size is defined in 128 byte units. 352 */ 353 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; 354 355 /* use 32 byte descriptors */ 356 rlan_ctx.dsize = 1; 357 358 /* Strip the Ethernet CRC bytes before the packet is posted to host 359 * memory. 360 */ 361 rlan_ctx.crcstrip = 1; 362 363 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */ 364 rlan_ctx.l2tsel = 1; 365 366 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT; 367 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT; 368 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT; 369 370 /* This controls whether VLAN is stripped from inner headers 371 * The VLAN in the inner L2 header is stripped to the receive 372 * descriptor if enabled by this flag. 373 */ 374 rlan_ctx.showiv = 0; 375 376 /* Max packet size for this queue - must not be set to a larger value 377 * than 5 x DBUF 378 */ 379 rlan_ctx.rxmax = min_t(u16, vsi->max_frame, 380 chain_len * ring->rx_buf_len); 381 382 /* Rx queue threshold in units of 64 */ 383 rlan_ctx.lrxqthresh = 1; 384 385 /* Enable Flexible Descriptors in the queue context which 386 * allows this driver to select a specific receive descriptor format 387 */ 388 regval = rd32(hw, QRXFLXP_CNTXT(pf_q)); 389 if (vsi->type != ICE_VSI_VF) { 390 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & 391 QRXFLXP_CNTXT_RXDID_IDX_M; 392 393 /* increasing context priority to pick up profile ID; 394 * default is 0x01; setting to 0x03 to ensure profile 395 * is programming if prev context is of same priority 396 */ 397 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & 398 QRXFLXP_CNTXT_RXDID_PRIO_M; 399 400 } else { 401 regval &= ~(QRXFLXP_CNTXT_RXDID_IDX_M | 402 QRXFLXP_CNTXT_RXDID_PRIO_M | 403 QRXFLXP_CNTXT_TS_M); 404 } 405 wr32(hw, QRXFLXP_CNTXT(pf_q), regval); 406 407 /* Absolute queue number out of 2K needs to be passed */ 408 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q); 409 if (err) { 410 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n", 411 pf_q, err); 412 return -EIO; 413 } 414 415 if (vsi->type == ICE_VSI_VF) 416 return 0; 417 418 /* configure Rx buffer alignment */ 419 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) 420 ice_clear_ring_build_skb_ena(ring); 421 else 422 ice_set_ring_build_skb_ena(ring); 423 424 /* init queue specific tail register */ 425 ring->tail = hw->hw_addr + QRX_TAIL(pf_q); 426 writel(0, ring->tail); 427 428 err = ring->xsk_umem ? 429 ice_alloc_rx_bufs_slow_zc(ring, ICE_DESC_UNUSED(ring)) : 430 ice_alloc_rx_bufs(ring, ICE_DESC_UNUSED(ring)); 431 if (err) 432 dev_info(ice_pf_to_dev(vsi->back), "Failed allocate some buffers on %sRx ring %d (pf_q %d)\n", 433 ring->xsk_umem ? "UMEM enabled " : "", 434 ring->q_index, pf_q); 435 436 return 0; 437 } 438 439 /** 440 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI 441 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 442 * 443 * This function first tries to find contiguous space. If it is not successful, 444 * it tries with the scatter approach. 445 * 446 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 447 */ 448 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg) 449 { 450 int ret = 0; 451 452 ret = __ice_vsi_get_qs_contig(qs_cfg); 453 if (ret) { 454 /* contig failed, so try with scatter approach */ 455 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER; 456 qs_cfg->q_count = min_t(u16, qs_cfg->q_count, 457 qs_cfg->scatter_count); 458 ret = __ice_vsi_get_qs_sc(qs_cfg); 459 } 460 return ret; 461 } 462 463 /** 464 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait 465 * @vsi: the VSI being configured 466 * @ena: start or stop the Rx ring 467 * @rxq_idx: 0-based Rx queue index for the VSI passed in 468 * @wait: wait or don't wait for configuration to finish in hardware 469 * 470 * Return 0 on success and negative on error. 471 */ 472 int 473 ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait) 474 { 475 int pf_q = vsi->rxq_map[rxq_idx]; 476 struct ice_pf *pf = vsi->back; 477 struct ice_hw *hw = &pf->hw; 478 u32 rx_reg; 479 480 rx_reg = rd32(hw, QRX_CTRL(pf_q)); 481 482 /* Skip if the queue is already in the requested state */ 483 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) 484 return 0; 485 486 /* turn on/off the queue */ 487 if (ena) 488 rx_reg |= QRX_CTRL_QENA_REQ_M; 489 else 490 rx_reg &= ~QRX_CTRL_QENA_REQ_M; 491 wr32(hw, QRX_CTRL(pf_q), rx_reg); 492 493 if (!wait) 494 return 0; 495 496 ice_flush(hw); 497 return ice_pf_rxq_wait(pf, pf_q, ena); 498 } 499 500 /** 501 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started 502 * @vsi: the VSI being configured 503 * @ena: true/false to verify Rx ring has been enabled/disabled respectively 504 * @rxq_idx: 0-based Rx queue index for the VSI passed in 505 * 506 * This routine will wait for the given Rx queue of the VSI to reach the 507 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach 508 * the requested state after multiple retries; else will return 0 in case of 509 * success. 510 */ 511 int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx) 512 { 513 int pf_q = vsi->rxq_map[rxq_idx]; 514 struct ice_pf *pf = vsi->back; 515 516 return ice_pf_rxq_wait(pf, pf_q, ena); 517 } 518 519 /** 520 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 521 * @vsi: the VSI being configured 522 * 523 * We allocate one q_vector per queue interrupt. If allocation fails we 524 * return -ENOMEM. 525 */ 526 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi) 527 { 528 struct device *dev = ice_pf_to_dev(vsi->back); 529 int v_idx, err; 530 531 if (vsi->q_vectors[0]) { 532 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num); 533 return -EEXIST; 534 } 535 536 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) { 537 err = ice_vsi_alloc_q_vector(vsi, v_idx); 538 if (err) 539 goto err_out; 540 } 541 542 return 0; 543 544 err_out: 545 while (v_idx--) 546 ice_free_q_vector(vsi, v_idx); 547 548 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n", 549 vsi->num_q_vectors, vsi->vsi_num, err); 550 vsi->num_q_vectors = 0; 551 return err; 552 } 553 554 /** 555 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors 556 * @vsi: the VSI being configured 557 * 558 * This function maps descriptor rings to the queue-specific vectors allotted 559 * through the MSI-X enabling code. On a constrained vector budget, we map Tx 560 * and Rx rings to the vector as "efficiently" as possible. 561 */ 562 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi) 563 { 564 int q_vectors = vsi->num_q_vectors; 565 int tx_rings_rem, rx_rings_rem; 566 int v_id; 567 568 /* initially assigning remaining rings count to VSIs num queue value */ 569 tx_rings_rem = vsi->num_txq; 570 rx_rings_rem = vsi->num_rxq; 571 572 for (v_id = 0; v_id < q_vectors; v_id++) { 573 struct ice_q_vector *q_vector = vsi->q_vectors[v_id]; 574 int tx_rings_per_v, rx_rings_per_v, q_id, q_base; 575 576 /* Tx rings mapping to vector */ 577 tx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id); 578 q_vector->num_ring_tx = tx_rings_per_v; 579 q_vector->tx.ring = NULL; 580 q_vector->tx.itr_idx = ICE_TX_ITR; 581 q_base = vsi->num_txq - tx_rings_rem; 582 583 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) { 584 struct ice_ring *tx_ring = vsi->tx_rings[q_id]; 585 586 tx_ring->q_vector = q_vector; 587 tx_ring->next = q_vector->tx.ring; 588 q_vector->tx.ring = tx_ring; 589 } 590 tx_rings_rem -= tx_rings_per_v; 591 592 /* Rx rings mapping to vector */ 593 rx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id); 594 q_vector->num_ring_rx = rx_rings_per_v; 595 q_vector->rx.ring = NULL; 596 q_vector->rx.itr_idx = ICE_RX_ITR; 597 q_base = vsi->num_rxq - rx_rings_rem; 598 599 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) { 600 struct ice_ring *rx_ring = vsi->rx_rings[q_id]; 601 602 rx_ring->q_vector = q_vector; 603 rx_ring->next = q_vector->rx.ring; 604 q_vector->rx.ring = rx_ring; 605 } 606 rx_rings_rem -= rx_rings_per_v; 607 } 608 } 609 610 /** 611 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors 612 * @vsi: the VSI having memory freed 613 */ 614 void ice_vsi_free_q_vectors(struct ice_vsi *vsi) 615 { 616 int v_idx; 617 618 ice_for_each_q_vector(vsi, v_idx) 619 ice_free_q_vector(vsi, v_idx); 620 } 621 622 /** 623 * ice_vsi_cfg_txq - Configure single Tx queue 624 * @vsi: the VSI that queue belongs to 625 * @ring: Tx ring to be configured 626 * @qg_buf: queue group buffer 627 */ 628 int 629 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring, 630 struct ice_aqc_add_tx_qgrp *qg_buf) 631 { 632 struct ice_tlan_ctx tlan_ctx = { 0 }; 633 struct ice_aqc_add_txqs_perq *txq; 634 struct ice_pf *pf = vsi->back; 635 u8 buf_len = sizeof(*qg_buf); 636 enum ice_status status; 637 u16 pf_q; 638 u8 tc; 639 640 pf_q = ring->reg_idx; 641 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q); 642 /* copy context contents into the qg_buf */ 643 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q); 644 ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx, 645 ice_tlan_ctx_info); 646 647 /* init queue specific tail reg. It is referred as 648 * transmit comm scheduler queue doorbell. 649 */ 650 ring->tail = pf->hw.hw_addr + QTX_COMM_DBELL(pf_q); 651 652 if (IS_ENABLED(CONFIG_DCB)) 653 tc = ring->dcb_tc; 654 else 655 tc = 0; 656 657 /* Add unique software queue handle of the Tx queue per 658 * TC into the VSI Tx ring 659 */ 660 ring->q_handle = ice_calc_q_handle(vsi, ring, tc); 661 662 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle, 663 1, qg_buf, buf_len, NULL); 664 if (status) { 665 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %d\n", 666 status); 667 return -ENODEV; 668 } 669 670 /* Add Tx Queue TEID into the VSI Tx ring from the 671 * response. This will complete configuring and 672 * enabling the queue. 673 */ 674 txq = &qg_buf->txqs[0]; 675 if (pf_q == le16_to_cpu(txq->txq_id)) 676 ring->txq_teid = le32_to_cpu(txq->q_teid); 677 678 return 0; 679 } 680 681 /** 682 * ice_cfg_itr - configure the initial interrupt throttle values 683 * @hw: pointer to the HW structure 684 * @q_vector: interrupt vector that's being configured 685 * 686 * Configure interrupt throttling values for the ring containers that are 687 * associated with the interrupt vector passed in. 688 */ 689 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector) 690 { 691 ice_cfg_itr_gran(hw); 692 693 if (q_vector->num_ring_rx) { 694 struct ice_ring_container *rc = &q_vector->rx; 695 696 rc->target_itr = ITR_TO_REG(rc->itr_setting); 697 rc->next_update = jiffies + 1; 698 rc->current_itr = rc->target_itr; 699 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), 700 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 701 } 702 703 if (q_vector->num_ring_tx) { 704 struct ice_ring_container *rc = &q_vector->tx; 705 706 rc->target_itr = ITR_TO_REG(rc->itr_setting); 707 rc->next_update = jiffies + 1; 708 rc->current_itr = rc->target_itr; 709 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), 710 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 711 } 712 } 713 714 /** 715 * ice_cfg_txq_interrupt - configure interrupt on Tx queue 716 * @vsi: the VSI being configured 717 * @txq: Tx queue being mapped to MSI-X vector 718 * @msix_idx: MSI-X vector index within the function 719 * @itr_idx: ITR index of the interrupt cause 720 * 721 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector 722 * within the function space. 723 */ 724 void 725 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 726 { 727 struct ice_pf *pf = vsi->back; 728 struct ice_hw *hw = &pf->hw; 729 u32 val; 730 731 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M; 732 733 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 734 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M); 735 736 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 737 if (ice_is_xdp_ena_vsi(vsi)) { 738 u32 xdp_txq = txq + vsi->num_xdp_txq; 739 740 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 741 val); 742 } 743 ice_flush(hw); 744 } 745 746 /** 747 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue 748 * @vsi: the VSI being configured 749 * @rxq: Rx queue being mapped to MSI-X vector 750 * @msix_idx: MSI-X vector index within the function 751 * @itr_idx: ITR index of the interrupt cause 752 * 753 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector 754 * within the function space. 755 */ 756 void 757 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 758 { 759 struct ice_pf *pf = vsi->back; 760 struct ice_hw *hw = &pf->hw; 761 u32 val; 762 763 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M; 764 765 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 766 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M); 767 768 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 769 770 ice_flush(hw); 771 } 772 773 /** 774 * ice_trigger_sw_intr - trigger a software interrupt 775 * @hw: pointer to the HW structure 776 * @q_vector: interrupt vector to trigger the software interrupt for 777 */ 778 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector) 779 { 780 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 781 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) | 782 GLINT_DYN_CTL_SWINT_TRIG_M | 783 GLINT_DYN_CTL_INTENA_M); 784 } 785 786 /** 787 * ice_vsi_stop_tx_ring - Disable single Tx ring 788 * @vsi: the VSI being configured 789 * @rst_src: reset source 790 * @rel_vmvf_num: Relative ID of VF/VM 791 * @ring: Tx ring to be stopped 792 * @txq_meta: Meta data of Tx ring to be stopped 793 */ 794 int 795 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 796 u16 rel_vmvf_num, struct ice_ring *ring, 797 struct ice_txq_meta *txq_meta) 798 { 799 struct ice_pf *pf = vsi->back; 800 struct ice_q_vector *q_vector; 801 struct ice_hw *hw = &pf->hw; 802 enum ice_status status; 803 u32 val; 804 805 /* clear cause_ena bit for disabled queues */ 806 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); 807 val &= ~QINT_TQCTL_CAUSE_ENA_M; 808 wr32(hw, QINT_TQCTL(ring->reg_idx), val); 809 810 /* software is expected to wait for 100 ns */ 811 ndelay(100); 812 813 /* trigger a software interrupt for the vector 814 * associated to the queue to schedule NAPI handler 815 */ 816 q_vector = ring->q_vector; 817 if (q_vector) 818 ice_trigger_sw_intr(hw, q_vector); 819 820 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx, 821 txq_meta->tc, 1, &txq_meta->q_handle, 822 &txq_meta->q_id, &txq_meta->q_teid, rst_src, 823 rel_vmvf_num, NULL); 824 825 /* if the disable queue command was exercised during an 826 * active reset flow, ICE_ERR_RESET_ONGOING is returned. 827 * This is not an error as the reset operation disables 828 * queues at the hardware level anyway. 829 */ 830 if (status == ICE_ERR_RESET_ONGOING) { 831 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n"); 832 } else if (status == ICE_ERR_DOES_NOT_EXIST) { 833 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n"); 834 } else if (status) { 835 dev_err(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %d\n", 836 status); 837 return -ENODEV; 838 } 839 840 return 0; 841 } 842 843 /** 844 * ice_fill_txq_meta - Prepare the Tx queue's meta data 845 * @vsi: VSI that ring belongs to 846 * @ring: ring that txq_meta will be based on 847 * @txq_meta: a helper struct that wraps Tx queue's information 848 * 849 * Set up a helper struct that will contain all the necessary fields that 850 * are needed for stopping Tx queue 851 */ 852 void 853 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring, 854 struct ice_txq_meta *txq_meta) 855 { 856 u8 tc; 857 858 if (IS_ENABLED(CONFIG_DCB)) 859 tc = ring->dcb_tc; 860 else 861 tc = 0; 862 863 txq_meta->q_id = ring->reg_idx; 864 txq_meta->q_teid = ring->txq_teid; 865 txq_meta->q_handle = ring->q_handle; 866 txq_meta->vsi_idx = vsi->idx; 867 txq_meta->tc = tc; 868 } 869