1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 33 #include <drm/drm_drv.h> 34 #include <drm/drm_ioctl.h> 35 #include <drm/drm_sysfs.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_module.h> 38 #include <drm/ttm/ttm_placement.h> 39 40 #include "ttm_object.h" 41 #include "vmwgfx_binding.h" 42 #include "vmwgfx_drv.h" 43 44 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 45 #define VMWGFX_CHIP_SVGAII 0 46 #define VMW_FB_RESERVATION 0 47 48 #define VMW_MIN_INITIAL_WIDTH 800 49 #define VMW_MIN_INITIAL_HEIGHT 600 50 51 #ifndef VMWGFX_GIT_VERSION 52 #define VMWGFX_GIT_VERSION "Unknown" 53 #endif 54 55 #define VMWGFX_REPO "In Tree" 56 57 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 58 59 60 /** 61 * Fully encoded drm commands. Might move to vmw_drm.h 62 */ 63 64 #define DRM_IOCTL_VMW_GET_PARAM \ 65 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 66 struct drm_vmw_getparam_arg) 67 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 69 union drm_vmw_alloc_dmabuf_arg) 70 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 72 struct drm_vmw_unref_dmabuf_arg) 73 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 75 struct drm_vmw_cursor_bypass_arg) 76 77 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 79 struct drm_vmw_control_stream_arg) 80 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 82 struct drm_vmw_stream_arg) 83 #define DRM_IOCTL_VMW_UNREF_STREAM \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 85 struct drm_vmw_stream_arg) 86 87 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 88 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 89 struct drm_vmw_context_arg) 90 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 92 struct drm_vmw_context_arg) 93 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 95 union drm_vmw_surface_create_arg) 96 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 98 struct drm_vmw_surface_arg) 99 #define DRM_IOCTL_VMW_REF_SURFACE \ 100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 101 union drm_vmw_surface_reference_arg) 102 #define DRM_IOCTL_VMW_EXECBUF \ 103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 104 struct drm_vmw_execbuf_arg) 105 #define DRM_IOCTL_VMW_GET_3D_CAP \ 106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 107 struct drm_vmw_get_3d_cap_arg) 108 #define DRM_IOCTL_VMW_FENCE_WAIT \ 109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 110 struct drm_vmw_fence_wait_arg) 111 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 113 struct drm_vmw_fence_signaled_arg) 114 #define DRM_IOCTL_VMW_FENCE_UNREF \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 116 struct drm_vmw_fence_arg) 117 #define DRM_IOCTL_VMW_FENCE_EVENT \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 119 struct drm_vmw_fence_event_arg) 120 #define DRM_IOCTL_VMW_PRESENT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 122 struct drm_vmw_present_arg) 123 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 125 struct drm_vmw_present_readback_arg) 126 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 128 struct drm_vmw_update_layout_arg) 129 #define DRM_IOCTL_VMW_CREATE_SHADER \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 131 struct drm_vmw_shader_create_arg) 132 #define DRM_IOCTL_VMW_UNREF_SHADER \ 133 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 134 struct drm_vmw_shader_arg) 135 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 136 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 137 union drm_vmw_gb_surface_create_arg) 138 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 140 union drm_vmw_gb_surface_reference_arg) 141 #define DRM_IOCTL_VMW_SYNCCPU \ 142 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 143 struct drm_vmw_synccpu_arg) 144 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 146 struct drm_vmw_context_arg) 147 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 149 union drm_vmw_gb_surface_create_ext_arg) 150 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 152 union drm_vmw_gb_surface_reference_ext_arg) 153 #define DRM_IOCTL_VMW_MSG \ 154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 155 struct drm_vmw_msg_arg) 156 157 /** 158 * The core DRM version of this macro doesn't account for 159 * DRM_COMMAND_BASE. 160 */ 161 162 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 163 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 164 165 /** 166 * Ioctl definitions. 167 */ 168 169 static const struct drm_ioctl_desc vmw_ioctls[] = { 170 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 171 DRM_RENDER_ALLOW), 172 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 173 DRM_RENDER_ALLOW), 174 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 175 DRM_RENDER_ALLOW), 176 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 177 vmw_kms_cursor_bypass_ioctl, 178 DRM_MASTER), 179 180 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 181 DRM_MASTER), 182 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 183 DRM_MASTER), 184 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 185 DRM_MASTER), 186 187 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 188 DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 192 DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 194 DRM_RENDER_ALLOW), 195 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 196 DRM_RENDER_ALLOW), 197 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 198 DRM_RENDER_ALLOW), 199 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 200 DRM_RENDER_ALLOW), 201 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 202 vmw_fence_obj_signaled_ioctl, 203 DRM_RENDER_ALLOW), 204 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 205 DRM_RENDER_ALLOW), 206 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 207 DRM_RENDER_ALLOW), 208 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 209 DRM_RENDER_ALLOW), 210 211 /* these allow direct access to the framebuffers mark as master only */ 212 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 213 DRM_MASTER | DRM_AUTH), 214 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 215 vmw_present_readback_ioctl, 216 DRM_MASTER | DRM_AUTH), 217 /* 218 * The permissions of the below ioctl are overridden in 219 * vmw_generic_ioctl(). We require either 220 * DRM_MASTER or capable(CAP_SYS_ADMIN). 221 */ 222 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 223 vmw_kms_update_layout_ioctl, 224 DRM_RENDER_ALLOW), 225 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 226 vmw_shader_define_ioctl, 227 DRM_RENDER_ALLOW), 228 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 229 vmw_shader_destroy_ioctl, 230 DRM_RENDER_ALLOW), 231 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 232 vmw_gb_surface_define_ioctl, 233 DRM_RENDER_ALLOW), 234 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 235 vmw_gb_surface_reference_ioctl, 236 DRM_RENDER_ALLOW), 237 VMW_IOCTL_DEF(VMW_SYNCCPU, 238 vmw_user_bo_synccpu_ioctl, 239 DRM_RENDER_ALLOW), 240 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 241 vmw_extended_context_define_ioctl, 242 DRM_RENDER_ALLOW), 243 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 244 vmw_gb_surface_define_ext_ioctl, 245 DRM_RENDER_ALLOW), 246 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 247 vmw_gb_surface_reference_ext_ioctl, 248 DRM_RENDER_ALLOW), 249 VMW_IOCTL_DEF(VMW_MSG, 250 vmw_msg_ioctl, 251 DRM_RENDER_ALLOW), 252 }; 253 254 static const struct pci_device_id vmw_pci_id_list[] = { 255 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 256 {0, 0, 0} 257 }; 258 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 259 260 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 261 static int vmw_force_iommu; 262 static int vmw_restrict_iommu; 263 static int vmw_force_coherent; 264 static int vmw_restrict_dma_mask; 265 static int vmw_assume_16bpp; 266 267 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 268 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 269 void *ptr); 270 271 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 272 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 273 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 274 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 275 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 276 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 277 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 278 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 279 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 280 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 281 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 282 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 283 284 285 static void vmw_print_capabilities2(uint32_t capabilities2) 286 { 287 DRM_INFO("Capabilities2:\n"); 288 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 289 DRM_INFO(" Grow oTable.\n"); 290 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 291 DRM_INFO(" IntraSurface copy.\n"); 292 } 293 294 static void vmw_print_capabilities(uint32_t capabilities) 295 { 296 DRM_INFO("Capabilities:\n"); 297 if (capabilities & SVGA_CAP_RECT_COPY) 298 DRM_INFO(" Rect copy.\n"); 299 if (capabilities & SVGA_CAP_CURSOR) 300 DRM_INFO(" Cursor.\n"); 301 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 302 DRM_INFO(" Cursor bypass.\n"); 303 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 304 DRM_INFO(" Cursor bypass 2.\n"); 305 if (capabilities & SVGA_CAP_8BIT_EMULATION) 306 DRM_INFO(" 8bit emulation.\n"); 307 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 308 DRM_INFO(" Alpha cursor.\n"); 309 if (capabilities & SVGA_CAP_3D) 310 DRM_INFO(" 3D.\n"); 311 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 312 DRM_INFO(" Extended Fifo.\n"); 313 if (capabilities & SVGA_CAP_MULTIMON) 314 DRM_INFO(" Multimon.\n"); 315 if (capabilities & SVGA_CAP_PITCHLOCK) 316 DRM_INFO(" Pitchlock.\n"); 317 if (capabilities & SVGA_CAP_IRQMASK) 318 DRM_INFO(" Irq mask.\n"); 319 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 320 DRM_INFO(" Display Topology.\n"); 321 if (capabilities & SVGA_CAP_GMR) 322 DRM_INFO(" GMR.\n"); 323 if (capabilities & SVGA_CAP_TRACES) 324 DRM_INFO(" Traces.\n"); 325 if (capabilities & SVGA_CAP_GMR2) 326 DRM_INFO(" GMR2.\n"); 327 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 328 DRM_INFO(" Screen Object 2.\n"); 329 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 330 DRM_INFO(" Command Buffers.\n"); 331 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 332 DRM_INFO(" Command Buffers 2.\n"); 333 if (capabilities & SVGA_CAP_GBOBJECTS) 334 DRM_INFO(" Guest Backed Resources.\n"); 335 if (capabilities & SVGA_CAP_DX) 336 DRM_INFO(" DX Features.\n"); 337 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 338 DRM_INFO(" HP Command Queue.\n"); 339 } 340 341 /** 342 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 343 * 344 * @dev_priv: A device private structure. 345 * 346 * This function creates a small buffer object that holds the query 347 * result for dummy queries emitted as query barriers. 348 * The function will then map the first page and initialize a pending 349 * occlusion query result structure, Finally it will unmap the buffer. 350 * No interruptible waits are done within this function. 351 * 352 * Returns an error if bo creation or initialization fails. 353 */ 354 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 355 { 356 int ret; 357 struct vmw_buffer_object *vbo; 358 struct ttm_bo_kmap_obj map; 359 volatile SVGA3dQueryResult *result; 360 bool dummy; 361 362 /* 363 * Create the vbo as pinned, so that a tryreserve will 364 * immediately succeed. This is because we're the only 365 * user of the bo currently. 366 */ 367 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 368 if (!vbo) 369 return -ENOMEM; 370 371 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 372 &vmw_sys_ne_placement, false, 373 &vmw_bo_bo_free); 374 if (unlikely(ret != 0)) 375 return ret; 376 377 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 378 BUG_ON(ret != 0); 379 vmw_bo_pin_reserved(vbo, true); 380 381 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 382 if (likely(ret == 0)) { 383 result = ttm_kmap_obj_virtual(&map, &dummy); 384 result->totalSize = sizeof(*result); 385 result->state = SVGA3D_QUERYSTATE_PENDING; 386 result->result32 = 0xff; 387 ttm_bo_kunmap(&map); 388 } 389 vmw_bo_pin_reserved(vbo, false); 390 ttm_bo_unreserve(&vbo->base); 391 392 if (unlikely(ret != 0)) { 393 DRM_ERROR("Dummy query buffer map failed.\n"); 394 vmw_bo_unreference(&vbo); 395 } else 396 dev_priv->dummy_query_bo = vbo; 397 398 return ret; 399 } 400 401 /** 402 * vmw_request_device_late - Perform late device setup 403 * 404 * @dev_priv: Pointer to device private. 405 * 406 * This function performs setup of otables and enables large command 407 * buffer submission. These tasks are split out to a separate function 408 * because it reverts vmw_release_device_early and is intended to be used 409 * by an error path in the hibernation code. 410 */ 411 static int vmw_request_device_late(struct vmw_private *dev_priv) 412 { 413 int ret; 414 415 if (dev_priv->has_mob) { 416 ret = vmw_otables_setup(dev_priv); 417 if (unlikely(ret != 0)) { 418 DRM_ERROR("Unable to initialize " 419 "guest Memory OBjects.\n"); 420 return ret; 421 } 422 } 423 424 if (dev_priv->cman) { 425 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 426 256*4096, 2*4096); 427 if (ret) { 428 struct vmw_cmdbuf_man *man = dev_priv->cman; 429 430 dev_priv->cman = NULL; 431 vmw_cmdbuf_man_destroy(man); 432 } 433 } 434 435 return 0; 436 } 437 438 static int vmw_request_device(struct vmw_private *dev_priv) 439 { 440 int ret; 441 442 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 443 if (unlikely(ret != 0)) { 444 DRM_ERROR("Unable to initialize FIFO.\n"); 445 return ret; 446 } 447 vmw_fence_fifo_up(dev_priv->fman); 448 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 449 if (IS_ERR(dev_priv->cman)) { 450 dev_priv->cman = NULL; 451 dev_priv->has_dx = false; 452 } 453 454 ret = vmw_request_device_late(dev_priv); 455 if (ret) 456 goto out_no_mob; 457 458 ret = vmw_dummy_query_bo_create(dev_priv); 459 if (unlikely(ret != 0)) 460 goto out_no_query_bo; 461 462 return 0; 463 464 out_no_query_bo: 465 if (dev_priv->cman) 466 vmw_cmdbuf_remove_pool(dev_priv->cman); 467 if (dev_priv->has_mob) { 468 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 469 vmw_otables_takedown(dev_priv); 470 } 471 if (dev_priv->cman) 472 vmw_cmdbuf_man_destroy(dev_priv->cman); 473 out_no_mob: 474 vmw_fence_fifo_down(dev_priv->fman); 475 vmw_fifo_release(dev_priv, &dev_priv->fifo); 476 return ret; 477 } 478 479 /** 480 * vmw_release_device_early - Early part of fifo takedown. 481 * 482 * @dev_priv: Pointer to device private struct. 483 * 484 * This is the first part of command submission takedown, to be called before 485 * buffer management is taken down. 486 */ 487 static void vmw_release_device_early(struct vmw_private *dev_priv) 488 { 489 /* 490 * Previous destructions should've released 491 * the pinned bo. 492 */ 493 494 BUG_ON(dev_priv->pinned_bo != NULL); 495 496 vmw_bo_unreference(&dev_priv->dummy_query_bo); 497 if (dev_priv->cman) 498 vmw_cmdbuf_remove_pool(dev_priv->cman); 499 500 if (dev_priv->has_mob) { 501 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 502 vmw_otables_takedown(dev_priv); 503 } 504 } 505 506 /** 507 * vmw_release_device_late - Late part of fifo takedown. 508 * 509 * @dev_priv: Pointer to device private struct. 510 * 511 * This is the last part of the command submission takedown, to be called when 512 * command submission is no longer needed. It may wait on pending fences. 513 */ 514 static void vmw_release_device_late(struct vmw_private *dev_priv) 515 { 516 vmw_fence_fifo_down(dev_priv->fman); 517 if (dev_priv->cman) 518 vmw_cmdbuf_man_destroy(dev_priv->cman); 519 520 vmw_fifo_release(dev_priv, &dev_priv->fifo); 521 } 522 523 /** 524 * Sets the initial_[width|height] fields on the given vmw_private. 525 * 526 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 527 * clamping the value to fb_max_[width|height] fields and the 528 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 529 * If the values appear to be invalid, set them to 530 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 531 */ 532 static void vmw_get_initial_size(struct vmw_private *dev_priv) 533 { 534 uint32_t width; 535 uint32_t height; 536 537 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 538 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 539 540 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 541 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 542 543 if (width > dev_priv->fb_max_width || 544 height > dev_priv->fb_max_height) { 545 546 /* 547 * This is a host error and shouldn't occur. 548 */ 549 550 width = VMW_MIN_INITIAL_WIDTH; 551 height = VMW_MIN_INITIAL_HEIGHT; 552 } 553 554 dev_priv->initial_width = width; 555 dev_priv->initial_height = height; 556 } 557 558 /** 559 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 560 * system. 561 * 562 * @dev_priv: Pointer to a struct vmw_private 563 * 564 * This functions tries to determine what actions need to be taken by the 565 * driver to make system pages visible to the device. 566 * If this function decides that DMA is not possible, it returns -EINVAL. 567 * The driver may then try to disable features of the device that require 568 * DMA. 569 */ 570 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 571 { 572 static const char *names[vmw_dma_map_max] = { 573 [vmw_dma_phys] = "Using physical TTM page addresses.", 574 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 575 [vmw_dma_map_populate] = "Caching DMA mappings.", 576 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 577 578 if (vmw_force_coherent) 579 dev_priv->map_mode = vmw_dma_alloc_coherent; 580 else if (vmw_restrict_iommu) 581 dev_priv->map_mode = vmw_dma_map_bind; 582 else 583 dev_priv->map_mode = vmw_dma_map_populate; 584 585 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 586 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 587 return -EINVAL; 588 589 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 590 return 0; 591 } 592 593 /** 594 * vmw_dma_masks - set required page- and dma masks 595 * 596 * @dev: Pointer to struct drm-device 597 * 598 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 599 * restriction also for 64-bit systems. 600 */ 601 static int vmw_dma_masks(struct vmw_private *dev_priv) 602 { 603 struct drm_device *dev = dev_priv->dev; 604 int ret = 0; 605 606 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 607 if (dev_priv->map_mode != vmw_dma_phys && 608 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 609 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 610 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 611 } 612 613 return ret; 614 } 615 616 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 617 { 618 struct vmw_private *dev_priv; 619 int ret; 620 uint32_t svga_id; 621 enum vmw_res_type i; 622 bool refuse_dma = false; 623 char host_log[100] = {0}; 624 625 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 626 if (unlikely(!dev_priv)) { 627 DRM_ERROR("Failed allocating a device private struct.\n"); 628 return -ENOMEM; 629 } 630 631 pci_set_master(dev->pdev); 632 633 dev_priv->dev = dev; 634 dev_priv->vmw_chipset = chipset; 635 dev_priv->last_read_seqno = (uint32_t) -100; 636 mutex_init(&dev_priv->cmdbuf_mutex); 637 mutex_init(&dev_priv->release_mutex); 638 mutex_init(&dev_priv->binding_mutex); 639 mutex_init(&dev_priv->global_kms_state_mutex); 640 ttm_lock_init(&dev_priv->reservation_sem); 641 spin_lock_init(&dev_priv->resource_lock); 642 spin_lock_init(&dev_priv->hw_lock); 643 spin_lock_init(&dev_priv->waiter_lock); 644 spin_lock_init(&dev_priv->cap_lock); 645 spin_lock_init(&dev_priv->svga_lock); 646 spin_lock_init(&dev_priv->cursor_lock); 647 648 for (i = vmw_res_context; i < vmw_res_max; ++i) { 649 idr_init(&dev_priv->res_idr[i]); 650 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 651 } 652 653 init_waitqueue_head(&dev_priv->fence_queue); 654 init_waitqueue_head(&dev_priv->fifo_queue); 655 dev_priv->fence_queue_waiters = 0; 656 dev_priv->fifo_queue_waiters = 0; 657 658 dev_priv->used_memory_size = 0; 659 660 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 661 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 662 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 663 664 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 665 666 dev_priv->enable_fb = enable_fbdev; 667 668 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 669 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 670 if (svga_id != SVGA_ID_2) { 671 ret = -ENOSYS; 672 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 673 goto out_err0; 674 } 675 676 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 677 678 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 679 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 680 } 681 682 683 ret = vmw_dma_select_mode(dev_priv); 684 if (unlikely(ret != 0)) { 685 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 686 refuse_dma = true; 687 } 688 689 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 690 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 691 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 692 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 693 694 vmw_get_initial_size(dev_priv); 695 696 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 697 dev_priv->max_gmr_ids = 698 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 699 dev_priv->max_gmr_pages = 700 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 701 dev_priv->memory_size = 702 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 703 dev_priv->memory_size -= dev_priv->vram_size; 704 } else { 705 /* 706 * An arbitrary limit of 512MiB on surface 707 * memory. But all HWV8 hardware supports GMR2. 708 */ 709 dev_priv->memory_size = 512*1024*1024; 710 } 711 dev_priv->max_mob_pages = 0; 712 dev_priv->max_mob_size = 0; 713 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 714 uint64_t mem_size = 715 vmw_read(dev_priv, 716 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 717 718 /* 719 * Workaround for low memory 2D VMs to compensate for the 720 * allocation taken by fbdev 721 */ 722 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 723 mem_size *= 3; 724 725 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 726 dev_priv->prim_bb_mem = 727 vmw_read(dev_priv, 728 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 729 dev_priv->max_mob_size = 730 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 731 dev_priv->stdu_max_width = 732 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 733 dev_priv->stdu_max_height = 734 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 735 736 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 737 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 738 dev_priv->texture_max_width = vmw_read(dev_priv, 739 SVGA_REG_DEV_CAP); 740 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 741 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 742 dev_priv->texture_max_height = vmw_read(dev_priv, 743 SVGA_REG_DEV_CAP); 744 } else { 745 dev_priv->texture_max_width = 8192; 746 dev_priv->texture_max_height = 8192; 747 dev_priv->prim_bb_mem = dev_priv->vram_size; 748 } 749 750 vmw_print_capabilities(dev_priv->capabilities); 751 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 752 vmw_print_capabilities2(dev_priv->capabilities2); 753 754 ret = vmw_dma_masks(dev_priv); 755 if (unlikely(ret != 0)) 756 goto out_err0; 757 758 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 759 SCATTERLIST_MAX_SEGMENT)); 760 761 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 762 DRM_INFO("Max GMR ids is %u\n", 763 (unsigned)dev_priv->max_gmr_ids); 764 DRM_INFO("Max number of GMR pages is %u\n", 765 (unsigned)dev_priv->max_gmr_pages); 766 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 767 (unsigned)dev_priv->memory_size / 1024); 768 } 769 DRM_INFO("Maximum display memory size is %u kiB\n", 770 dev_priv->prim_bb_mem / 1024); 771 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 772 dev_priv->vram_start, dev_priv->vram_size / 1024); 773 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 774 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 775 776 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 777 dev_priv->mmio_size, MEMREMAP_WB); 778 779 if (unlikely(dev_priv->mmio_virt == NULL)) { 780 ret = -ENOMEM; 781 DRM_ERROR("Failed mapping MMIO.\n"); 782 goto out_err0; 783 } 784 785 /* Need mmio memory to check for fifo pitchlock cap. */ 786 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 787 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 788 !vmw_fifo_have_pitchlock(dev_priv)) { 789 ret = -ENOSYS; 790 DRM_ERROR("Hardware has no pitchlock\n"); 791 goto out_err4; 792 } 793 794 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 795 &vmw_prime_dmabuf_ops); 796 797 if (unlikely(dev_priv->tdev == NULL)) { 798 DRM_ERROR("Unable to initialize TTM object management.\n"); 799 ret = -ENOMEM; 800 goto out_err4; 801 } 802 803 dev->dev_private = dev_priv; 804 805 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 806 dev_priv->stealth = (ret != 0); 807 if (dev_priv->stealth) { 808 /** 809 * Request at least the mmio PCI resource. 810 */ 811 812 DRM_INFO("It appears like vesafb is loaded. " 813 "Ignore above error if any.\n"); 814 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 815 if (unlikely(ret != 0)) { 816 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 817 goto out_no_device; 818 } 819 } 820 821 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 822 ret = vmw_irq_install(dev, dev->pdev->irq); 823 if (ret != 0) { 824 DRM_ERROR("Failed installing irq: %d\n", ret); 825 goto out_no_irq; 826 } 827 } 828 829 dev_priv->fman = vmw_fence_manager_init(dev_priv); 830 if (unlikely(dev_priv->fman == NULL)) { 831 ret = -ENOMEM; 832 goto out_no_fman; 833 } 834 835 drm_vma_offset_manager_init(&dev_priv->vma_manager, 836 DRM_FILE_PAGE_OFFSET_START, 837 DRM_FILE_PAGE_OFFSET_SIZE); 838 ret = ttm_bo_device_init(&dev_priv->bdev, 839 &vmw_bo_driver, 840 dev->anon_inode->i_mapping, 841 &dev_priv->vma_manager, 842 false); 843 if (unlikely(ret != 0)) { 844 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 845 goto out_no_bdev; 846 } 847 848 /* 849 * Enable VRAM, but initially don't use it until SVGA is enabled and 850 * unhidden. 851 */ 852 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 853 (dev_priv->vram_size >> PAGE_SHIFT)); 854 if (unlikely(ret != 0)) { 855 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 856 goto out_no_vram; 857 } 858 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 859 860 dev_priv->has_gmr = true; 861 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 862 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 863 VMW_PL_GMR) != 0) { 864 DRM_INFO("No GMR memory available. " 865 "Graphics memory resources are very limited.\n"); 866 dev_priv->has_gmr = false; 867 } 868 869 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 870 dev_priv->has_mob = true; 871 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 872 VMW_PL_MOB) != 0) { 873 DRM_INFO("No MOB memory available. " 874 "3D will be disabled.\n"); 875 dev_priv->has_mob = false; 876 } 877 } 878 879 if (dev_priv->has_mob) { 880 spin_lock(&dev_priv->cap_lock); 881 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 882 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 883 spin_unlock(&dev_priv->cap_lock); 884 } 885 886 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 887 ret = vmw_kms_init(dev_priv); 888 if (unlikely(ret != 0)) 889 goto out_no_kms; 890 vmw_overlay_init(dev_priv); 891 892 ret = vmw_request_device(dev_priv); 893 if (ret) 894 goto out_no_fifo; 895 896 if (dev_priv->has_dx) { 897 /* 898 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 899 * support 900 */ 901 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 902 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 903 SVGA3D_DEVCAP_SM41); 904 dev_priv->has_sm4_1 = vmw_read(dev_priv, 905 SVGA_REG_DEV_CAP); 906 } 907 } 908 909 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 910 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 911 ? "yes." : "no."); 912 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 913 914 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 915 VMWGFX_REPO, VMWGFX_GIT_VERSION); 916 vmw_host_log(host_log); 917 918 memset(host_log, 0, sizeof(host_log)); 919 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 920 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 921 VMWGFX_DRIVER_PATCHLEVEL); 922 vmw_host_log(host_log); 923 924 if (dev_priv->enable_fb) { 925 vmw_fifo_resource_inc(dev_priv); 926 vmw_svga_enable(dev_priv); 927 vmw_fb_init(dev_priv); 928 } 929 930 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 931 register_pm_notifier(&dev_priv->pm_nb); 932 933 return 0; 934 935 out_no_fifo: 936 vmw_overlay_close(dev_priv); 937 vmw_kms_close(dev_priv); 938 out_no_kms: 939 if (dev_priv->has_mob) 940 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 941 if (dev_priv->has_gmr) 942 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 943 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 944 out_no_vram: 945 (void)ttm_bo_device_release(&dev_priv->bdev); 946 out_no_bdev: 947 vmw_fence_manager_takedown(dev_priv->fman); 948 out_no_fman: 949 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 950 vmw_irq_uninstall(dev_priv->dev); 951 out_no_irq: 952 if (dev_priv->stealth) 953 pci_release_region(dev->pdev, 2); 954 else 955 pci_release_regions(dev->pdev); 956 out_no_device: 957 ttm_object_device_release(&dev_priv->tdev); 958 out_err4: 959 memunmap(dev_priv->mmio_virt); 960 out_err0: 961 for (i = vmw_res_context; i < vmw_res_max; ++i) 962 idr_destroy(&dev_priv->res_idr[i]); 963 964 if (dev_priv->ctx.staged_bindings) 965 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 966 kfree(dev_priv); 967 return ret; 968 } 969 970 static void vmw_driver_unload(struct drm_device *dev) 971 { 972 struct vmw_private *dev_priv = vmw_priv(dev); 973 enum vmw_res_type i; 974 975 unregister_pm_notifier(&dev_priv->pm_nb); 976 977 if (dev_priv->ctx.res_ht_initialized) 978 drm_ht_remove(&dev_priv->ctx.res_ht); 979 vfree(dev_priv->ctx.cmd_bounce); 980 if (dev_priv->enable_fb) { 981 vmw_fb_off(dev_priv); 982 vmw_fb_close(dev_priv); 983 vmw_fifo_resource_dec(dev_priv); 984 vmw_svga_disable(dev_priv); 985 } 986 987 vmw_kms_close(dev_priv); 988 vmw_overlay_close(dev_priv); 989 990 if (dev_priv->has_gmr) 991 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 992 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 993 994 vmw_release_device_early(dev_priv); 995 if (dev_priv->has_mob) 996 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 997 (void) ttm_bo_device_release(&dev_priv->bdev); 998 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 999 vmw_release_device_late(dev_priv); 1000 vmw_fence_manager_takedown(dev_priv->fman); 1001 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1002 vmw_irq_uninstall(dev_priv->dev); 1003 if (dev_priv->stealth) 1004 pci_release_region(dev->pdev, 2); 1005 else 1006 pci_release_regions(dev->pdev); 1007 1008 ttm_object_device_release(&dev_priv->tdev); 1009 memunmap(dev_priv->mmio_virt); 1010 if (dev_priv->ctx.staged_bindings) 1011 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1012 1013 for (i = vmw_res_context; i < vmw_res_max; ++i) 1014 idr_destroy(&dev_priv->res_idr[i]); 1015 1016 kfree(dev_priv); 1017 } 1018 1019 static void vmw_postclose(struct drm_device *dev, 1020 struct drm_file *file_priv) 1021 { 1022 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1023 1024 ttm_object_file_release(&vmw_fp->tfile); 1025 kfree(vmw_fp); 1026 } 1027 1028 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1029 { 1030 struct vmw_private *dev_priv = vmw_priv(dev); 1031 struct vmw_fpriv *vmw_fp; 1032 int ret = -ENOMEM; 1033 1034 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1035 if (unlikely(!vmw_fp)) 1036 return ret; 1037 1038 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1039 if (unlikely(vmw_fp->tfile == NULL)) 1040 goto out_no_tfile; 1041 1042 file_priv->driver_priv = vmw_fp; 1043 1044 return 0; 1045 1046 out_no_tfile: 1047 kfree(vmw_fp); 1048 return ret; 1049 } 1050 1051 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1052 unsigned long arg, 1053 long (*ioctl_func)(struct file *, unsigned int, 1054 unsigned long)) 1055 { 1056 struct drm_file *file_priv = filp->private_data; 1057 struct drm_device *dev = file_priv->minor->dev; 1058 unsigned int nr = DRM_IOCTL_NR(cmd); 1059 unsigned int flags; 1060 1061 /* 1062 * Do extra checking on driver private ioctls. 1063 */ 1064 1065 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1066 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1067 const struct drm_ioctl_desc *ioctl = 1068 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1069 1070 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1071 return ioctl_func(filp, cmd, arg); 1072 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1073 if (!drm_is_current_master(file_priv) && 1074 !capable(CAP_SYS_ADMIN)) 1075 return -EACCES; 1076 } 1077 1078 if (unlikely(ioctl->cmd != cmd)) 1079 goto out_io_encoding; 1080 1081 flags = ioctl->flags; 1082 } else if (!drm_ioctl_flags(nr, &flags)) 1083 return -EINVAL; 1084 1085 return ioctl_func(filp, cmd, arg); 1086 1087 out_io_encoding: 1088 DRM_ERROR("Invalid command format, ioctl %d\n", 1089 nr - DRM_COMMAND_BASE); 1090 1091 return -EINVAL; 1092 } 1093 1094 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1095 unsigned long arg) 1096 { 1097 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1098 } 1099 1100 #ifdef CONFIG_COMPAT 1101 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1102 unsigned long arg) 1103 { 1104 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1105 } 1106 #endif 1107 1108 static int vmw_master_set(struct drm_device *dev, 1109 struct drm_file *file_priv, 1110 bool from_open) 1111 { 1112 /* 1113 * Inform a new master that the layout may have changed while 1114 * it was gone. 1115 */ 1116 if (!from_open) 1117 drm_sysfs_hotplug_event(dev); 1118 1119 return 0; 1120 } 1121 1122 static void vmw_master_drop(struct drm_device *dev, 1123 struct drm_file *file_priv) 1124 { 1125 struct vmw_private *dev_priv = vmw_priv(dev); 1126 1127 vmw_kms_legacy_hotspot_clear(dev_priv); 1128 if (!dev_priv->enable_fb) 1129 vmw_svga_disable(dev_priv); 1130 } 1131 1132 /** 1133 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1134 * 1135 * @dev_priv: Pointer to device private struct. 1136 * Needs the reservation sem to be held in non-exclusive mode. 1137 */ 1138 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1139 { 1140 spin_lock(&dev_priv->svga_lock); 1141 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1142 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1143 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1144 } 1145 spin_unlock(&dev_priv->svga_lock); 1146 } 1147 1148 /** 1149 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1150 * 1151 * @dev_priv: Pointer to device private struct. 1152 */ 1153 void vmw_svga_enable(struct vmw_private *dev_priv) 1154 { 1155 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1156 __vmw_svga_enable(dev_priv); 1157 ttm_read_unlock(&dev_priv->reservation_sem); 1158 } 1159 1160 /** 1161 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1162 * 1163 * @dev_priv: Pointer to device private struct. 1164 * Needs the reservation sem to be held in exclusive mode. 1165 * Will not empty VRAM. VRAM must be emptied by caller. 1166 */ 1167 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1168 { 1169 spin_lock(&dev_priv->svga_lock); 1170 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1171 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1172 vmw_write(dev_priv, SVGA_REG_ENABLE, 1173 SVGA_REG_ENABLE_HIDE | 1174 SVGA_REG_ENABLE_ENABLE); 1175 } 1176 spin_unlock(&dev_priv->svga_lock); 1177 } 1178 1179 /** 1180 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1181 * running. 1182 * 1183 * @dev_priv: Pointer to device private struct. 1184 * Will empty VRAM. 1185 */ 1186 void vmw_svga_disable(struct vmw_private *dev_priv) 1187 { 1188 /* 1189 * Disabling SVGA will turn off device modesetting capabilities, so 1190 * notify KMS about that so that it doesn't cache atomic state that 1191 * isn't valid anymore, for example crtcs turned on. 1192 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1193 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1194 * end up with lock order reversal. Thus, a master may actually perform 1195 * a new modeset just after we call vmw_kms_lost_device() and race with 1196 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1197 * to be inconsistent with the device, causing modesetting problems. 1198 * 1199 */ 1200 vmw_kms_lost_device(dev_priv->dev); 1201 ttm_write_lock(&dev_priv->reservation_sem, false); 1202 spin_lock(&dev_priv->svga_lock); 1203 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1204 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1205 spin_unlock(&dev_priv->svga_lock); 1206 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1207 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1208 vmw_write(dev_priv, SVGA_REG_ENABLE, 1209 SVGA_REG_ENABLE_HIDE | 1210 SVGA_REG_ENABLE_ENABLE); 1211 } else 1212 spin_unlock(&dev_priv->svga_lock); 1213 ttm_write_unlock(&dev_priv->reservation_sem); 1214 } 1215 1216 static void vmw_remove(struct pci_dev *pdev) 1217 { 1218 struct drm_device *dev = pci_get_drvdata(pdev); 1219 1220 drm_dev_unregister(dev); 1221 vmw_driver_unload(dev); 1222 drm_dev_put(dev); 1223 pci_disable_device(pdev); 1224 } 1225 1226 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1227 void *ptr) 1228 { 1229 struct vmw_private *dev_priv = 1230 container_of(nb, struct vmw_private, pm_nb); 1231 1232 switch (val) { 1233 case PM_HIBERNATION_PREPARE: 1234 /* 1235 * Take the reservation sem in write mode, which will make sure 1236 * there are no other processes holding a buffer object 1237 * reservation, meaning we should be able to evict all buffer 1238 * objects if needed. 1239 * Once user-space processes have been frozen, we can release 1240 * the lock again. 1241 */ 1242 ttm_suspend_lock(&dev_priv->reservation_sem); 1243 dev_priv->suspend_locked = true; 1244 break; 1245 case PM_POST_HIBERNATION: 1246 case PM_POST_RESTORE: 1247 if (READ_ONCE(dev_priv->suspend_locked)) { 1248 dev_priv->suspend_locked = false; 1249 ttm_suspend_unlock(&dev_priv->reservation_sem); 1250 } 1251 break; 1252 default: 1253 break; 1254 } 1255 return 0; 1256 } 1257 1258 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1259 { 1260 struct drm_device *dev = pci_get_drvdata(pdev); 1261 struct vmw_private *dev_priv = vmw_priv(dev); 1262 1263 if (dev_priv->refuse_hibernation) 1264 return -EBUSY; 1265 1266 pci_save_state(pdev); 1267 pci_disable_device(pdev); 1268 pci_set_power_state(pdev, PCI_D3hot); 1269 return 0; 1270 } 1271 1272 static int vmw_pci_resume(struct pci_dev *pdev) 1273 { 1274 pci_set_power_state(pdev, PCI_D0); 1275 pci_restore_state(pdev); 1276 return pci_enable_device(pdev); 1277 } 1278 1279 static int vmw_pm_suspend(struct device *kdev) 1280 { 1281 struct pci_dev *pdev = to_pci_dev(kdev); 1282 struct pm_message dummy; 1283 1284 dummy.event = 0; 1285 1286 return vmw_pci_suspend(pdev, dummy); 1287 } 1288 1289 static int vmw_pm_resume(struct device *kdev) 1290 { 1291 struct pci_dev *pdev = to_pci_dev(kdev); 1292 1293 return vmw_pci_resume(pdev); 1294 } 1295 1296 static int vmw_pm_freeze(struct device *kdev) 1297 { 1298 struct pci_dev *pdev = to_pci_dev(kdev); 1299 struct drm_device *dev = pci_get_drvdata(pdev); 1300 struct vmw_private *dev_priv = vmw_priv(dev); 1301 int ret; 1302 1303 /* 1304 * Unlock for vmw_kms_suspend. 1305 * No user-space processes should be running now. 1306 */ 1307 ttm_suspend_unlock(&dev_priv->reservation_sem); 1308 ret = vmw_kms_suspend(dev_priv->dev); 1309 if (ret) { 1310 ttm_suspend_lock(&dev_priv->reservation_sem); 1311 DRM_ERROR("Failed to freeze modesetting.\n"); 1312 return ret; 1313 } 1314 if (dev_priv->enable_fb) 1315 vmw_fb_off(dev_priv); 1316 1317 ttm_suspend_lock(&dev_priv->reservation_sem); 1318 vmw_execbuf_release_pinned_bo(dev_priv); 1319 vmw_resource_evict_all(dev_priv); 1320 vmw_release_device_early(dev_priv); 1321 ttm_bo_swapout_all(&dev_priv->bdev); 1322 if (dev_priv->enable_fb) 1323 vmw_fifo_resource_dec(dev_priv); 1324 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1325 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1326 if (dev_priv->enable_fb) 1327 vmw_fifo_resource_inc(dev_priv); 1328 WARN_ON(vmw_request_device_late(dev_priv)); 1329 dev_priv->suspend_locked = false; 1330 ttm_suspend_unlock(&dev_priv->reservation_sem); 1331 if (dev_priv->suspend_state) 1332 vmw_kms_resume(dev); 1333 if (dev_priv->enable_fb) 1334 vmw_fb_on(dev_priv); 1335 return -EBUSY; 1336 } 1337 1338 vmw_fence_fifo_down(dev_priv->fman); 1339 __vmw_svga_disable(dev_priv); 1340 1341 vmw_release_device_late(dev_priv); 1342 return 0; 1343 } 1344 1345 static int vmw_pm_restore(struct device *kdev) 1346 { 1347 struct pci_dev *pdev = to_pci_dev(kdev); 1348 struct drm_device *dev = pci_get_drvdata(pdev); 1349 struct vmw_private *dev_priv = vmw_priv(dev); 1350 int ret; 1351 1352 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1353 (void) vmw_read(dev_priv, SVGA_REG_ID); 1354 1355 if (dev_priv->enable_fb) 1356 vmw_fifo_resource_inc(dev_priv); 1357 1358 ret = vmw_request_device(dev_priv); 1359 if (ret) 1360 return ret; 1361 1362 if (dev_priv->enable_fb) 1363 __vmw_svga_enable(dev_priv); 1364 1365 vmw_fence_fifo_up(dev_priv->fman); 1366 dev_priv->suspend_locked = false; 1367 ttm_suspend_unlock(&dev_priv->reservation_sem); 1368 if (dev_priv->suspend_state) 1369 vmw_kms_resume(dev_priv->dev); 1370 1371 if (dev_priv->enable_fb) 1372 vmw_fb_on(dev_priv); 1373 1374 return 0; 1375 } 1376 1377 static const struct dev_pm_ops vmw_pm_ops = { 1378 .freeze = vmw_pm_freeze, 1379 .thaw = vmw_pm_restore, 1380 .restore = vmw_pm_restore, 1381 .suspend = vmw_pm_suspend, 1382 .resume = vmw_pm_resume, 1383 }; 1384 1385 static const struct file_operations vmwgfx_driver_fops = { 1386 .owner = THIS_MODULE, 1387 .open = drm_open, 1388 .release = drm_release, 1389 .unlocked_ioctl = vmw_unlocked_ioctl, 1390 .mmap = vmw_mmap, 1391 .poll = vmw_fops_poll, 1392 .read = vmw_fops_read, 1393 #if defined(CONFIG_COMPAT) 1394 .compat_ioctl = vmw_compat_ioctl, 1395 #endif 1396 .llseek = noop_llseek, 1397 }; 1398 1399 static struct drm_driver driver = { 1400 .driver_features = 1401 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1402 .get_vblank_counter = vmw_get_vblank_counter, 1403 .enable_vblank = vmw_enable_vblank, 1404 .disable_vblank = vmw_disable_vblank, 1405 .ioctls = vmw_ioctls, 1406 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1407 .master_set = vmw_master_set, 1408 .master_drop = vmw_master_drop, 1409 .open = vmw_driver_open, 1410 .postclose = vmw_postclose, 1411 1412 .dumb_create = vmw_dumb_create, 1413 .dumb_map_offset = vmw_dumb_map_offset, 1414 .dumb_destroy = vmw_dumb_destroy, 1415 1416 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1417 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1418 1419 .fops = &vmwgfx_driver_fops, 1420 .name = VMWGFX_DRIVER_NAME, 1421 .desc = VMWGFX_DRIVER_DESC, 1422 .date = VMWGFX_DRIVER_DATE, 1423 .major = VMWGFX_DRIVER_MAJOR, 1424 .minor = VMWGFX_DRIVER_MINOR, 1425 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1426 }; 1427 1428 static struct pci_driver vmw_pci_driver = { 1429 .name = VMWGFX_DRIVER_NAME, 1430 .id_table = vmw_pci_id_list, 1431 .probe = vmw_probe, 1432 .remove = vmw_remove, 1433 .driver = { 1434 .pm = &vmw_pm_ops 1435 } 1436 }; 1437 1438 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1439 { 1440 struct drm_device *dev; 1441 int ret; 1442 1443 ret = pci_enable_device(pdev); 1444 if (ret) 1445 return ret; 1446 1447 dev = drm_dev_alloc(&driver, &pdev->dev); 1448 if (IS_ERR(dev)) { 1449 ret = PTR_ERR(dev); 1450 goto err_pci_disable_device; 1451 } 1452 1453 dev->pdev = pdev; 1454 pci_set_drvdata(pdev, dev); 1455 1456 ret = vmw_driver_load(dev, ent->driver_data); 1457 if (ret) 1458 goto err_drm_dev_put; 1459 1460 ret = drm_dev_register(dev, ent->driver_data); 1461 if (ret) 1462 goto err_vmw_driver_unload; 1463 1464 return 0; 1465 1466 err_vmw_driver_unload: 1467 vmw_driver_unload(dev); 1468 err_drm_dev_put: 1469 drm_dev_put(dev); 1470 err_pci_disable_device: 1471 pci_disable_device(pdev); 1472 return ret; 1473 } 1474 1475 static int __init vmwgfx_init(void) 1476 { 1477 int ret; 1478 1479 if (vgacon_text_force()) 1480 return -EINVAL; 1481 1482 ret = pci_register_driver(&vmw_pci_driver); 1483 if (ret) 1484 DRM_ERROR("Failed initializing DRM.\n"); 1485 return ret; 1486 } 1487 1488 static void __exit vmwgfx_exit(void) 1489 { 1490 pci_unregister_driver(&vmw_pci_driver); 1491 } 1492 1493 module_init(vmwgfx_init); 1494 module_exit(vmwgfx_exit); 1495 1496 MODULE_AUTHOR("VMware Inc. and others"); 1497 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1498 MODULE_LICENSE("GPL and additional rights"); 1499 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1500 __stringify(VMWGFX_DRIVER_MINOR) "." 1501 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1502 "0"); 1503