1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 29 #include "e1000.h" 30 31 #define DRV_EXTRAVERSION "-k" 32 33 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 34 char e1000e_driver_name[] = "e1000e"; 35 const char e1000e_driver_version[] = DRV_VERSION; 36 37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 38 static int debug = -1; 39 module_param(debug, int, 0); 40 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 41 42 static const struct e1000_info *e1000_info_tbl[] = { 43 [board_82571] = &e1000_82571_info, 44 [board_82572] = &e1000_82572_info, 45 [board_82573] = &e1000_82573_info, 46 [board_82574] = &e1000_82574_info, 47 [board_82583] = &e1000_82583_info, 48 [board_80003es2lan] = &e1000_es2_info, 49 [board_ich8lan] = &e1000_ich8_info, 50 [board_ich9lan] = &e1000_ich9_info, 51 [board_ich10lan] = &e1000_ich10_info, 52 [board_pchlan] = &e1000_pch_info, 53 [board_pch2lan] = &e1000_pch2_info, 54 [board_pch_lpt] = &e1000_pch_lpt_info, 55 [board_pch_spt] = &e1000_pch_spt_info, 56 [board_pch_cnp] = &e1000_pch_cnp_info, 57 }; 58 59 struct e1000_reg_info { 60 u32 ofs; 61 char *name; 62 }; 63 64 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 65 /* General Registers */ 66 {E1000_CTRL, "CTRL"}, 67 {E1000_STATUS, "STATUS"}, 68 {E1000_CTRL_EXT, "CTRL_EXT"}, 69 70 /* Interrupt Registers */ 71 {E1000_ICR, "ICR"}, 72 73 /* Rx Registers */ 74 {E1000_RCTL, "RCTL"}, 75 {E1000_RDLEN(0), "RDLEN"}, 76 {E1000_RDH(0), "RDH"}, 77 {E1000_RDT(0), "RDT"}, 78 {E1000_RDTR, "RDTR"}, 79 {E1000_RXDCTL(0), "RXDCTL"}, 80 {E1000_ERT, "ERT"}, 81 {E1000_RDBAL(0), "RDBAL"}, 82 {E1000_RDBAH(0), "RDBAH"}, 83 {E1000_RDFH, "RDFH"}, 84 {E1000_RDFT, "RDFT"}, 85 {E1000_RDFHS, "RDFHS"}, 86 {E1000_RDFTS, "RDFTS"}, 87 {E1000_RDFPC, "RDFPC"}, 88 89 /* Tx Registers */ 90 {E1000_TCTL, "TCTL"}, 91 {E1000_TDBAL(0), "TDBAL"}, 92 {E1000_TDBAH(0), "TDBAH"}, 93 {E1000_TDLEN(0), "TDLEN"}, 94 {E1000_TDH(0), "TDH"}, 95 {E1000_TDT(0), "TDT"}, 96 {E1000_TIDV, "TIDV"}, 97 {E1000_TXDCTL(0), "TXDCTL"}, 98 {E1000_TADV, "TADV"}, 99 {E1000_TARC(0), "TARC"}, 100 {E1000_TDFH, "TDFH"}, 101 {E1000_TDFT, "TDFT"}, 102 {E1000_TDFHS, "TDFHS"}, 103 {E1000_TDFTS, "TDFTS"}, 104 {E1000_TDFPC, "TDFPC"}, 105 106 /* List Terminator */ 107 {0, NULL} 108 }; 109 110 struct e1000e_me_supported { 111 u16 device_id; /* supported device ID */ 112 }; 113 114 static const struct e1000e_me_supported me_supported[] = { 115 {E1000_DEV_ID_PCH_LPT_I217_LM}, 116 {E1000_DEV_ID_PCH_LPTLP_I218_LM}, 117 {E1000_DEV_ID_PCH_I218_LM2}, 118 {E1000_DEV_ID_PCH_I218_LM3}, 119 {E1000_DEV_ID_PCH_SPT_I219_LM}, 120 {E1000_DEV_ID_PCH_SPT_I219_LM2}, 121 {E1000_DEV_ID_PCH_LBG_I219_LM3}, 122 {E1000_DEV_ID_PCH_SPT_I219_LM4}, 123 {E1000_DEV_ID_PCH_SPT_I219_LM5}, 124 {E1000_DEV_ID_PCH_CNP_I219_LM6}, 125 {E1000_DEV_ID_PCH_CNP_I219_LM7}, 126 {E1000_DEV_ID_PCH_ICP_I219_LM8}, 127 {E1000_DEV_ID_PCH_ICP_I219_LM9}, 128 {E1000_DEV_ID_PCH_CMP_I219_LM10}, 129 {E1000_DEV_ID_PCH_CMP_I219_LM11}, 130 {E1000_DEV_ID_PCH_CMP_I219_LM12}, 131 {E1000_DEV_ID_PCH_TGP_I219_LM13}, 132 {E1000_DEV_ID_PCH_TGP_I219_LM14}, 133 {E1000_DEV_ID_PCH_TGP_I219_LM15}, 134 {0} 135 }; 136 137 static bool e1000e_check_me(u16 device_id) 138 { 139 struct e1000e_me_supported *id; 140 141 for (id = (struct e1000e_me_supported *)me_supported; 142 id->device_id; id++) 143 if (device_id == id->device_id) 144 return true; 145 146 return false; 147 } 148 149 /** 150 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 151 * @hw: pointer to the HW structure 152 * 153 * When updating the MAC CSR registers, the Manageability Engine (ME) could 154 * be accessing the registers at the same time. Normally, this is handled in 155 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 156 * accesses later than it should which could result in the register to have 157 * an incorrect value. Workaround this by checking the FWSM register which 158 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 159 * and try again a number of times. 160 **/ 161 static void __ew32_prepare(struct e1000_hw *hw) 162 { 163 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 164 165 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 166 udelay(50); 167 } 168 169 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 170 { 171 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 172 __ew32_prepare(hw); 173 174 writel(val, hw->hw_addr + reg); 175 } 176 177 /** 178 * e1000_regdump - register printout routine 179 * @hw: pointer to the HW structure 180 * @reginfo: pointer to the register info table 181 **/ 182 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 183 { 184 int n = 0; 185 char rname[16]; 186 u32 regs[8]; 187 188 switch (reginfo->ofs) { 189 case E1000_RXDCTL(0): 190 for (n = 0; n < 2; n++) 191 regs[n] = __er32(hw, E1000_RXDCTL(n)); 192 break; 193 case E1000_TXDCTL(0): 194 for (n = 0; n < 2; n++) 195 regs[n] = __er32(hw, E1000_TXDCTL(n)); 196 break; 197 case E1000_TARC(0): 198 for (n = 0; n < 2; n++) 199 regs[n] = __er32(hw, E1000_TARC(n)); 200 break; 201 default: 202 pr_info("%-15s %08x\n", 203 reginfo->name, __er32(hw, reginfo->ofs)); 204 return; 205 } 206 207 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 208 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 209 } 210 211 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 212 struct e1000_buffer *bi) 213 { 214 int i; 215 struct e1000_ps_page *ps_page; 216 217 for (i = 0; i < adapter->rx_ps_pages; i++) { 218 ps_page = &bi->ps_pages[i]; 219 220 if (ps_page->page) { 221 pr_info("packet dump for ps_page %d:\n", i); 222 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 223 16, 1, page_address(ps_page->page), 224 PAGE_SIZE, true); 225 } 226 } 227 } 228 229 /** 230 * e1000e_dump - Print registers, Tx-ring and Rx-ring 231 * @adapter: board private structure 232 **/ 233 static void e1000e_dump(struct e1000_adapter *adapter) 234 { 235 struct net_device *netdev = adapter->netdev; 236 struct e1000_hw *hw = &adapter->hw; 237 struct e1000_reg_info *reginfo; 238 struct e1000_ring *tx_ring = adapter->tx_ring; 239 struct e1000_tx_desc *tx_desc; 240 struct my_u0 { 241 __le64 a; 242 __le64 b; 243 } *u0; 244 struct e1000_buffer *buffer_info; 245 struct e1000_ring *rx_ring = adapter->rx_ring; 246 union e1000_rx_desc_packet_split *rx_desc_ps; 247 union e1000_rx_desc_extended *rx_desc; 248 struct my_u1 { 249 __le64 a; 250 __le64 b; 251 __le64 c; 252 __le64 d; 253 } *u1; 254 u32 staterr; 255 int i = 0; 256 257 if (!netif_msg_hw(adapter)) 258 return; 259 260 /* Print netdevice Info */ 261 if (netdev) { 262 dev_info(&adapter->pdev->dev, "Net device Info\n"); 263 pr_info("Device Name state trans_start\n"); 264 pr_info("%-15s %016lX %016lX\n", netdev->name, 265 netdev->state, dev_trans_start(netdev)); 266 } 267 268 /* Print Registers */ 269 dev_info(&adapter->pdev->dev, "Register Dump\n"); 270 pr_info(" Register Name Value\n"); 271 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 272 reginfo->name; reginfo++) { 273 e1000_regdump(hw, reginfo); 274 } 275 276 /* Print Tx Ring Summary */ 277 if (!netdev || !netif_running(netdev)) 278 return; 279 280 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 281 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 282 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 283 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 284 0, tx_ring->next_to_use, tx_ring->next_to_clean, 285 (unsigned long long)buffer_info->dma, 286 buffer_info->length, 287 buffer_info->next_to_watch, 288 (unsigned long long)buffer_info->time_stamp); 289 290 /* Print Tx Ring */ 291 if (!netif_msg_tx_done(adapter)) 292 goto rx_ring_summary; 293 294 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 295 296 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 297 * 298 * Legacy Transmit Descriptor 299 * +--------------------------------------------------------------+ 300 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 301 * +--------------------------------------------------------------+ 302 * 8 | Special | CSS | Status | CMD | CSO | Length | 303 * +--------------------------------------------------------------+ 304 * 63 48 47 36 35 32 31 24 23 16 15 0 305 * 306 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 307 * 63 48 47 40 39 32 31 16 15 8 7 0 308 * +----------------------------------------------------------------+ 309 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 310 * +----------------------------------------------------------------+ 311 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 312 * +----------------------------------------------------------------+ 313 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 314 * 315 * Extended Data Descriptor (DTYP=0x1) 316 * +----------------------------------------------------------------+ 317 * 0 | Buffer Address [63:0] | 318 * +----------------------------------------------------------------+ 319 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 320 * +----------------------------------------------------------------+ 321 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 322 */ 323 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 324 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 325 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 326 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 327 const char *next_desc; 328 tx_desc = E1000_TX_DESC(*tx_ring, i); 329 buffer_info = &tx_ring->buffer_info[i]; 330 u0 = (struct my_u0 *)tx_desc; 331 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 332 next_desc = " NTC/U"; 333 else if (i == tx_ring->next_to_use) 334 next_desc = " NTU"; 335 else if (i == tx_ring->next_to_clean) 336 next_desc = " NTC"; 337 else 338 next_desc = ""; 339 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 340 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 341 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 342 i, 343 (unsigned long long)le64_to_cpu(u0->a), 344 (unsigned long long)le64_to_cpu(u0->b), 345 (unsigned long long)buffer_info->dma, 346 buffer_info->length, buffer_info->next_to_watch, 347 (unsigned long long)buffer_info->time_stamp, 348 buffer_info->skb, next_desc); 349 350 if (netif_msg_pktdata(adapter) && buffer_info->skb) 351 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 352 16, 1, buffer_info->skb->data, 353 buffer_info->skb->len, true); 354 } 355 356 /* Print Rx Ring Summary */ 357 rx_ring_summary: 358 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 359 pr_info("Queue [NTU] [NTC]\n"); 360 pr_info(" %5d %5X %5X\n", 361 0, rx_ring->next_to_use, rx_ring->next_to_clean); 362 363 /* Print Rx Ring */ 364 if (!netif_msg_rx_status(adapter)) 365 return; 366 367 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 368 switch (adapter->rx_ps_pages) { 369 case 1: 370 case 2: 371 case 3: 372 /* [Extended] Packet Split Receive Descriptor Format 373 * 374 * +-----------------------------------------------------+ 375 * 0 | Buffer Address 0 [63:0] | 376 * +-----------------------------------------------------+ 377 * 8 | Buffer Address 1 [63:0] | 378 * +-----------------------------------------------------+ 379 * 16 | Buffer Address 2 [63:0] | 380 * +-----------------------------------------------------+ 381 * 24 | Buffer Address 3 [63:0] | 382 * +-----------------------------------------------------+ 383 */ 384 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 385 /* [Extended] Receive Descriptor (Write-Back) Format 386 * 387 * 63 48 47 32 31 13 12 8 7 4 3 0 388 * +------------------------------------------------------+ 389 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 390 * | Checksum | Ident | | Queue | | Type | 391 * +------------------------------------------------------+ 392 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 393 * +------------------------------------------------------+ 394 * 63 48 47 32 31 20 19 0 395 */ 396 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 397 for (i = 0; i < rx_ring->count; i++) { 398 const char *next_desc; 399 buffer_info = &rx_ring->buffer_info[i]; 400 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 401 u1 = (struct my_u1 *)rx_desc_ps; 402 staterr = 403 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 404 405 if (i == rx_ring->next_to_use) 406 next_desc = " NTU"; 407 else if (i == rx_ring->next_to_clean) 408 next_desc = " NTC"; 409 else 410 next_desc = ""; 411 412 if (staterr & E1000_RXD_STAT_DD) { 413 /* Descriptor Done */ 414 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 415 "RWB", i, 416 (unsigned long long)le64_to_cpu(u1->a), 417 (unsigned long long)le64_to_cpu(u1->b), 418 (unsigned long long)le64_to_cpu(u1->c), 419 (unsigned long long)le64_to_cpu(u1->d), 420 buffer_info->skb, next_desc); 421 } else { 422 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 423 "R ", i, 424 (unsigned long long)le64_to_cpu(u1->a), 425 (unsigned long long)le64_to_cpu(u1->b), 426 (unsigned long long)le64_to_cpu(u1->c), 427 (unsigned long long)le64_to_cpu(u1->d), 428 (unsigned long long)buffer_info->dma, 429 buffer_info->skb, next_desc); 430 431 if (netif_msg_pktdata(adapter)) 432 e1000e_dump_ps_pages(adapter, 433 buffer_info); 434 } 435 } 436 break; 437 default: 438 case 0: 439 /* Extended Receive Descriptor (Read) Format 440 * 441 * +-----------------------------------------------------+ 442 * 0 | Buffer Address [63:0] | 443 * +-----------------------------------------------------+ 444 * 8 | Reserved | 445 * +-----------------------------------------------------+ 446 */ 447 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 448 /* Extended Receive Descriptor (Write-Back) Format 449 * 450 * 63 48 47 32 31 24 23 4 3 0 451 * +------------------------------------------------------+ 452 * | RSS Hash | | | | 453 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 454 * | Packet | IP | | | Type | 455 * | Checksum | Ident | | | | 456 * +------------------------------------------------------+ 457 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 458 * +------------------------------------------------------+ 459 * 63 48 47 32 31 20 19 0 460 */ 461 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 462 463 for (i = 0; i < rx_ring->count; i++) { 464 const char *next_desc; 465 466 buffer_info = &rx_ring->buffer_info[i]; 467 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 468 u1 = (struct my_u1 *)rx_desc; 469 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 470 471 if (i == rx_ring->next_to_use) 472 next_desc = " NTU"; 473 else if (i == rx_ring->next_to_clean) 474 next_desc = " NTC"; 475 else 476 next_desc = ""; 477 478 if (staterr & E1000_RXD_STAT_DD) { 479 /* Descriptor Done */ 480 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 481 "RWB", i, 482 (unsigned long long)le64_to_cpu(u1->a), 483 (unsigned long long)le64_to_cpu(u1->b), 484 buffer_info->skb, next_desc); 485 } else { 486 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 487 "R ", i, 488 (unsigned long long)le64_to_cpu(u1->a), 489 (unsigned long long)le64_to_cpu(u1->b), 490 (unsigned long long)buffer_info->dma, 491 buffer_info->skb, next_desc); 492 493 if (netif_msg_pktdata(adapter) && 494 buffer_info->skb) 495 print_hex_dump(KERN_INFO, "", 496 DUMP_PREFIX_ADDRESS, 16, 497 1, 498 buffer_info->skb->data, 499 adapter->rx_buffer_len, 500 true); 501 } 502 } 503 } 504 } 505 506 /** 507 * e1000_desc_unused - calculate if we have unused descriptors 508 **/ 509 static int e1000_desc_unused(struct e1000_ring *ring) 510 { 511 if (ring->next_to_clean > ring->next_to_use) 512 return ring->next_to_clean - ring->next_to_use - 1; 513 514 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 515 } 516 517 /** 518 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 519 * @adapter: board private structure 520 * @hwtstamps: time stamp structure to update 521 * @systim: unsigned 64bit system time value. 522 * 523 * Convert the system time value stored in the RX/TXSTMP registers into a 524 * hwtstamp which can be used by the upper level time stamping functions. 525 * 526 * The 'systim_lock' spinlock is used to protect the consistency of the 527 * system time value. This is needed because reading the 64 bit time 528 * value involves reading two 32 bit registers. The first read latches the 529 * value. 530 **/ 531 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 532 struct skb_shared_hwtstamps *hwtstamps, 533 u64 systim) 534 { 535 u64 ns; 536 unsigned long flags; 537 538 spin_lock_irqsave(&adapter->systim_lock, flags); 539 ns = timecounter_cyc2time(&adapter->tc, systim); 540 spin_unlock_irqrestore(&adapter->systim_lock, flags); 541 542 memset(hwtstamps, 0, sizeof(*hwtstamps)); 543 hwtstamps->hwtstamp = ns_to_ktime(ns); 544 } 545 546 /** 547 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 548 * @adapter: board private structure 549 * @status: descriptor extended error and status field 550 * @skb: particular skb to include time stamp 551 * 552 * If the time stamp is valid, convert it into the timecounter ns value 553 * and store that result into the shhwtstamps structure which is passed 554 * up the network stack. 555 **/ 556 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 557 struct sk_buff *skb) 558 { 559 struct e1000_hw *hw = &adapter->hw; 560 u64 rxstmp; 561 562 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 563 !(status & E1000_RXDEXT_STATERR_TST) || 564 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 565 return; 566 567 /* The Rx time stamp registers contain the time stamp. No other 568 * received packet will be time stamped until the Rx time stamp 569 * registers are read. Because only one packet can be time stamped 570 * at a time, the register values must belong to this packet and 571 * therefore none of the other additional attributes need to be 572 * compared. 573 */ 574 rxstmp = (u64)er32(RXSTMPL); 575 rxstmp |= (u64)er32(RXSTMPH) << 32; 576 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 577 578 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 579 } 580 581 /** 582 * e1000_receive_skb - helper function to handle Rx indications 583 * @adapter: board private structure 584 * @staterr: descriptor extended error and status field as written by hardware 585 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 586 * @skb: pointer to sk_buff to be indicated to stack 587 **/ 588 static void e1000_receive_skb(struct e1000_adapter *adapter, 589 struct net_device *netdev, struct sk_buff *skb, 590 u32 staterr, __le16 vlan) 591 { 592 u16 tag = le16_to_cpu(vlan); 593 594 e1000e_rx_hwtstamp(adapter, staterr, skb); 595 596 skb->protocol = eth_type_trans(skb, netdev); 597 598 if (staterr & E1000_RXD_STAT_VP) 599 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 600 601 napi_gro_receive(&adapter->napi, skb); 602 } 603 604 /** 605 * e1000_rx_checksum - Receive Checksum Offload 606 * @adapter: board private structure 607 * @status_err: receive descriptor status and error fields 608 * @csum: receive descriptor csum field 609 * @sk_buff: socket buffer with received data 610 **/ 611 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 612 struct sk_buff *skb) 613 { 614 u16 status = (u16)status_err; 615 u8 errors = (u8)(status_err >> 24); 616 617 skb_checksum_none_assert(skb); 618 619 /* Rx checksum disabled */ 620 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 621 return; 622 623 /* Ignore Checksum bit is set */ 624 if (status & E1000_RXD_STAT_IXSM) 625 return; 626 627 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 628 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 629 /* let the stack verify checksum errors */ 630 adapter->hw_csum_err++; 631 return; 632 } 633 634 /* TCP/UDP Checksum has not been calculated */ 635 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 636 return; 637 638 /* It must be a TCP or UDP packet with a valid checksum */ 639 skb->ip_summed = CHECKSUM_UNNECESSARY; 640 adapter->hw_csum_good++; 641 } 642 643 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 644 { 645 struct e1000_adapter *adapter = rx_ring->adapter; 646 struct e1000_hw *hw = &adapter->hw; 647 648 __ew32_prepare(hw); 649 writel(i, rx_ring->tail); 650 651 if (unlikely(i != readl(rx_ring->tail))) { 652 u32 rctl = er32(RCTL); 653 654 ew32(RCTL, rctl & ~E1000_RCTL_EN); 655 e_err("ME firmware caused invalid RDT - resetting\n"); 656 schedule_work(&adapter->reset_task); 657 } 658 } 659 660 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 661 { 662 struct e1000_adapter *adapter = tx_ring->adapter; 663 struct e1000_hw *hw = &adapter->hw; 664 665 __ew32_prepare(hw); 666 writel(i, tx_ring->tail); 667 668 if (unlikely(i != readl(tx_ring->tail))) { 669 u32 tctl = er32(TCTL); 670 671 ew32(TCTL, tctl & ~E1000_TCTL_EN); 672 e_err("ME firmware caused invalid TDT - resetting\n"); 673 schedule_work(&adapter->reset_task); 674 } 675 } 676 677 /** 678 * e1000_alloc_rx_buffers - Replace used receive buffers 679 * @rx_ring: Rx descriptor ring 680 **/ 681 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 682 int cleaned_count, gfp_t gfp) 683 { 684 struct e1000_adapter *adapter = rx_ring->adapter; 685 struct net_device *netdev = adapter->netdev; 686 struct pci_dev *pdev = adapter->pdev; 687 union e1000_rx_desc_extended *rx_desc; 688 struct e1000_buffer *buffer_info; 689 struct sk_buff *skb; 690 unsigned int i; 691 unsigned int bufsz = adapter->rx_buffer_len; 692 693 i = rx_ring->next_to_use; 694 buffer_info = &rx_ring->buffer_info[i]; 695 696 while (cleaned_count--) { 697 skb = buffer_info->skb; 698 if (skb) { 699 skb_trim(skb, 0); 700 goto map_skb; 701 } 702 703 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 704 if (!skb) { 705 /* Better luck next round */ 706 adapter->alloc_rx_buff_failed++; 707 break; 708 } 709 710 buffer_info->skb = skb; 711 map_skb: 712 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 713 adapter->rx_buffer_len, 714 DMA_FROM_DEVICE); 715 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 716 dev_err(&pdev->dev, "Rx DMA map failed\n"); 717 adapter->rx_dma_failed++; 718 break; 719 } 720 721 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 722 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 723 724 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 725 /* Force memory writes to complete before letting h/w 726 * know there are new descriptors to fetch. (Only 727 * applicable for weak-ordered memory model archs, 728 * such as IA-64). 729 */ 730 wmb(); 731 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 732 e1000e_update_rdt_wa(rx_ring, i); 733 else 734 writel(i, rx_ring->tail); 735 } 736 i++; 737 if (i == rx_ring->count) 738 i = 0; 739 buffer_info = &rx_ring->buffer_info[i]; 740 } 741 742 rx_ring->next_to_use = i; 743 } 744 745 /** 746 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 747 * @rx_ring: Rx descriptor ring 748 **/ 749 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 750 int cleaned_count, gfp_t gfp) 751 { 752 struct e1000_adapter *adapter = rx_ring->adapter; 753 struct net_device *netdev = adapter->netdev; 754 struct pci_dev *pdev = adapter->pdev; 755 union e1000_rx_desc_packet_split *rx_desc; 756 struct e1000_buffer *buffer_info; 757 struct e1000_ps_page *ps_page; 758 struct sk_buff *skb; 759 unsigned int i, j; 760 761 i = rx_ring->next_to_use; 762 buffer_info = &rx_ring->buffer_info[i]; 763 764 while (cleaned_count--) { 765 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 766 767 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 768 ps_page = &buffer_info->ps_pages[j]; 769 if (j >= adapter->rx_ps_pages) { 770 /* all unused desc entries get hw null ptr */ 771 rx_desc->read.buffer_addr[j + 1] = 772 ~cpu_to_le64(0); 773 continue; 774 } 775 if (!ps_page->page) { 776 ps_page->page = alloc_page(gfp); 777 if (!ps_page->page) { 778 adapter->alloc_rx_buff_failed++; 779 goto no_buffers; 780 } 781 ps_page->dma = dma_map_page(&pdev->dev, 782 ps_page->page, 783 0, PAGE_SIZE, 784 DMA_FROM_DEVICE); 785 if (dma_mapping_error(&pdev->dev, 786 ps_page->dma)) { 787 dev_err(&adapter->pdev->dev, 788 "Rx DMA page map failed\n"); 789 adapter->rx_dma_failed++; 790 goto no_buffers; 791 } 792 } 793 /* Refresh the desc even if buffer_addrs 794 * didn't change because each write-back 795 * erases this info. 796 */ 797 rx_desc->read.buffer_addr[j + 1] = 798 cpu_to_le64(ps_page->dma); 799 } 800 801 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 802 gfp); 803 804 if (!skb) { 805 adapter->alloc_rx_buff_failed++; 806 break; 807 } 808 809 buffer_info->skb = skb; 810 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 811 adapter->rx_ps_bsize0, 812 DMA_FROM_DEVICE); 813 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 814 dev_err(&pdev->dev, "Rx DMA map failed\n"); 815 adapter->rx_dma_failed++; 816 /* cleanup skb */ 817 dev_kfree_skb_any(skb); 818 buffer_info->skb = NULL; 819 break; 820 } 821 822 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 823 824 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 825 /* Force memory writes to complete before letting h/w 826 * know there are new descriptors to fetch. (Only 827 * applicable for weak-ordered memory model archs, 828 * such as IA-64). 829 */ 830 wmb(); 831 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 832 e1000e_update_rdt_wa(rx_ring, i << 1); 833 else 834 writel(i << 1, rx_ring->tail); 835 } 836 837 i++; 838 if (i == rx_ring->count) 839 i = 0; 840 buffer_info = &rx_ring->buffer_info[i]; 841 } 842 843 no_buffers: 844 rx_ring->next_to_use = i; 845 } 846 847 /** 848 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 849 * @rx_ring: Rx descriptor ring 850 * @cleaned_count: number of buffers to allocate this pass 851 **/ 852 853 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 854 int cleaned_count, gfp_t gfp) 855 { 856 struct e1000_adapter *adapter = rx_ring->adapter; 857 struct net_device *netdev = adapter->netdev; 858 struct pci_dev *pdev = adapter->pdev; 859 union e1000_rx_desc_extended *rx_desc; 860 struct e1000_buffer *buffer_info; 861 struct sk_buff *skb; 862 unsigned int i; 863 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 864 865 i = rx_ring->next_to_use; 866 buffer_info = &rx_ring->buffer_info[i]; 867 868 while (cleaned_count--) { 869 skb = buffer_info->skb; 870 if (skb) { 871 skb_trim(skb, 0); 872 goto check_page; 873 } 874 875 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 876 if (unlikely(!skb)) { 877 /* Better luck next round */ 878 adapter->alloc_rx_buff_failed++; 879 break; 880 } 881 882 buffer_info->skb = skb; 883 check_page: 884 /* allocate a new page if necessary */ 885 if (!buffer_info->page) { 886 buffer_info->page = alloc_page(gfp); 887 if (unlikely(!buffer_info->page)) { 888 adapter->alloc_rx_buff_failed++; 889 break; 890 } 891 } 892 893 if (!buffer_info->dma) { 894 buffer_info->dma = dma_map_page(&pdev->dev, 895 buffer_info->page, 0, 896 PAGE_SIZE, 897 DMA_FROM_DEVICE); 898 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 899 adapter->alloc_rx_buff_failed++; 900 break; 901 } 902 } 903 904 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 905 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 906 907 if (unlikely(++i == rx_ring->count)) 908 i = 0; 909 buffer_info = &rx_ring->buffer_info[i]; 910 } 911 912 if (likely(rx_ring->next_to_use != i)) { 913 rx_ring->next_to_use = i; 914 if (unlikely(i-- == 0)) 915 i = (rx_ring->count - 1); 916 917 /* Force memory writes to complete before letting h/w 918 * know there are new descriptors to fetch. (Only 919 * applicable for weak-ordered memory model archs, 920 * such as IA-64). 921 */ 922 wmb(); 923 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 924 e1000e_update_rdt_wa(rx_ring, i); 925 else 926 writel(i, rx_ring->tail); 927 } 928 } 929 930 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 931 struct sk_buff *skb) 932 { 933 if (netdev->features & NETIF_F_RXHASH) 934 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 935 } 936 937 /** 938 * e1000_clean_rx_irq - Send received data up the network stack 939 * @rx_ring: Rx descriptor ring 940 * 941 * the return value indicates whether actual cleaning was done, there 942 * is no guarantee that everything was cleaned 943 **/ 944 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 945 int work_to_do) 946 { 947 struct e1000_adapter *adapter = rx_ring->adapter; 948 struct net_device *netdev = adapter->netdev; 949 struct pci_dev *pdev = adapter->pdev; 950 struct e1000_hw *hw = &adapter->hw; 951 union e1000_rx_desc_extended *rx_desc, *next_rxd; 952 struct e1000_buffer *buffer_info, *next_buffer; 953 u32 length, staterr; 954 unsigned int i; 955 int cleaned_count = 0; 956 bool cleaned = false; 957 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 958 959 i = rx_ring->next_to_clean; 960 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 961 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 962 buffer_info = &rx_ring->buffer_info[i]; 963 964 while (staterr & E1000_RXD_STAT_DD) { 965 struct sk_buff *skb; 966 967 if (*work_done >= work_to_do) 968 break; 969 (*work_done)++; 970 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 971 972 skb = buffer_info->skb; 973 buffer_info->skb = NULL; 974 975 prefetch(skb->data - NET_IP_ALIGN); 976 977 i++; 978 if (i == rx_ring->count) 979 i = 0; 980 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 981 prefetch(next_rxd); 982 983 next_buffer = &rx_ring->buffer_info[i]; 984 985 cleaned = true; 986 cleaned_count++; 987 dma_unmap_single(&pdev->dev, buffer_info->dma, 988 adapter->rx_buffer_len, DMA_FROM_DEVICE); 989 buffer_info->dma = 0; 990 991 length = le16_to_cpu(rx_desc->wb.upper.length); 992 993 /* !EOP means multiple descriptors were used to store a single 994 * packet, if that's the case we need to toss it. In fact, we 995 * need to toss every packet with the EOP bit clear and the 996 * next frame that _does_ have the EOP bit set, as it is by 997 * definition only a frame fragment 998 */ 999 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 1000 adapter->flags2 |= FLAG2_IS_DISCARDING; 1001 1002 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1003 /* All receives must fit into a single buffer */ 1004 e_dbg("Receive packet consumed multiple buffers\n"); 1005 /* recycle */ 1006 buffer_info->skb = skb; 1007 if (staterr & E1000_RXD_STAT_EOP) 1008 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1009 goto next_desc; 1010 } 1011 1012 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1013 !(netdev->features & NETIF_F_RXALL))) { 1014 /* recycle */ 1015 buffer_info->skb = skb; 1016 goto next_desc; 1017 } 1018 1019 /* adjust length to remove Ethernet CRC */ 1020 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1021 /* If configured to store CRC, don't subtract FCS, 1022 * but keep the FCS bytes out of the total_rx_bytes 1023 * counter 1024 */ 1025 if (netdev->features & NETIF_F_RXFCS) 1026 total_rx_bytes -= 4; 1027 else 1028 length -= 4; 1029 } 1030 1031 total_rx_bytes += length; 1032 total_rx_packets++; 1033 1034 /* code added for copybreak, this should improve 1035 * performance for small packets with large amounts 1036 * of reassembly being done in the stack 1037 */ 1038 if (length < copybreak) { 1039 struct sk_buff *new_skb = 1040 napi_alloc_skb(&adapter->napi, length); 1041 if (new_skb) { 1042 skb_copy_to_linear_data_offset(new_skb, 1043 -NET_IP_ALIGN, 1044 (skb->data - 1045 NET_IP_ALIGN), 1046 (length + 1047 NET_IP_ALIGN)); 1048 /* save the skb in buffer_info as good */ 1049 buffer_info->skb = skb; 1050 skb = new_skb; 1051 } 1052 /* else just continue with the old one */ 1053 } 1054 /* end copybreak code */ 1055 skb_put(skb, length); 1056 1057 /* Receive Checksum Offload */ 1058 e1000_rx_checksum(adapter, staterr, skb); 1059 1060 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1061 1062 e1000_receive_skb(adapter, netdev, skb, staterr, 1063 rx_desc->wb.upper.vlan); 1064 1065 next_desc: 1066 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1067 1068 /* return some buffers to hardware, one at a time is too slow */ 1069 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1070 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1071 GFP_ATOMIC); 1072 cleaned_count = 0; 1073 } 1074 1075 /* use prefetched values */ 1076 rx_desc = next_rxd; 1077 buffer_info = next_buffer; 1078 1079 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1080 } 1081 rx_ring->next_to_clean = i; 1082 1083 cleaned_count = e1000_desc_unused(rx_ring); 1084 if (cleaned_count) 1085 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1086 1087 adapter->total_rx_bytes += total_rx_bytes; 1088 adapter->total_rx_packets += total_rx_packets; 1089 return cleaned; 1090 } 1091 1092 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1093 struct e1000_buffer *buffer_info, 1094 bool drop) 1095 { 1096 struct e1000_adapter *adapter = tx_ring->adapter; 1097 1098 if (buffer_info->dma) { 1099 if (buffer_info->mapped_as_page) 1100 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1101 buffer_info->length, DMA_TO_DEVICE); 1102 else 1103 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1104 buffer_info->length, DMA_TO_DEVICE); 1105 buffer_info->dma = 0; 1106 } 1107 if (buffer_info->skb) { 1108 if (drop) 1109 dev_kfree_skb_any(buffer_info->skb); 1110 else 1111 dev_consume_skb_any(buffer_info->skb); 1112 buffer_info->skb = NULL; 1113 } 1114 buffer_info->time_stamp = 0; 1115 } 1116 1117 static void e1000_print_hw_hang(struct work_struct *work) 1118 { 1119 struct e1000_adapter *adapter = container_of(work, 1120 struct e1000_adapter, 1121 print_hang_task); 1122 struct net_device *netdev = adapter->netdev; 1123 struct e1000_ring *tx_ring = adapter->tx_ring; 1124 unsigned int i = tx_ring->next_to_clean; 1125 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1126 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1127 struct e1000_hw *hw = &adapter->hw; 1128 u16 phy_status, phy_1000t_status, phy_ext_status; 1129 u16 pci_status; 1130 1131 if (test_bit(__E1000_DOWN, &adapter->state)) 1132 return; 1133 1134 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1135 /* May be block on write-back, flush and detect again 1136 * flush pending descriptor writebacks to memory 1137 */ 1138 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1139 /* execute the writes immediately */ 1140 e1e_flush(); 1141 /* Due to rare timing issues, write to TIDV again to ensure 1142 * the write is successful 1143 */ 1144 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1145 /* execute the writes immediately */ 1146 e1e_flush(); 1147 adapter->tx_hang_recheck = true; 1148 return; 1149 } 1150 adapter->tx_hang_recheck = false; 1151 1152 if (er32(TDH(0)) == er32(TDT(0))) { 1153 e_dbg("false hang detected, ignoring\n"); 1154 return; 1155 } 1156 1157 /* Real hang detected */ 1158 netif_stop_queue(netdev); 1159 1160 e1e_rphy(hw, MII_BMSR, &phy_status); 1161 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1162 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1163 1164 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1165 1166 /* detected Hardware unit hang */ 1167 e_err("Detected Hardware Unit Hang:\n" 1168 " TDH <%x>\n" 1169 " TDT <%x>\n" 1170 " next_to_use <%x>\n" 1171 " next_to_clean <%x>\n" 1172 "buffer_info[next_to_clean]:\n" 1173 " time_stamp <%lx>\n" 1174 " next_to_watch <%x>\n" 1175 " jiffies <%lx>\n" 1176 " next_to_watch.status <%x>\n" 1177 "MAC Status <%x>\n" 1178 "PHY Status <%x>\n" 1179 "PHY 1000BASE-T Status <%x>\n" 1180 "PHY Extended Status <%x>\n" 1181 "PCI Status <%x>\n", 1182 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1183 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1184 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1185 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1186 1187 e1000e_dump(adapter); 1188 1189 /* Suggest workaround for known h/w issue */ 1190 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1191 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1192 } 1193 1194 /** 1195 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1196 * @work: pointer to work struct 1197 * 1198 * This work function polls the TSYNCTXCTL valid bit to determine when a 1199 * timestamp has been taken for the current stored skb. The timestamp must 1200 * be for this skb because only one such packet is allowed in the queue. 1201 */ 1202 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1203 { 1204 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1205 tx_hwtstamp_work); 1206 struct e1000_hw *hw = &adapter->hw; 1207 1208 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1209 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1210 struct skb_shared_hwtstamps shhwtstamps; 1211 u64 txstmp; 1212 1213 txstmp = er32(TXSTMPL); 1214 txstmp |= (u64)er32(TXSTMPH) << 32; 1215 1216 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1217 1218 /* Clear the global tx_hwtstamp_skb pointer and force writes 1219 * prior to notifying the stack of a Tx timestamp. 1220 */ 1221 adapter->tx_hwtstamp_skb = NULL; 1222 wmb(); /* force write prior to skb_tstamp_tx */ 1223 1224 skb_tstamp_tx(skb, &shhwtstamps); 1225 dev_consume_skb_any(skb); 1226 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1227 + adapter->tx_timeout_factor * HZ)) { 1228 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1229 adapter->tx_hwtstamp_skb = NULL; 1230 adapter->tx_hwtstamp_timeouts++; 1231 e_warn("clearing Tx timestamp hang\n"); 1232 } else { 1233 /* reschedule to check later */ 1234 schedule_work(&adapter->tx_hwtstamp_work); 1235 } 1236 } 1237 1238 /** 1239 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1240 * @tx_ring: Tx descriptor ring 1241 * 1242 * the return value indicates whether actual cleaning was done, there 1243 * is no guarantee that everything was cleaned 1244 **/ 1245 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1246 { 1247 struct e1000_adapter *adapter = tx_ring->adapter; 1248 struct net_device *netdev = adapter->netdev; 1249 struct e1000_hw *hw = &adapter->hw; 1250 struct e1000_tx_desc *tx_desc, *eop_desc; 1251 struct e1000_buffer *buffer_info; 1252 unsigned int i, eop; 1253 unsigned int count = 0; 1254 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1255 unsigned int bytes_compl = 0, pkts_compl = 0; 1256 1257 i = tx_ring->next_to_clean; 1258 eop = tx_ring->buffer_info[i].next_to_watch; 1259 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1260 1261 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1262 (count < tx_ring->count)) { 1263 bool cleaned = false; 1264 1265 dma_rmb(); /* read buffer_info after eop_desc */ 1266 for (; !cleaned; count++) { 1267 tx_desc = E1000_TX_DESC(*tx_ring, i); 1268 buffer_info = &tx_ring->buffer_info[i]; 1269 cleaned = (i == eop); 1270 1271 if (cleaned) { 1272 total_tx_packets += buffer_info->segs; 1273 total_tx_bytes += buffer_info->bytecount; 1274 if (buffer_info->skb) { 1275 bytes_compl += buffer_info->skb->len; 1276 pkts_compl++; 1277 } 1278 } 1279 1280 e1000_put_txbuf(tx_ring, buffer_info, false); 1281 tx_desc->upper.data = 0; 1282 1283 i++; 1284 if (i == tx_ring->count) 1285 i = 0; 1286 } 1287 1288 if (i == tx_ring->next_to_use) 1289 break; 1290 eop = tx_ring->buffer_info[i].next_to_watch; 1291 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1292 } 1293 1294 tx_ring->next_to_clean = i; 1295 1296 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1297 1298 #define TX_WAKE_THRESHOLD 32 1299 if (count && netif_carrier_ok(netdev) && 1300 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1301 /* Make sure that anybody stopping the queue after this 1302 * sees the new next_to_clean. 1303 */ 1304 smp_mb(); 1305 1306 if (netif_queue_stopped(netdev) && 1307 !(test_bit(__E1000_DOWN, &adapter->state))) { 1308 netif_wake_queue(netdev); 1309 ++adapter->restart_queue; 1310 } 1311 } 1312 1313 if (adapter->detect_tx_hung) { 1314 /* Detect a transmit hang in hardware, this serializes the 1315 * check with the clearing of time_stamp and movement of i 1316 */ 1317 adapter->detect_tx_hung = false; 1318 if (tx_ring->buffer_info[i].time_stamp && 1319 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1320 + (adapter->tx_timeout_factor * HZ)) && 1321 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1322 schedule_work(&adapter->print_hang_task); 1323 else 1324 adapter->tx_hang_recheck = false; 1325 } 1326 adapter->total_tx_bytes += total_tx_bytes; 1327 adapter->total_tx_packets += total_tx_packets; 1328 return count < tx_ring->count; 1329 } 1330 1331 /** 1332 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1333 * @rx_ring: Rx descriptor ring 1334 * 1335 * the return value indicates whether actual cleaning was done, there 1336 * is no guarantee that everything was cleaned 1337 **/ 1338 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1339 int work_to_do) 1340 { 1341 struct e1000_adapter *adapter = rx_ring->adapter; 1342 struct e1000_hw *hw = &adapter->hw; 1343 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1344 struct net_device *netdev = adapter->netdev; 1345 struct pci_dev *pdev = adapter->pdev; 1346 struct e1000_buffer *buffer_info, *next_buffer; 1347 struct e1000_ps_page *ps_page; 1348 struct sk_buff *skb; 1349 unsigned int i, j; 1350 u32 length, staterr; 1351 int cleaned_count = 0; 1352 bool cleaned = false; 1353 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1354 1355 i = rx_ring->next_to_clean; 1356 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1357 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1358 buffer_info = &rx_ring->buffer_info[i]; 1359 1360 while (staterr & E1000_RXD_STAT_DD) { 1361 if (*work_done >= work_to_do) 1362 break; 1363 (*work_done)++; 1364 skb = buffer_info->skb; 1365 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1366 1367 /* in the packet split case this is header only */ 1368 prefetch(skb->data - NET_IP_ALIGN); 1369 1370 i++; 1371 if (i == rx_ring->count) 1372 i = 0; 1373 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1374 prefetch(next_rxd); 1375 1376 next_buffer = &rx_ring->buffer_info[i]; 1377 1378 cleaned = true; 1379 cleaned_count++; 1380 dma_unmap_single(&pdev->dev, buffer_info->dma, 1381 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1382 buffer_info->dma = 0; 1383 1384 /* see !EOP comment in other Rx routine */ 1385 if (!(staterr & E1000_RXD_STAT_EOP)) 1386 adapter->flags2 |= FLAG2_IS_DISCARDING; 1387 1388 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1389 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1390 dev_kfree_skb_irq(skb); 1391 if (staterr & E1000_RXD_STAT_EOP) 1392 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1393 goto next_desc; 1394 } 1395 1396 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1397 !(netdev->features & NETIF_F_RXALL))) { 1398 dev_kfree_skb_irq(skb); 1399 goto next_desc; 1400 } 1401 1402 length = le16_to_cpu(rx_desc->wb.middle.length0); 1403 1404 if (!length) { 1405 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1406 dev_kfree_skb_irq(skb); 1407 goto next_desc; 1408 } 1409 1410 /* Good Receive */ 1411 skb_put(skb, length); 1412 1413 { 1414 /* this looks ugly, but it seems compiler issues make 1415 * it more efficient than reusing j 1416 */ 1417 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1418 1419 /* page alloc/put takes too long and effects small 1420 * packet throughput, so unsplit small packets and 1421 * save the alloc/put only valid in softirq (napi) 1422 * context to call kmap_* 1423 */ 1424 if (l1 && (l1 <= copybreak) && 1425 ((length + l1) <= adapter->rx_ps_bsize0)) { 1426 u8 *vaddr; 1427 1428 ps_page = &buffer_info->ps_pages[0]; 1429 1430 /* there is no documentation about how to call 1431 * kmap_atomic, so we can't hold the mapping 1432 * very long 1433 */ 1434 dma_sync_single_for_cpu(&pdev->dev, 1435 ps_page->dma, 1436 PAGE_SIZE, 1437 DMA_FROM_DEVICE); 1438 vaddr = kmap_atomic(ps_page->page); 1439 memcpy(skb_tail_pointer(skb), vaddr, l1); 1440 kunmap_atomic(vaddr); 1441 dma_sync_single_for_device(&pdev->dev, 1442 ps_page->dma, 1443 PAGE_SIZE, 1444 DMA_FROM_DEVICE); 1445 1446 /* remove the CRC */ 1447 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1448 if (!(netdev->features & NETIF_F_RXFCS)) 1449 l1 -= 4; 1450 } 1451 1452 skb_put(skb, l1); 1453 goto copydone; 1454 } /* if */ 1455 } 1456 1457 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1458 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1459 if (!length) 1460 break; 1461 1462 ps_page = &buffer_info->ps_pages[j]; 1463 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1464 DMA_FROM_DEVICE); 1465 ps_page->dma = 0; 1466 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1467 ps_page->page = NULL; 1468 skb->len += length; 1469 skb->data_len += length; 1470 skb->truesize += PAGE_SIZE; 1471 } 1472 1473 /* strip the ethernet crc, problem is we're using pages now so 1474 * this whole operation can get a little cpu intensive 1475 */ 1476 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1477 if (!(netdev->features & NETIF_F_RXFCS)) 1478 pskb_trim(skb, skb->len - 4); 1479 } 1480 1481 copydone: 1482 total_rx_bytes += skb->len; 1483 total_rx_packets++; 1484 1485 e1000_rx_checksum(adapter, staterr, skb); 1486 1487 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1488 1489 if (rx_desc->wb.upper.header_status & 1490 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1491 adapter->rx_hdr_split++; 1492 1493 e1000_receive_skb(adapter, netdev, skb, staterr, 1494 rx_desc->wb.middle.vlan); 1495 1496 next_desc: 1497 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1498 buffer_info->skb = NULL; 1499 1500 /* return some buffers to hardware, one at a time is too slow */ 1501 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1502 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1503 GFP_ATOMIC); 1504 cleaned_count = 0; 1505 } 1506 1507 /* use prefetched values */ 1508 rx_desc = next_rxd; 1509 buffer_info = next_buffer; 1510 1511 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1512 } 1513 rx_ring->next_to_clean = i; 1514 1515 cleaned_count = e1000_desc_unused(rx_ring); 1516 if (cleaned_count) 1517 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1518 1519 adapter->total_rx_bytes += total_rx_bytes; 1520 adapter->total_rx_packets += total_rx_packets; 1521 return cleaned; 1522 } 1523 1524 /** 1525 * e1000_consume_page - helper function 1526 **/ 1527 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1528 u16 length) 1529 { 1530 bi->page = NULL; 1531 skb->len += length; 1532 skb->data_len += length; 1533 skb->truesize += PAGE_SIZE; 1534 } 1535 1536 /** 1537 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1538 * @adapter: board private structure 1539 * 1540 * the return value indicates whether actual cleaning was done, there 1541 * is no guarantee that everything was cleaned 1542 **/ 1543 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1544 int work_to_do) 1545 { 1546 struct e1000_adapter *adapter = rx_ring->adapter; 1547 struct net_device *netdev = adapter->netdev; 1548 struct pci_dev *pdev = adapter->pdev; 1549 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1550 struct e1000_buffer *buffer_info, *next_buffer; 1551 u32 length, staterr; 1552 unsigned int i; 1553 int cleaned_count = 0; 1554 bool cleaned = false; 1555 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1556 struct skb_shared_info *shinfo; 1557 1558 i = rx_ring->next_to_clean; 1559 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1561 buffer_info = &rx_ring->buffer_info[i]; 1562 1563 while (staterr & E1000_RXD_STAT_DD) { 1564 struct sk_buff *skb; 1565 1566 if (*work_done >= work_to_do) 1567 break; 1568 (*work_done)++; 1569 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1570 1571 skb = buffer_info->skb; 1572 buffer_info->skb = NULL; 1573 1574 ++i; 1575 if (i == rx_ring->count) 1576 i = 0; 1577 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1578 prefetch(next_rxd); 1579 1580 next_buffer = &rx_ring->buffer_info[i]; 1581 1582 cleaned = true; 1583 cleaned_count++; 1584 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1585 DMA_FROM_DEVICE); 1586 buffer_info->dma = 0; 1587 1588 length = le16_to_cpu(rx_desc->wb.upper.length); 1589 1590 /* errors is only valid for DD + EOP descriptors */ 1591 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1592 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1593 !(netdev->features & NETIF_F_RXALL)))) { 1594 /* recycle both page and skb */ 1595 buffer_info->skb = skb; 1596 /* an error means any chain goes out the window too */ 1597 if (rx_ring->rx_skb_top) 1598 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1599 rx_ring->rx_skb_top = NULL; 1600 goto next_desc; 1601 } 1602 #define rxtop (rx_ring->rx_skb_top) 1603 if (!(staterr & E1000_RXD_STAT_EOP)) { 1604 /* this descriptor is only the beginning (or middle) */ 1605 if (!rxtop) { 1606 /* this is the beginning of a chain */ 1607 rxtop = skb; 1608 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1609 0, length); 1610 } else { 1611 /* this is the middle of a chain */ 1612 shinfo = skb_shinfo(rxtop); 1613 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1614 buffer_info->page, 0, 1615 length); 1616 /* re-use the skb, only consumed the page */ 1617 buffer_info->skb = skb; 1618 } 1619 e1000_consume_page(buffer_info, rxtop, length); 1620 goto next_desc; 1621 } else { 1622 if (rxtop) { 1623 /* end of the chain */ 1624 shinfo = skb_shinfo(rxtop); 1625 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1626 buffer_info->page, 0, 1627 length); 1628 /* re-use the current skb, we only consumed the 1629 * page 1630 */ 1631 buffer_info->skb = skb; 1632 skb = rxtop; 1633 rxtop = NULL; 1634 e1000_consume_page(buffer_info, skb, length); 1635 } else { 1636 /* no chain, got EOP, this buf is the packet 1637 * copybreak to save the put_page/alloc_page 1638 */ 1639 if (length <= copybreak && 1640 skb_tailroom(skb) >= length) { 1641 u8 *vaddr; 1642 vaddr = kmap_atomic(buffer_info->page); 1643 memcpy(skb_tail_pointer(skb), vaddr, 1644 length); 1645 kunmap_atomic(vaddr); 1646 /* re-use the page, so don't erase 1647 * buffer_info->page 1648 */ 1649 skb_put(skb, length); 1650 } else { 1651 skb_fill_page_desc(skb, 0, 1652 buffer_info->page, 0, 1653 length); 1654 e1000_consume_page(buffer_info, skb, 1655 length); 1656 } 1657 } 1658 } 1659 1660 /* Receive Checksum Offload */ 1661 e1000_rx_checksum(adapter, staterr, skb); 1662 1663 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1664 1665 /* probably a little skewed due to removing CRC */ 1666 total_rx_bytes += skb->len; 1667 total_rx_packets++; 1668 1669 /* eth type trans needs skb->data to point to something */ 1670 if (!pskb_may_pull(skb, ETH_HLEN)) { 1671 e_err("pskb_may_pull failed.\n"); 1672 dev_kfree_skb_irq(skb); 1673 goto next_desc; 1674 } 1675 1676 e1000_receive_skb(adapter, netdev, skb, staterr, 1677 rx_desc->wb.upper.vlan); 1678 1679 next_desc: 1680 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1681 1682 /* return some buffers to hardware, one at a time is too slow */ 1683 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1684 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1685 GFP_ATOMIC); 1686 cleaned_count = 0; 1687 } 1688 1689 /* use prefetched values */ 1690 rx_desc = next_rxd; 1691 buffer_info = next_buffer; 1692 1693 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1694 } 1695 rx_ring->next_to_clean = i; 1696 1697 cleaned_count = e1000_desc_unused(rx_ring); 1698 if (cleaned_count) 1699 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1700 1701 adapter->total_rx_bytes += total_rx_bytes; 1702 adapter->total_rx_packets += total_rx_packets; 1703 return cleaned; 1704 } 1705 1706 /** 1707 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1708 * @rx_ring: Rx descriptor ring 1709 **/ 1710 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1711 { 1712 struct e1000_adapter *adapter = rx_ring->adapter; 1713 struct e1000_buffer *buffer_info; 1714 struct e1000_ps_page *ps_page; 1715 struct pci_dev *pdev = adapter->pdev; 1716 unsigned int i, j; 1717 1718 /* Free all the Rx ring sk_buffs */ 1719 for (i = 0; i < rx_ring->count; i++) { 1720 buffer_info = &rx_ring->buffer_info[i]; 1721 if (buffer_info->dma) { 1722 if (adapter->clean_rx == e1000_clean_rx_irq) 1723 dma_unmap_single(&pdev->dev, buffer_info->dma, 1724 adapter->rx_buffer_len, 1725 DMA_FROM_DEVICE); 1726 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1727 dma_unmap_page(&pdev->dev, buffer_info->dma, 1728 PAGE_SIZE, DMA_FROM_DEVICE); 1729 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1730 dma_unmap_single(&pdev->dev, buffer_info->dma, 1731 adapter->rx_ps_bsize0, 1732 DMA_FROM_DEVICE); 1733 buffer_info->dma = 0; 1734 } 1735 1736 if (buffer_info->page) { 1737 put_page(buffer_info->page); 1738 buffer_info->page = NULL; 1739 } 1740 1741 if (buffer_info->skb) { 1742 dev_kfree_skb(buffer_info->skb); 1743 buffer_info->skb = NULL; 1744 } 1745 1746 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1747 ps_page = &buffer_info->ps_pages[j]; 1748 if (!ps_page->page) 1749 break; 1750 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1751 DMA_FROM_DEVICE); 1752 ps_page->dma = 0; 1753 put_page(ps_page->page); 1754 ps_page->page = NULL; 1755 } 1756 } 1757 1758 /* there also may be some cached data from a chained receive */ 1759 if (rx_ring->rx_skb_top) { 1760 dev_kfree_skb(rx_ring->rx_skb_top); 1761 rx_ring->rx_skb_top = NULL; 1762 } 1763 1764 /* Zero out the descriptor ring */ 1765 memset(rx_ring->desc, 0, rx_ring->size); 1766 1767 rx_ring->next_to_clean = 0; 1768 rx_ring->next_to_use = 0; 1769 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1770 } 1771 1772 static void e1000e_downshift_workaround(struct work_struct *work) 1773 { 1774 struct e1000_adapter *adapter = container_of(work, 1775 struct e1000_adapter, 1776 downshift_task); 1777 1778 if (test_bit(__E1000_DOWN, &adapter->state)) 1779 return; 1780 1781 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1782 } 1783 1784 /** 1785 * e1000_intr_msi - Interrupt Handler 1786 * @irq: interrupt number 1787 * @data: pointer to a network interface device structure 1788 **/ 1789 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1790 { 1791 struct net_device *netdev = data; 1792 struct e1000_adapter *adapter = netdev_priv(netdev); 1793 struct e1000_hw *hw = &adapter->hw; 1794 u32 icr = er32(ICR); 1795 1796 /* read ICR disables interrupts using IAM */ 1797 if (icr & E1000_ICR_LSC) { 1798 hw->mac.get_link_status = true; 1799 /* ICH8 workaround-- Call gig speed drop workaround on cable 1800 * disconnect (LSC) before accessing any PHY registers 1801 */ 1802 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1803 (!(er32(STATUS) & E1000_STATUS_LU))) 1804 schedule_work(&adapter->downshift_task); 1805 1806 /* 80003ES2LAN workaround-- For packet buffer work-around on 1807 * link down event; disable receives here in the ISR and reset 1808 * adapter in watchdog 1809 */ 1810 if (netif_carrier_ok(netdev) && 1811 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1812 /* disable receives */ 1813 u32 rctl = er32(RCTL); 1814 1815 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1816 adapter->flags |= FLAG_RESTART_NOW; 1817 } 1818 /* guard against interrupt when we're going down */ 1819 if (!test_bit(__E1000_DOWN, &adapter->state)) 1820 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1821 } 1822 1823 /* Reset on uncorrectable ECC error */ 1824 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1825 u32 pbeccsts = er32(PBECCSTS); 1826 1827 adapter->corr_errors += 1828 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1829 adapter->uncorr_errors += 1830 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1831 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1832 1833 /* Do the reset outside of interrupt context */ 1834 schedule_work(&adapter->reset_task); 1835 1836 /* return immediately since reset is imminent */ 1837 return IRQ_HANDLED; 1838 } 1839 1840 if (napi_schedule_prep(&adapter->napi)) { 1841 adapter->total_tx_bytes = 0; 1842 adapter->total_tx_packets = 0; 1843 adapter->total_rx_bytes = 0; 1844 adapter->total_rx_packets = 0; 1845 __napi_schedule(&adapter->napi); 1846 } 1847 1848 return IRQ_HANDLED; 1849 } 1850 1851 /** 1852 * e1000_intr - Interrupt Handler 1853 * @irq: interrupt number 1854 * @data: pointer to a network interface device structure 1855 **/ 1856 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1857 { 1858 struct net_device *netdev = data; 1859 struct e1000_adapter *adapter = netdev_priv(netdev); 1860 struct e1000_hw *hw = &adapter->hw; 1861 u32 rctl, icr = er32(ICR); 1862 1863 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1864 return IRQ_NONE; /* Not our interrupt */ 1865 1866 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1867 * not set, then the adapter didn't send an interrupt 1868 */ 1869 if (!(icr & E1000_ICR_INT_ASSERTED)) 1870 return IRQ_NONE; 1871 1872 /* Interrupt Auto-Mask...upon reading ICR, 1873 * interrupts are masked. No need for the 1874 * IMC write 1875 */ 1876 1877 if (icr & E1000_ICR_LSC) { 1878 hw->mac.get_link_status = true; 1879 /* ICH8 workaround-- Call gig speed drop workaround on cable 1880 * disconnect (LSC) before accessing any PHY registers 1881 */ 1882 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1883 (!(er32(STATUS) & E1000_STATUS_LU))) 1884 schedule_work(&adapter->downshift_task); 1885 1886 /* 80003ES2LAN workaround-- 1887 * For packet buffer work-around on link down event; 1888 * disable receives here in the ISR and 1889 * reset adapter in watchdog 1890 */ 1891 if (netif_carrier_ok(netdev) && 1892 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1893 /* disable receives */ 1894 rctl = er32(RCTL); 1895 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1896 adapter->flags |= FLAG_RESTART_NOW; 1897 } 1898 /* guard against interrupt when we're going down */ 1899 if (!test_bit(__E1000_DOWN, &adapter->state)) 1900 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1901 } 1902 1903 /* Reset on uncorrectable ECC error */ 1904 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1905 u32 pbeccsts = er32(PBECCSTS); 1906 1907 adapter->corr_errors += 1908 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1909 adapter->uncorr_errors += 1910 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1911 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1912 1913 /* Do the reset outside of interrupt context */ 1914 schedule_work(&adapter->reset_task); 1915 1916 /* return immediately since reset is imminent */ 1917 return IRQ_HANDLED; 1918 } 1919 1920 if (napi_schedule_prep(&adapter->napi)) { 1921 adapter->total_tx_bytes = 0; 1922 adapter->total_tx_packets = 0; 1923 adapter->total_rx_bytes = 0; 1924 adapter->total_rx_packets = 0; 1925 __napi_schedule(&adapter->napi); 1926 } 1927 1928 return IRQ_HANDLED; 1929 } 1930 1931 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1932 { 1933 struct net_device *netdev = data; 1934 struct e1000_adapter *adapter = netdev_priv(netdev); 1935 struct e1000_hw *hw = &adapter->hw; 1936 u32 icr = er32(ICR); 1937 1938 if (icr & adapter->eiac_mask) 1939 ew32(ICS, (icr & adapter->eiac_mask)); 1940 1941 if (icr & E1000_ICR_LSC) { 1942 hw->mac.get_link_status = true; 1943 /* guard against interrupt when we're going down */ 1944 if (!test_bit(__E1000_DOWN, &adapter->state)) 1945 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1946 } 1947 1948 if (!test_bit(__E1000_DOWN, &adapter->state)) 1949 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1950 1951 return IRQ_HANDLED; 1952 } 1953 1954 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1955 { 1956 struct net_device *netdev = data; 1957 struct e1000_adapter *adapter = netdev_priv(netdev); 1958 struct e1000_hw *hw = &adapter->hw; 1959 struct e1000_ring *tx_ring = adapter->tx_ring; 1960 1961 adapter->total_tx_bytes = 0; 1962 adapter->total_tx_packets = 0; 1963 1964 if (!e1000_clean_tx_irq(tx_ring)) 1965 /* Ring was not completely cleaned, so fire another interrupt */ 1966 ew32(ICS, tx_ring->ims_val); 1967 1968 if (!test_bit(__E1000_DOWN, &adapter->state)) 1969 ew32(IMS, adapter->tx_ring->ims_val); 1970 1971 return IRQ_HANDLED; 1972 } 1973 1974 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1975 { 1976 struct net_device *netdev = data; 1977 struct e1000_adapter *adapter = netdev_priv(netdev); 1978 struct e1000_ring *rx_ring = adapter->rx_ring; 1979 1980 /* Write the ITR value calculated at the end of the 1981 * previous interrupt. 1982 */ 1983 if (rx_ring->set_itr) { 1984 u32 itr = rx_ring->itr_val ? 1985 1000000000 / (rx_ring->itr_val * 256) : 0; 1986 1987 writel(itr, rx_ring->itr_register); 1988 rx_ring->set_itr = 0; 1989 } 1990 1991 if (napi_schedule_prep(&adapter->napi)) { 1992 adapter->total_rx_bytes = 0; 1993 adapter->total_rx_packets = 0; 1994 __napi_schedule(&adapter->napi); 1995 } 1996 return IRQ_HANDLED; 1997 } 1998 1999 /** 2000 * e1000_configure_msix - Configure MSI-X hardware 2001 * 2002 * e1000_configure_msix sets up the hardware to properly 2003 * generate MSI-X interrupts. 2004 **/ 2005 static void e1000_configure_msix(struct e1000_adapter *adapter) 2006 { 2007 struct e1000_hw *hw = &adapter->hw; 2008 struct e1000_ring *rx_ring = adapter->rx_ring; 2009 struct e1000_ring *tx_ring = adapter->tx_ring; 2010 int vector = 0; 2011 u32 ctrl_ext, ivar = 0; 2012 2013 adapter->eiac_mask = 0; 2014 2015 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 2016 if (hw->mac.type == e1000_82574) { 2017 u32 rfctl = er32(RFCTL); 2018 2019 rfctl |= E1000_RFCTL_ACK_DIS; 2020 ew32(RFCTL, rfctl); 2021 } 2022 2023 /* Configure Rx vector */ 2024 rx_ring->ims_val = E1000_IMS_RXQ0; 2025 adapter->eiac_mask |= rx_ring->ims_val; 2026 if (rx_ring->itr_val) 2027 writel(1000000000 / (rx_ring->itr_val * 256), 2028 rx_ring->itr_register); 2029 else 2030 writel(1, rx_ring->itr_register); 2031 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2032 2033 /* Configure Tx vector */ 2034 tx_ring->ims_val = E1000_IMS_TXQ0; 2035 vector++; 2036 if (tx_ring->itr_val) 2037 writel(1000000000 / (tx_ring->itr_val * 256), 2038 tx_ring->itr_register); 2039 else 2040 writel(1, tx_ring->itr_register); 2041 adapter->eiac_mask |= tx_ring->ims_val; 2042 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2043 2044 /* set vector for Other Causes, e.g. link changes */ 2045 vector++; 2046 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2047 if (rx_ring->itr_val) 2048 writel(1000000000 / (rx_ring->itr_val * 256), 2049 hw->hw_addr + E1000_EITR_82574(vector)); 2050 else 2051 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2052 2053 /* Cause Tx interrupts on every write back */ 2054 ivar |= BIT(31); 2055 2056 ew32(IVAR, ivar); 2057 2058 /* enable MSI-X PBA support */ 2059 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2060 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2061 ew32(CTRL_EXT, ctrl_ext); 2062 e1e_flush(); 2063 } 2064 2065 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2066 { 2067 if (adapter->msix_entries) { 2068 pci_disable_msix(adapter->pdev); 2069 kfree(adapter->msix_entries); 2070 adapter->msix_entries = NULL; 2071 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2072 pci_disable_msi(adapter->pdev); 2073 adapter->flags &= ~FLAG_MSI_ENABLED; 2074 } 2075 } 2076 2077 /** 2078 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2079 * 2080 * Attempt to configure interrupts using the best available 2081 * capabilities of the hardware and kernel. 2082 **/ 2083 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2084 { 2085 int err; 2086 int i; 2087 2088 switch (adapter->int_mode) { 2089 case E1000E_INT_MODE_MSIX: 2090 if (adapter->flags & FLAG_HAS_MSIX) { 2091 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2092 adapter->msix_entries = kcalloc(adapter->num_vectors, 2093 sizeof(struct 2094 msix_entry), 2095 GFP_KERNEL); 2096 if (adapter->msix_entries) { 2097 struct e1000_adapter *a = adapter; 2098 2099 for (i = 0; i < adapter->num_vectors; i++) 2100 adapter->msix_entries[i].entry = i; 2101 2102 err = pci_enable_msix_range(a->pdev, 2103 a->msix_entries, 2104 a->num_vectors, 2105 a->num_vectors); 2106 if (err > 0) 2107 return; 2108 } 2109 /* MSI-X failed, so fall through and try MSI */ 2110 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2111 e1000e_reset_interrupt_capability(adapter); 2112 } 2113 adapter->int_mode = E1000E_INT_MODE_MSI; 2114 /* Fall through */ 2115 case E1000E_INT_MODE_MSI: 2116 if (!pci_enable_msi(adapter->pdev)) { 2117 adapter->flags |= FLAG_MSI_ENABLED; 2118 } else { 2119 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2120 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2121 } 2122 /* Fall through */ 2123 case E1000E_INT_MODE_LEGACY: 2124 /* Don't do anything; this is the system default */ 2125 break; 2126 } 2127 2128 /* store the number of vectors being used */ 2129 adapter->num_vectors = 1; 2130 } 2131 2132 /** 2133 * e1000_request_msix - Initialize MSI-X interrupts 2134 * 2135 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2136 * kernel. 2137 **/ 2138 static int e1000_request_msix(struct e1000_adapter *adapter) 2139 { 2140 struct net_device *netdev = adapter->netdev; 2141 int err = 0, vector = 0; 2142 2143 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2144 snprintf(adapter->rx_ring->name, 2145 sizeof(adapter->rx_ring->name) - 1, 2146 "%.14s-rx-0", netdev->name); 2147 else 2148 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2149 err = request_irq(adapter->msix_entries[vector].vector, 2150 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2151 netdev); 2152 if (err) 2153 return err; 2154 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2155 E1000_EITR_82574(vector); 2156 adapter->rx_ring->itr_val = adapter->itr; 2157 vector++; 2158 2159 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2160 snprintf(adapter->tx_ring->name, 2161 sizeof(adapter->tx_ring->name) - 1, 2162 "%.14s-tx-0", netdev->name); 2163 else 2164 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2165 err = request_irq(adapter->msix_entries[vector].vector, 2166 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2167 netdev); 2168 if (err) 2169 return err; 2170 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2171 E1000_EITR_82574(vector); 2172 adapter->tx_ring->itr_val = adapter->itr; 2173 vector++; 2174 2175 err = request_irq(adapter->msix_entries[vector].vector, 2176 e1000_msix_other, 0, netdev->name, netdev); 2177 if (err) 2178 return err; 2179 2180 e1000_configure_msix(adapter); 2181 2182 return 0; 2183 } 2184 2185 /** 2186 * e1000_request_irq - initialize interrupts 2187 * 2188 * Attempts to configure interrupts using the best available 2189 * capabilities of the hardware and kernel. 2190 **/ 2191 static int e1000_request_irq(struct e1000_adapter *adapter) 2192 { 2193 struct net_device *netdev = adapter->netdev; 2194 int err; 2195 2196 if (adapter->msix_entries) { 2197 err = e1000_request_msix(adapter); 2198 if (!err) 2199 return err; 2200 /* fall back to MSI */ 2201 e1000e_reset_interrupt_capability(adapter); 2202 adapter->int_mode = E1000E_INT_MODE_MSI; 2203 e1000e_set_interrupt_capability(adapter); 2204 } 2205 if (adapter->flags & FLAG_MSI_ENABLED) { 2206 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2207 netdev->name, netdev); 2208 if (!err) 2209 return err; 2210 2211 /* fall back to legacy interrupt */ 2212 e1000e_reset_interrupt_capability(adapter); 2213 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2214 } 2215 2216 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2217 netdev->name, netdev); 2218 if (err) 2219 e_err("Unable to allocate interrupt, Error: %d\n", err); 2220 2221 return err; 2222 } 2223 2224 static void e1000_free_irq(struct e1000_adapter *adapter) 2225 { 2226 struct net_device *netdev = adapter->netdev; 2227 2228 if (adapter->msix_entries) { 2229 int vector = 0; 2230 2231 free_irq(adapter->msix_entries[vector].vector, netdev); 2232 vector++; 2233 2234 free_irq(adapter->msix_entries[vector].vector, netdev); 2235 vector++; 2236 2237 /* Other Causes interrupt vector */ 2238 free_irq(adapter->msix_entries[vector].vector, netdev); 2239 return; 2240 } 2241 2242 free_irq(adapter->pdev->irq, netdev); 2243 } 2244 2245 /** 2246 * e1000_irq_disable - Mask off interrupt generation on the NIC 2247 **/ 2248 static void e1000_irq_disable(struct e1000_adapter *adapter) 2249 { 2250 struct e1000_hw *hw = &adapter->hw; 2251 2252 ew32(IMC, ~0); 2253 if (adapter->msix_entries) 2254 ew32(EIAC_82574, 0); 2255 e1e_flush(); 2256 2257 if (adapter->msix_entries) { 2258 int i; 2259 2260 for (i = 0; i < adapter->num_vectors; i++) 2261 synchronize_irq(adapter->msix_entries[i].vector); 2262 } else { 2263 synchronize_irq(adapter->pdev->irq); 2264 } 2265 } 2266 2267 /** 2268 * e1000_irq_enable - Enable default interrupt generation settings 2269 **/ 2270 static void e1000_irq_enable(struct e1000_adapter *adapter) 2271 { 2272 struct e1000_hw *hw = &adapter->hw; 2273 2274 if (adapter->msix_entries) { 2275 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2276 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2277 IMS_OTHER_MASK); 2278 } else if (hw->mac.type >= e1000_pch_lpt) { 2279 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2280 } else { 2281 ew32(IMS, IMS_ENABLE_MASK); 2282 } 2283 e1e_flush(); 2284 } 2285 2286 /** 2287 * e1000e_get_hw_control - get control of the h/w from f/w 2288 * @adapter: address of board private structure 2289 * 2290 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2291 * For ASF and Pass Through versions of f/w this means that 2292 * the driver is loaded. For AMT version (only with 82573) 2293 * of the f/w this means that the network i/f is open. 2294 **/ 2295 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2296 { 2297 struct e1000_hw *hw = &adapter->hw; 2298 u32 ctrl_ext; 2299 u32 swsm; 2300 2301 /* Let firmware know the driver has taken over */ 2302 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2303 swsm = er32(SWSM); 2304 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2305 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2306 ctrl_ext = er32(CTRL_EXT); 2307 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2308 } 2309 } 2310 2311 /** 2312 * e1000e_release_hw_control - release control of the h/w to f/w 2313 * @adapter: address of board private structure 2314 * 2315 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2316 * For ASF and Pass Through versions of f/w this means that the 2317 * driver is no longer loaded. For AMT version (only with 82573) i 2318 * of the f/w this means that the network i/f is closed. 2319 * 2320 **/ 2321 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2322 { 2323 struct e1000_hw *hw = &adapter->hw; 2324 u32 ctrl_ext; 2325 u32 swsm; 2326 2327 /* Let firmware taken over control of h/w */ 2328 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2329 swsm = er32(SWSM); 2330 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2331 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2332 ctrl_ext = er32(CTRL_EXT); 2333 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2334 } 2335 } 2336 2337 /** 2338 * e1000_alloc_ring_dma - allocate memory for a ring structure 2339 **/ 2340 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2341 struct e1000_ring *ring) 2342 { 2343 struct pci_dev *pdev = adapter->pdev; 2344 2345 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2346 GFP_KERNEL); 2347 if (!ring->desc) 2348 return -ENOMEM; 2349 2350 return 0; 2351 } 2352 2353 /** 2354 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2355 * @tx_ring: Tx descriptor ring 2356 * 2357 * Return 0 on success, negative on failure 2358 **/ 2359 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2360 { 2361 struct e1000_adapter *adapter = tx_ring->adapter; 2362 int err = -ENOMEM, size; 2363 2364 size = sizeof(struct e1000_buffer) * tx_ring->count; 2365 tx_ring->buffer_info = vzalloc(size); 2366 if (!tx_ring->buffer_info) 2367 goto err; 2368 2369 /* round up to nearest 4K */ 2370 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2371 tx_ring->size = ALIGN(tx_ring->size, 4096); 2372 2373 err = e1000_alloc_ring_dma(adapter, tx_ring); 2374 if (err) 2375 goto err; 2376 2377 tx_ring->next_to_use = 0; 2378 tx_ring->next_to_clean = 0; 2379 2380 return 0; 2381 err: 2382 vfree(tx_ring->buffer_info); 2383 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2384 return err; 2385 } 2386 2387 /** 2388 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2389 * @rx_ring: Rx descriptor ring 2390 * 2391 * Returns 0 on success, negative on failure 2392 **/ 2393 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2394 { 2395 struct e1000_adapter *adapter = rx_ring->adapter; 2396 struct e1000_buffer *buffer_info; 2397 int i, size, desc_len, err = -ENOMEM; 2398 2399 size = sizeof(struct e1000_buffer) * rx_ring->count; 2400 rx_ring->buffer_info = vzalloc(size); 2401 if (!rx_ring->buffer_info) 2402 goto err; 2403 2404 for (i = 0; i < rx_ring->count; i++) { 2405 buffer_info = &rx_ring->buffer_info[i]; 2406 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2407 sizeof(struct e1000_ps_page), 2408 GFP_KERNEL); 2409 if (!buffer_info->ps_pages) 2410 goto err_pages; 2411 } 2412 2413 desc_len = sizeof(union e1000_rx_desc_packet_split); 2414 2415 /* Round up to nearest 4K */ 2416 rx_ring->size = rx_ring->count * desc_len; 2417 rx_ring->size = ALIGN(rx_ring->size, 4096); 2418 2419 err = e1000_alloc_ring_dma(adapter, rx_ring); 2420 if (err) 2421 goto err_pages; 2422 2423 rx_ring->next_to_clean = 0; 2424 rx_ring->next_to_use = 0; 2425 rx_ring->rx_skb_top = NULL; 2426 2427 return 0; 2428 2429 err_pages: 2430 for (i = 0; i < rx_ring->count; i++) { 2431 buffer_info = &rx_ring->buffer_info[i]; 2432 kfree(buffer_info->ps_pages); 2433 } 2434 err: 2435 vfree(rx_ring->buffer_info); 2436 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2437 return err; 2438 } 2439 2440 /** 2441 * e1000_clean_tx_ring - Free Tx Buffers 2442 * @tx_ring: Tx descriptor ring 2443 **/ 2444 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2445 { 2446 struct e1000_adapter *adapter = tx_ring->adapter; 2447 struct e1000_buffer *buffer_info; 2448 unsigned long size; 2449 unsigned int i; 2450 2451 for (i = 0; i < tx_ring->count; i++) { 2452 buffer_info = &tx_ring->buffer_info[i]; 2453 e1000_put_txbuf(tx_ring, buffer_info, false); 2454 } 2455 2456 netdev_reset_queue(adapter->netdev); 2457 size = sizeof(struct e1000_buffer) * tx_ring->count; 2458 memset(tx_ring->buffer_info, 0, size); 2459 2460 memset(tx_ring->desc, 0, tx_ring->size); 2461 2462 tx_ring->next_to_use = 0; 2463 tx_ring->next_to_clean = 0; 2464 } 2465 2466 /** 2467 * e1000e_free_tx_resources - Free Tx Resources per Queue 2468 * @tx_ring: Tx descriptor ring 2469 * 2470 * Free all transmit software resources 2471 **/ 2472 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2473 { 2474 struct e1000_adapter *adapter = tx_ring->adapter; 2475 struct pci_dev *pdev = adapter->pdev; 2476 2477 e1000_clean_tx_ring(tx_ring); 2478 2479 vfree(tx_ring->buffer_info); 2480 tx_ring->buffer_info = NULL; 2481 2482 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2483 tx_ring->dma); 2484 tx_ring->desc = NULL; 2485 } 2486 2487 /** 2488 * e1000e_free_rx_resources - Free Rx Resources 2489 * @rx_ring: Rx descriptor ring 2490 * 2491 * Free all receive software resources 2492 **/ 2493 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2494 { 2495 struct e1000_adapter *adapter = rx_ring->adapter; 2496 struct pci_dev *pdev = adapter->pdev; 2497 int i; 2498 2499 e1000_clean_rx_ring(rx_ring); 2500 2501 for (i = 0; i < rx_ring->count; i++) 2502 kfree(rx_ring->buffer_info[i].ps_pages); 2503 2504 vfree(rx_ring->buffer_info); 2505 rx_ring->buffer_info = NULL; 2506 2507 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2508 rx_ring->dma); 2509 rx_ring->desc = NULL; 2510 } 2511 2512 /** 2513 * e1000_update_itr - update the dynamic ITR value based on statistics 2514 * @adapter: pointer to adapter 2515 * @itr_setting: current adapter->itr 2516 * @packets: the number of packets during this measurement interval 2517 * @bytes: the number of bytes during this measurement interval 2518 * 2519 * Stores a new ITR value based on packets and byte 2520 * counts during the last interrupt. The advantage of per interrupt 2521 * computation is faster updates and more accurate ITR for the current 2522 * traffic pattern. Constants in this function were computed 2523 * based on theoretical maximum wire speed and thresholds were set based 2524 * on testing data as well as attempting to minimize response time 2525 * while increasing bulk throughput. This functionality is controlled 2526 * by the InterruptThrottleRate module parameter. 2527 **/ 2528 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2529 { 2530 unsigned int retval = itr_setting; 2531 2532 if (packets == 0) 2533 return itr_setting; 2534 2535 switch (itr_setting) { 2536 case lowest_latency: 2537 /* handle TSO and jumbo frames */ 2538 if (bytes / packets > 8000) 2539 retval = bulk_latency; 2540 else if ((packets < 5) && (bytes > 512)) 2541 retval = low_latency; 2542 break; 2543 case low_latency: /* 50 usec aka 20000 ints/s */ 2544 if (bytes > 10000) { 2545 /* this if handles the TSO accounting */ 2546 if (bytes / packets > 8000) 2547 retval = bulk_latency; 2548 else if ((packets < 10) || ((bytes / packets) > 1200)) 2549 retval = bulk_latency; 2550 else if ((packets > 35)) 2551 retval = lowest_latency; 2552 } else if (bytes / packets > 2000) { 2553 retval = bulk_latency; 2554 } else if (packets <= 2 && bytes < 512) { 2555 retval = lowest_latency; 2556 } 2557 break; 2558 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2559 if (bytes > 25000) { 2560 if (packets > 35) 2561 retval = low_latency; 2562 } else if (bytes < 6000) { 2563 retval = low_latency; 2564 } 2565 break; 2566 } 2567 2568 return retval; 2569 } 2570 2571 static void e1000_set_itr(struct e1000_adapter *adapter) 2572 { 2573 u16 current_itr; 2574 u32 new_itr = adapter->itr; 2575 2576 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2577 if (adapter->link_speed != SPEED_1000) { 2578 current_itr = 0; 2579 new_itr = 4000; 2580 goto set_itr_now; 2581 } 2582 2583 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2584 new_itr = 0; 2585 goto set_itr_now; 2586 } 2587 2588 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2589 adapter->total_tx_packets, 2590 adapter->total_tx_bytes); 2591 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2592 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2593 adapter->tx_itr = low_latency; 2594 2595 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2596 adapter->total_rx_packets, 2597 adapter->total_rx_bytes); 2598 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2599 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2600 adapter->rx_itr = low_latency; 2601 2602 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2603 2604 /* counts and packets in update_itr are dependent on these numbers */ 2605 switch (current_itr) { 2606 case lowest_latency: 2607 new_itr = 70000; 2608 break; 2609 case low_latency: 2610 new_itr = 20000; /* aka hwitr = ~200 */ 2611 break; 2612 case bulk_latency: 2613 new_itr = 4000; 2614 break; 2615 default: 2616 break; 2617 } 2618 2619 set_itr_now: 2620 if (new_itr != adapter->itr) { 2621 /* this attempts to bias the interrupt rate towards Bulk 2622 * by adding intermediate steps when interrupt rate is 2623 * increasing 2624 */ 2625 new_itr = new_itr > adapter->itr ? 2626 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2627 adapter->itr = new_itr; 2628 adapter->rx_ring->itr_val = new_itr; 2629 if (adapter->msix_entries) 2630 adapter->rx_ring->set_itr = 1; 2631 else 2632 e1000e_write_itr(adapter, new_itr); 2633 } 2634 } 2635 2636 /** 2637 * e1000e_write_itr - write the ITR value to the appropriate registers 2638 * @adapter: address of board private structure 2639 * @itr: new ITR value to program 2640 * 2641 * e1000e_write_itr determines if the adapter is in MSI-X mode 2642 * and, if so, writes the EITR registers with the ITR value. 2643 * Otherwise, it writes the ITR value into the ITR register. 2644 **/ 2645 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2646 { 2647 struct e1000_hw *hw = &adapter->hw; 2648 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2649 2650 if (adapter->msix_entries) { 2651 int vector; 2652 2653 for (vector = 0; vector < adapter->num_vectors; vector++) 2654 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2655 } else { 2656 ew32(ITR, new_itr); 2657 } 2658 } 2659 2660 /** 2661 * e1000_alloc_queues - Allocate memory for all rings 2662 * @adapter: board private structure to initialize 2663 **/ 2664 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2665 { 2666 int size = sizeof(struct e1000_ring); 2667 2668 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2669 if (!adapter->tx_ring) 2670 goto err; 2671 adapter->tx_ring->count = adapter->tx_ring_count; 2672 adapter->tx_ring->adapter = adapter; 2673 2674 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2675 if (!adapter->rx_ring) 2676 goto err; 2677 adapter->rx_ring->count = adapter->rx_ring_count; 2678 adapter->rx_ring->adapter = adapter; 2679 2680 return 0; 2681 err: 2682 e_err("Unable to allocate memory for queues\n"); 2683 kfree(adapter->rx_ring); 2684 kfree(adapter->tx_ring); 2685 return -ENOMEM; 2686 } 2687 2688 /** 2689 * e1000e_poll - NAPI Rx polling callback 2690 * @napi: struct associated with this polling callback 2691 * @budget: number of packets driver is allowed to process this poll 2692 **/ 2693 static int e1000e_poll(struct napi_struct *napi, int budget) 2694 { 2695 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2696 napi); 2697 struct e1000_hw *hw = &adapter->hw; 2698 struct net_device *poll_dev = adapter->netdev; 2699 int tx_cleaned = 1, work_done = 0; 2700 2701 adapter = netdev_priv(poll_dev); 2702 2703 if (!adapter->msix_entries || 2704 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2705 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2706 2707 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2708 2709 if (!tx_cleaned || work_done == budget) 2710 return budget; 2711 2712 /* Exit the polling mode, but don't re-enable interrupts if stack might 2713 * poll us due to busy-polling 2714 */ 2715 if (likely(napi_complete_done(napi, work_done))) { 2716 if (adapter->itr_setting & 3) 2717 e1000_set_itr(adapter); 2718 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2719 if (adapter->msix_entries) 2720 ew32(IMS, adapter->rx_ring->ims_val); 2721 else 2722 e1000_irq_enable(adapter); 2723 } 2724 } 2725 2726 return work_done; 2727 } 2728 2729 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2730 __always_unused __be16 proto, u16 vid) 2731 { 2732 struct e1000_adapter *adapter = netdev_priv(netdev); 2733 struct e1000_hw *hw = &adapter->hw; 2734 u32 vfta, index; 2735 2736 /* don't update vlan cookie if already programmed */ 2737 if ((adapter->hw.mng_cookie.status & 2738 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2739 (vid == adapter->mng_vlan_id)) 2740 return 0; 2741 2742 /* add VID to filter table */ 2743 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2744 index = (vid >> 5) & 0x7F; 2745 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2746 vfta |= BIT((vid & 0x1F)); 2747 hw->mac.ops.write_vfta(hw, index, vfta); 2748 } 2749 2750 set_bit(vid, adapter->active_vlans); 2751 2752 return 0; 2753 } 2754 2755 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2756 __always_unused __be16 proto, u16 vid) 2757 { 2758 struct e1000_adapter *adapter = netdev_priv(netdev); 2759 struct e1000_hw *hw = &adapter->hw; 2760 u32 vfta, index; 2761 2762 if ((adapter->hw.mng_cookie.status & 2763 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2764 (vid == adapter->mng_vlan_id)) { 2765 /* release control to f/w */ 2766 e1000e_release_hw_control(adapter); 2767 return 0; 2768 } 2769 2770 /* remove VID from filter table */ 2771 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2772 index = (vid >> 5) & 0x7F; 2773 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2774 vfta &= ~BIT((vid & 0x1F)); 2775 hw->mac.ops.write_vfta(hw, index, vfta); 2776 } 2777 2778 clear_bit(vid, adapter->active_vlans); 2779 2780 return 0; 2781 } 2782 2783 /** 2784 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2785 * @adapter: board private structure to initialize 2786 **/ 2787 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2788 { 2789 struct net_device *netdev = adapter->netdev; 2790 struct e1000_hw *hw = &adapter->hw; 2791 u32 rctl; 2792 2793 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2794 /* disable VLAN receive filtering */ 2795 rctl = er32(RCTL); 2796 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2797 ew32(RCTL, rctl); 2798 2799 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2800 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2801 adapter->mng_vlan_id); 2802 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2803 } 2804 } 2805 } 2806 2807 /** 2808 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2809 * @adapter: board private structure to initialize 2810 **/ 2811 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2812 { 2813 struct e1000_hw *hw = &adapter->hw; 2814 u32 rctl; 2815 2816 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2817 /* enable VLAN receive filtering */ 2818 rctl = er32(RCTL); 2819 rctl |= E1000_RCTL_VFE; 2820 rctl &= ~E1000_RCTL_CFIEN; 2821 ew32(RCTL, rctl); 2822 } 2823 } 2824 2825 /** 2826 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2827 * @adapter: board private structure to initialize 2828 **/ 2829 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2830 { 2831 struct e1000_hw *hw = &adapter->hw; 2832 u32 ctrl; 2833 2834 /* disable VLAN tag insert/strip */ 2835 ctrl = er32(CTRL); 2836 ctrl &= ~E1000_CTRL_VME; 2837 ew32(CTRL, ctrl); 2838 } 2839 2840 /** 2841 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2842 * @adapter: board private structure to initialize 2843 **/ 2844 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2845 { 2846 struct e1000_hw *hw = &adapter->hw; 2847 u32 ctrl; 2848 2849 /* enable VLAN tag insert/strip */ 2850 ctrl = er32(CTRL); 2851 ctrl |= E1000_CTRL_VME; 2852 ew32(CTRL, ctrl); 2853 } 2854 2855 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2856 { 2857 struct net_device *netdev = adapter->netdev; 2858 u16 vid = adapter->hw.mng_cookie.vlan_id; 2859 u16 old_vid = adapter->mng_vlan_id; 2860 2861 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2862 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2863 adapter->mng_vlan_id = vid; 2864 } 2865 2866 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2867 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2868 } 2869 2870 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2871 { 2872 u16 vid; 2873 2874 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2875 2876 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2877 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2878 } 2879 2880 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2881 { 2882 struct e1000_hw *hw = &adapter->hw; 2883 u32 manc, manc2h, mdef, i, j; 2884 2885 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2886 return; 2887 2888 manc = er32(MANC); 2889 2890 /* enable receiving management packets to the host. this will probably 2891 * generate destination unreachable messages from the host OS, but 2892 * the packets will be handled on SMBUS 2893 */ 2894 manc |= E1000_MANC_EN_MNG2HOST; 2895 manc2h = er32(MANC2H); 2896 2897 switch (hw->mac.type) { 2898 default: 2899 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2900 break; 2901 case e1000_82574: 2902 case e1000_82583: 2903 /* Check if IPMI pass-through decision filter already exists; 2904 * if so, enable it. 2905 */ 2906 for (i = 0, j = 0; i < 8; i++) { 2907 mdef = er32(MDEF(i)); 2908 2909 /* Ignore filters with anything other than IPMI ports */ 2910 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2911 continue; 2912 2913 /* Enable this decision filter in MANC2H */ 2914 if (mdef) 2915 manc2h |= BIT(i); 2916 2917 j |= mdef; 2918 } 2919 2920 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2921 break; 2922 2923 /* Create new decision filter in an empty filter */ 2924 for (i = 0, j = 0; i < 8; i++) 2925 if (er32(MDEF(i)) == 0) { 2926 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2927 E1000_MDEF_PORT_664)); 2928 manc2h |= BIT(1); 2929 j++; 2930 break; 2931 } 2932 2933 if (!j) 2934 e_warn("Unable to create IPMI pass-through filter\n"); 2935 break; 2936 } 2937 2938 ew32(MANC2H, manc2h); 2939 ew32(MANC, manc); 2940 } 2941 2942 /** 2943 * e1000_configure_tx - Configure Transmit Unit after Reset 2944 * @adapter: board private structure 2945 * 2946 * Configure the Tx unit of the MAC after a reset. 2947 **/ 2948 static void e1000_configure_tx(struct e1000_adapter *adapter) 2949 { 2950 struct e1000_hw *hw = &adapter->hw; 2951 struct e1000_ring *tx_ring = adapter->tx_ring; 2952 u64 tdba; 2953 u32 tdlen, tctl, tarc; 2954 2955 /* Setup the HW Tx Head and Tail descriptor pointers */ 2956 tdba = tx_ring->dma; 2957 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2958 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2959 ew32(TDBAH(0), (tdba >> 32)); 2960 ew32(TDLEN(0), tdlen); 2961 ew32(TDH(0), 0); 2962 ew32(TDT(0), 0); 2963 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2964 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2965 2966 writel(0, tx_ring->head); 2967 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2968 e1000e_update_tdt_wa(tx_ring, 0); 2969 else 2970 writel(0, tx_ring->tail); 2971 2972 /* Set the Tx Interrupt Delay register */ 2973 ew32(TIDV, adapter->tx_int_delay); 2974 /* Tx irq moderation */ 2975 ew32(TADV, adapter->tx_abs_int_delay); 2976 2977 if (adapter->flags2 & FLAG2_DMA_BURST) { 2978 u32 txdctl = er32(TXDCTL(0)); 2979 2980 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2981 E1000_TXDCTL_WTHRESH); 2982 /* set up some performance related parameters to encourage the 2983 * hardware to use the bus more efficiently in bursts, depends 2984 * on the tx_int_delay to be enabled, 2985 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2986 * hthresh = 1 ==> prefetch when one or more available 2987 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2988 * BEWARE: this seems to work but should be considered first if 2989 * there are Tx hangs or other Tx related bugs 2990 */ 2991 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2992 ew32(TXDCTL(0), txdctl); 2993 } 2994 /* erratum work around: set txdctl the same for both queues */ 2995 ew32(TXDCTL(1), er32(TXDCTL(0))); 2996 2997 /* Program the Transmit Control Register */ 2998 tctl = er32(TCTL); 2999 tctl &= ~E1000_TCTL_CT; 3000 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3001 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3002 3003 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 3004 tarc = er32(TARC(0)); 3005 /* set the speed mode bit, we'll clear it if we're not at 3006 * gigabit link later 3007 */ 3008 #define SPEED_MODE_BIT BIT(21) 3009 tarc |= SPEED_MODE_BIT; 3010 ew32(TARC(0), tarc); 3011 } 3012 3013 /* errata: program both queues to unweighted RR */ 3014 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 3015 tarc = er32(TARC(0)); 3016 tarc |= 1; 3017 ew32(TARC(0), tarc); 3018 tarc = er32(TARC(1)); 3019 tarc |= 1; 3020 ew32(TARC(1), tarc); 3021 } 3022 3023 /* Setup Transmit Descriptor Settings for eop descriptor */ 3024 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3025 3026 /* only set IDE if we are delaying interrupts using the timers */ 3027 if (adapter->tx_int_delay) 3028 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3029 3030 /* enable Report Status bit */ 3031 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3032 3033 ew32(TCTL, tctl); 3034 3035 hw->mac.ops.config_collision_dist(hw); 3036 3037 /* SPT and KBL Si errata workaround to avoid data corruption */ 3038 if (hw->mac.type == e1000_pch_spt) { 3039 u32 reg_val; 3040 3041 reg_val = er32(IOSFPC); 3042 reg_val |= E1000_RCTL_RDMTS_HEX; 3043 ew32(IOSFPC, reg_val); 3044 3045 reg_val = er32(TARC(0)); 3046 /* SPT and KBL Si errata workaround to avoid Tx hang. 3047 * Dropping the number of outstanding requests from 3048 * 3 to 2 in order to avoid a buffer overrun. 3049 */ 3050 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3051 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3052 ew32(TARC(0), reg_val); 3053 } 3054 } 3055 3056 /** 3057 * e1000_setup_rctl - configure the receive control registers 3058 * @adapter: Board private structure 3059 **/ 3060 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3061 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3062 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3063 { 3064 struct e1000_hw *hw = &adapter->hw; 3065 u32 rctl, rfctl; 3066 u32 pages = 0; 3067 3068 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3069 * If jumbo frames not set, program related MAC/PHY registers 3070 * to h/w defaults 3071 */ 3072 if (hw->mac.type >= e1000_pch2lan) { 3073 s32 ret_val; 3074 3075 if (adapter->netdev->mtu > ETH_DATA_LEN) 3076 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3077 else 3078 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3079 3080 if (ret_val) 3081 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3082 } 3083 3084 /* Program MC offset vector base */ 3085 rctl = er32(RCTL); 3086 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3087 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3088 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3089 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3090 3091 /* Do not Store bad packets */ 3092 rctl &= ~E1000_RCTL_SBP; 3093 3094 /* Enable Long Packet receive */ 3095 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3096 rctl &= ~E1000_RCTL_LPE; 3097 else 3098 rctl |= E1000_RCTL_LPE; 3099 3100 /* Some systems expect that the CRC is included in SMBUS traffic. The 3101 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3102 * host memory when this is enabled 3103 */ 3104 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3105 rctl |= E1000_RCTL_SECRC; 3106 3107 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3108 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3109 u16 phy_data; 3110 3111 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3112 phy_data &= 0xfff8; 3113 phy_data |= BIT(2); 3114 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3115 3116 e1e_rphy(hw, 22, &phy_data); 3117 phy_data &= 0x0fff; 3118 phy_data |= BIT(14); 3119 e1e_wphy(hw, 0x10, 0x2823); 3120 e1e_wphy(hw, 0x11, 0x0003); 3121 e1e_wphy(hw, 22, phy_data); 3122 } 3123 3124 /* Setup buffer sizes */ 3125 rctl &= ~E1000_RCTL_SZ_4096; 3126 rctl |= E1000_RCTL_BSEX; 3127 switch (adapter->rx_buffer_len) { 3128 case 2048: 3129 default: 3130 rctl |= E1000_RCTL_SZ_2048; 3131 rctl &= ~E1000_RCTL_BSEX; 3132 break; 3133 case 4096: 3134 rctl |= E1000_RCTL_SZ_4096; 3135 break; 3136 case 8192: 3137 rctl |= E1000_RCTL_SZ_8192; 3138 break; 3139 case 16384: 3140 rctl |= E1000_RCTL_SZ_16384; 3141 break; 3142 } 3143 3144 /* Enable Extended Status in all Receive Descriptors */ 3145 rfctl = er32(RFCTL); 3146 rfctl |= E1000_RFCTL_EXTEN; 3147 ew32(RFCTL, rfctl); 3148 3149 /* 82571 and greater support packet-split where the protocol 3150 * header is placed in skb->data and the packet data is 3151 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3152 * In the case of a non-split, skb->data is linearly filled, 3153 * followed by the page buffers. Therefore, skb->data is 3154 * sized to hold the largest protocol header. 3155 * 3156 * allocations using alloc_page take too long for regular MTU 3157 * so only enable packet split for jumbo frames 3158 * 3159 * Using pages when the page size is greater than 16k wastes 3160 * a lot of memory, since we allocate 3 pages at all times 3161 * per packet. 3162 */ 3163 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3164 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3165 adapter->rx_ps_pages = pages; 3166 else 3167 adapter->rx_ps_pages = 0; 3168 3169 if (adapter->rx_ps_pages) { 3170 u32 psrctl = 0; 3171 3172 /* Enable Packet split descriptors */ 3173 rctl |= E1000_RCTL_DTYP_PS; 3174 3175 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3176 3177 switch (adapter->rx_ps_pages) { 3178 case 3: 3179 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3180 /* fall-through */ 3181 case 2: 3182 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3183 /* fall-through */ 3184 case 1: 3185 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3186 break; 3187 } 3188 3189 ew32(PSRCTL, psrctl); 3190 } 3191 3192 /* This is useful for sniffing bad packets. */ 3193 if (adapter->netdev->features & NETIF_F_RXALL) { 3194 /* UPE and MPE will be handled by normal PROMISC logic 3195 * in e1000e_set_rx_mode 3196 */ 3197 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3198 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3199 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3200 3201 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3202 E1000_RCTL_DPF | /* Allow filtered pause */ 3203 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3204 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3205 * and that breaks VLANs. 3206 */ 3207 } 3208 3209 ew32(RCTL, rctl); 3210 /* just started the receive unit, no need to restart */ 3211 adapter->flags &= ~FLAG_RESTART_NOW; 3212 } 3213 3214 /** 3215 * e1000_configure_rx - Configure Receive Unit after Reset 3216 * @adapter: board private structure 3217 * 3218 * Configure the Rx unit of the MAC after a reset. 3219 **/ 3220 static void e1000_configure_rx(struct e1000_adapter *adapter) 3221 { 3222 struct e1000_hw *hw = &adapter->hw; 3223 struct e1000_ring *rx_ring = adapter->rx_ring; 3224 u64 rdba; 3225 u32 rdlen, rctl, rxcsum, ctrl_ext; 3226 3227 if (adapter->rx_ps_pages) { 3228 /* this is a 32 byte descriptor */ 3229 rdlen = rx_ring->count * 3230 sizeof(union e1000_rx_desc_packet_split); 3231 adapter->clean_rx = e1000_clean_rx_irq_ps; 3232 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3233 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3234 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3235 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3236 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3237 } else { 3238 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3239 adapter->clean_rx = e1000_clean_rx_irq; 3240 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3241 } 3242 3243 /* disable receives while setting up the descriptors */ 3244 rctl = er32(RCTL); 3245 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3246 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3247 e1e_flush(); 3248 usleep_range(10000, 11000); 3249 3250 if (adapter->flags2 & FLAG2_DMA_BURST) { 3251 /* set the writeback threshold (only takes effect if the RDTR 3252 * is set). set GRAN=1 and write back up to 0x4 worth, and 3253 * enable prefetching of 0x20 Rx descriptors 3254 * granularity = 01 3255 * wthresh = 04, 3256 * hthresh = 04, 3257 * pthresh = 0x20 3258 */ 3259 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3260 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3261 } 3262 3263 /* set the Receive Delay Timer Register */ 3264 ew32(RDTR, adapter->rx_int_delay); 3265 3266 /* irq moderation */ 3267 ew32(RADV, adapter->rx_abs_int_delay); 3268 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3269 e1000e_write_itr(adapter, adapter->itr); 3270 3271 ctrl_ext = er32(CTRL_EXT); 3272 /* Auto-Mask interrupts upon ICR access */ 3273 ctrl_ext |= E1000_CTRL_EXT_IAME; 3274 ew32(IAM, 0xffffffff); 3275 ew32(CTRL_EXT, ctrl_ext); 3276 e1e_flush(); 3277 3278 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3279 * the Base and Length of the Rx Descriptor Ring 3280 */ 3281 rdba = rx_ring->dma; 3282 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3283 ew32(RDBAH(0), (rdba >> 32)); 3284 ew32(RDLEN(0), rdlen); 3285 ew32(RDH(0), 0); 3286 ew32(RDT(0), 0); 3287 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3288 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3289 3290 writel(0, rx_ring->head); 3291 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3292 e1000e_update_rdt_wa(rx_ring, 0); 3293 else 3294 writel(0, rx_ring->tail); 3295 3296 /* Enable Receive Checksum Offload for TCP and UDP */ 3297 rxcsum = er32(RXCSUM); 3298 if (adapter->netdev->features & NETIF_F_RXCSUM) 3299 rxcsum |= E1000_RXCSUM_TUOFL; 3300 else 3301 rxcsum &= ~E1000_RXCSUM_TUOFL; 3302 ew32(RXCSUM, rxcsum); 3303 3304 /* With jumbo frames, excessive C-state transition latencies result 3305 * in dropped transactions. 3306 */ 3307 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3308 u32 lat = 3309 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3310 adapter->max_frame_size) * 8 / 1000; 3311 3312 if (adapter->flags & FLAG_IS_ICH) { 3313 u32 rxdctl = er32(RXDCTL(0)); 3314 3315 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3316 } 3317 3318 dev_info(&adapter->pdev->dev, 3319 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3320 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3321 } else { 3322 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3323 PM_QOS_DEFAULT_VALUE); 3324 } 3325 3326 /* Enable Receives */ 3327 ew32(RCTL, rctl); 3328 } 3329 3330 /** 3331 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3332 * @netdev: network interface device structure 3333 * 3334 * Writes multicast address list to the MTA hash table. 3335 * Returns: -ENOMEM on failure 3336 * 0 on no addresses written 3337 * X on writing X addresses to MTA 3338 */ 3339 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3340 { 3341 struct e1000_adapter *adapter = netdev_priv(netdev); 3342 struct e1000_hw *hw = &adapter->hw; 3343 struct netdev_hw_addr *ha; 3344 u8 *mta_list; 3345 int i; 3346 3347 if (netdev_mc_empty(netdev)) { 3348 /* nothing to program, so clear mc list */ 3349 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3350 return 0; 3351 } 3352 3353 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3354 if (!mta_list) 3355 return -ENOMEM; 3356 3357 /* update_mc_addr_list expects a packed array of only addresses. */ 3358 i = 0; 3359 netdev_for_each_mc_addr(ha, netdev) 3360 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3361 3362 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3363 kfree(mta_list); 3364 3365 return netdev_mc_count(netdev); 3366 } 3367 3368 /** 3369 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3370 * @netdev: network interface device structure 3371 * 3372 * Writes unicast address list to the RAR table. 3373 * Returns: -ENOMEM on failure/insufficient address space 3374 * 0 on no addresses written 3375 * X on writing X addresses to the RAR table 3376 **/ 3377 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3378 { 3379 struct e1000_adapter *adapter = netdev_priv(netdev); 3380 struct e1000_hw *hw = &adapter->hw; 3381 unsigned int rar_entries; 3382 int count = 0; 3383 3384 rar_entries = hw->mac.ops.rar_get_count(hw); 3385 3386 /* save a rar entry for our hardware address */ 3387 rar_entries--; 3388 3389 /* save a rar entry for the LAA workaround */ 3390 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3391 rar_entries--; 3392 3393 /* return ENOMEM indicating insufficient memory for addresses */ 3394 if (netdev_uc_count(netdev) > rar_entries) 3395 return -ENOMEM; 3396 3397 if (!netdev_uc_empty(netdev) && rar_entries) { 3398 struct netdev_hw_addr *ha; 3399 3400 /* write the addresses in reverse order to avoid write 3401 * combining 3402 */ 3403 netdev_for_each_uc_addr(ha, netdev) { 3404 int ret_val; 3405 3406 if (!rar_entries) 3407 break; 3408 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3409 if (ret_val < 0) 3410 return -ENOMEM; 3411 count++; 3412 } 3413 } 3414 3415 /* zero out the remaining RAR entries not used above */ 3416 for (; rar_entries > 0; rar_entries--) { 3417 ew32(RAH(rar_entries), 0); 3418 ew32(RAL(rar_entries), 0); 3419 } 3420 e1e_flush(); 3421 3422 return count; 3423 } 3424 3425 /** 3426 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3427 * @netdev: network interface device structure 3428 * 3429 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3430 * address list or the network interface flags are updated. This routine is 3431 * responsible for configuring the hardware for proper unicast, multicast, 3432 * promiscuous mode, and all-multi behavior. 3433 **/ 3434 static void e1000e_set_rx_mode(struct net_device *netdev) 3435 { 3436 struct e1000_adapter *adapter = netdev_priv(netdev); 3437 struct e1000_hw *hw = &adapter->hw; 3438 u32 rctl; 3439 3440 if (pm_runtime_suspended(netdev->dev.parent)) 3441 return; 3442 3443 /* Check for Promiscuous and All Multicast modes */ 3444 rctl = er32(RCTL); 3445 3446 /* clear the affected bits */ 3447 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3448 3449 if (netdev->flags & IFF_PROMISC) { 3450 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3451 /* Do not hardware filter VLANs in promisc mode */ 3452 e1000e_vlan_filter_disable(adapter); 3453 } else { 3454 int count; 3455 3456 if (netdev->flags & IFF_ALLMULTI) { 3457 rctl |= E1000_RCTL_MPE; 3458 } else { 3459 /* Write addresses to the MTA, if the attempt fails 3460 * then we should just turn on promiscuous mode so 3461 * that we can at least receive multicast traffic 3462 */ 3463 count = e1000e_write_mc_addr_list(netdev); 3464 if (count < 0) 3465 rctl |= E1000_RCTL_MPE; 3466 } 3467 e1000e_vlan_filter_enable(adapter); 3468 /* Write addresses to available RAR registers, if there is not 3469 * sufficient space to store all the addresses then enable 3470 * unicast promiscuous mode 3471 */ 3472 count = e1000e_write_uc_addr_list(netdev); 3473 if (count < 0) 3474 rctl |= E1000_RCTL_UPE; 3475 } 3476 3477 ew32(RCTL, rctl); 3478 3479 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3480 e1000e_vlan_strip_enable(adapter); 3481 else 3482 e1000e_vlan_strip_disable(adapter); 3483 } 3484 3485 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3486 { 3487 struct e1000_hw *hw = &adapter->hw; 3488 u32 mrqc, rxcsum; 3489 u32 rss_key[10]; 3490 int i; 3491 3492 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3493 for (i = 0; i < 10; i++) 3494 ew32(RSSRK(i), rss_key[i]); 3495 3496 /* Direct all traffic to queue 0 */ 3497 for (i = 0; i < 32; i++) 3498 ew32(RETA(i), 0); 3499 3500 /* Disable raw packet checksumming so that RSS hash is placed in 3501 * descriptor on writeback. 3502 */ 3503 rxcsum = er32(RXCSUM); 3504 rxcsum |= E1000_RXCSUM_PCSD; 3505 3506 ew32(RXCSUM, rxcsum); 3507 3508 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3509 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3510 E1000_MRQC_RSS_FIELD_IPV6 | 3511 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3512 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3513 3514 ew32(MRQC, mrqc); 3515 } 3516 3517 /** 3518 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3519 * @adapter: board private structure 3520 * @timinca: pointer to returned time increment attributes 3521 * 3522 * Get attributes for incrementing the System Time Register SYSTIML/H at 3523 * the default base frequency, and set the cyclecounter shift value. 3524 **/ 3525 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3526 { 3527 struct e1000_hw *hw = &adapter->hw; 3528 u32 incvalue, incperiod, shift; 3529 3530 /* Make sure clock is enabled on I217/I218/I219 before checking 3531 * the frequency 3532 */ 3533 if ((hw->mac.type >= e1000_pch_lpt) && 3534 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3535 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3536 u32 fextnvm7 = er32(FEXTNVM7); 3537 3538 if (!(fextnvm7 & BIT(0))) { 3539 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3540 e1e_flush(); 3541 } 3542 } 3543 3544 switch (hw->mac.type) { 3545 case e1000_pch2lan: 3546 /* Stable 96MHz frequency */ 3547 incperiod = INCPERIOD_96MHZ; 3548 incvalue = INCVALUE_96MHZ; 3549 shift = INCVALUE_SHIFT_96MHZ; 3550 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3551 break; 3552 case e1000_pch_lpt: 3553 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3554 /* Stable 96MHz frequency */ 3555 incperiod = INCPERIOD_96MHZ; 3556 incvalue = INCVALUE_96MHZ; 3557 shift = INCVALUE_SHIFT_96MHZ; 3558 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3559 } else { 3560 /* Stable 25MHz frequency */ 3561 incperiod = INCPERIOD_25MHZ; 3562 incvalue = INCVALUE_25MHZ; 3563 shift = INCVALUE_SHIFT_25MHZ; 3564 adapter->cc.shift = shift; 3565 } 3566 break; 3567 case e1000_pch_spt: 3568 /* Stable 24MHz frequency */ 3569 incperiod = INCPERIOD_24MHZ; 3570 incvalue = INCVALUE_24MHZ; 3571 shift = INCVALUE_SHIFT_24MHZ; 3572 adapter->cc.shift = shift; 3573 break; 3574 case e1000_pch_cnp: 3575 case e1000_pch_tgp: 3576 case e1000_pch_adp: 3577 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3578 /* Stable 24MHz frequency */ 3579 incperiod = INCPERIOD_24MHZ; 3580 incvalue = INCVALUE_24MHZ; 3581 shift = INCVALUE_SHIFT_24MHZ; 3582 adapter->cc.shift = shift; 3583 } else { 3584 /* Stable 38400KHz frequency */ 3585 incperiod = INCPERIOD_38400KHZ; 3586 incvalue = INCVALUE_38400KHZ; 3587 shift = INCVALUE_SHIFT_38400KHZ; 3588 adapter->cc.shift = shift; 3589 } 3590 break; 3591 case e1000_82574: 3592 case e1000_82583: 3593 /* Stable 25MHz frequency */ 3594 incperiod = INCPERIOD_25MHZ; 3595 incvalue = INCVALUE_25MHZ; 3596 shift = INCVALUE_SHIFT_25MHZ; 3597 adapter->cc.shift = shift; 3598 break; 3599 default: 3600 return -EINVAL; 3601 } 3602 3603 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3604 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3605 3606 return 0; 3607 } 3608 3609 /** 3610 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3611 * @adapter: board private structure 3612 * 3613 * Outgoing time stamping can be enabled and disabled. Play nice and 3614 * disable it when requested, although it shouldn't cause any overhead 3615 * when no packet needs it. At most one packet in the queue may be 3616 * marked for time stamping, otherwise it would be impossible to tell 3617 * for sure to which packet the hardware time stamp belongs. 3618 * 3619 * Incoming time stamping has to be configured via the hardware filters. 3620 * Not all combinations are supported, in particular event type has to be 3621 * specified. Matching the kind of event packet is not supported, with the 3622 * exception of "all V2 events regardless of level 2 or 4". 3623 **/ 3624 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3625 struct hwtstamp_config *config) 3626 { 3627 struct e1000_hw *hw = &adapter->hw; 3628 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3629 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3630 u32 rxmtrl = 0; 3631 u16 rxudp = 0; 3632 bool is_l4 = false; 3633 bool is_l2 = false; 3634 u32 regval; 3635 3636 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3637 return -EINVAL; 3638 3639 /* flags reserved for future extensions - must be zero */ 3640 if (config->flags) 3641 return -EINVAL; 3642 3643 switch (config->tx_type) { 3644 case HWTSTAMP_TX_OFF: 3645 tsync_tx_ctl = 0; 3646 break; 3647 case HWTSTAMP_TX_ON: 3648 break; 3649 default: 3650 return -ERANGE; 3651 } 3652 3653 switch (config->rx_filter) { 3654 case HWTSTAMP_FILTER_NONE: 3655 tsync_rx_ctl = 0; 3656 break; 3657 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3659 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3660 is_l4 = true; 3661 break; 3662 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3663 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3664 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3665 is_l4 = true; 3666 break; 3667 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3668 /* Also time stamps V2 L2 Path Delay Request/Response */ 3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3670 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3671 is_l2 = true; 3672 break; 3673 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3674 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3675 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3676 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3677 is_l2 = true; 3678 break; 3679 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3680 /* Hardware cannot filter just V2 L4 Sync messages; 3681 * fall-through to V2 (both L2 and L4) Sync. 3682 */ 3683 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3684 /* Also time stamps V2 Path Delay Request/Response. */ 3685 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3686 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3687 is_l2 = true; 3688 is_l4 = true; 3689 break; 3690 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3691 /* Hardware cannot filter just V2 L4 Delay Request messages; 3692 * fall-through to V2 (both L2 and L4) Delay Request. 3693 */ 3694 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3695 /* Also time stamps V2 Path Delay Request/Response. */ 3696 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3697 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3698 is_l2 = true; 3699 is_l4 = true; 3700 break; 3701 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3702 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3703 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3704 * fall-through to all V2 (both L2 and L4) Events. 3705 */ 3706 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3707 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3708 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3709 is_l2 = true; 3710 is_l4 = true; 3711 break; 3712 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3713 /* For V1, the hardware can only filter Sync messages or 3714 * Delay Request messages but not both so fall-through to 3715 * time stamp all packets. 3716 */ 3717 case HWTSTAMP_FILTER_NTP_ALL: 3718 case HWTSTAMP_FILTER_ALL: 3719 is_l2 = true; 3720 is_l4 = true; 3721 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3722 config->rx_filter = HWTSTAMP_FILTER_ALL; 3723 break; 3724 default: 3725 return -ERANGE; 3726 } 3727 3728 adapter->hwtstamp_config = *config; 3729 3730 /* enable/disable Tx h/w time stamping */ 3731 regval = er32(TSYNCTXCTL); 3732 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3733 regval |= tsync_tx_ctl; 3734 ew32(TSYNCTXCTL, regval); 3735 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3736 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3737 e_err("Timesync Tx Control register not set as expected\n"); 3738 return -EAGAIN; 3739 } 3740 3741 /* enable/disable Rx h/w time stamping */ 3742 regval = er32(TSYNCRXCTL); 3743 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3744 regval |= tsync_rx_ctl; 3745 ew32(TSYNCRXCTL, regval); 3746 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3747 E1000_TSYNCRXCTL_TYPE_MASK)) != 3748 (regval & (E1000_TSYNCRXCTL_ENABLED | 3749 E1000_TSYNCRXCTL_TYPE_MASK))) { 3750 e_err("Timesync Rx Control register not set as expected\n"); 3751 return -EAGAIN; 3752 } 3753 3754 /* L2: define ethertype filter for time stamped packets */ 3755 if (is_l2) 3756 rxmtrl |= ETH_P_1588; 3757 3758 /* define which PTP packets get time stamped */ 3759 ew32(RXMTRL, rxmtrl); 3760 3761 /* Filter by destination port */ 3762 if (is_l4) { 3763 rxudp = PTP_EV_PORT; 3764 cpu_to_be16s(&rxudp); 3765 } 3766 ew32(RXUDP, rxudp); 3767 3768 e1e_flush(); 3769 3770 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3771 er32(RXSTMPH); 3772 er32(TXSTMPH); 3773 3774 return 0; 3775 } 3776 3777 /** 3778 * e1000_configure - configure the hardware for Rx and Tx 3779 * @adapter: private board structure 3780 **/ 3781 static void e1000_configure(struct e1000_adapter *adapter) 3782 { 3783 struct e1000_ring *rx_ring = adapter->rx_ring; 3784 3785 e1000e_set_rx_mode(adapter->netdev); 3786 3787 e1000_restore_vlan(adapter); 3788 e1000_init_manageability_pt(adapter); 3789 3790 e1000_configure_tx(adapter); 3791 3792 if (adapter->netdev->features & NETIF_F_RXHASH) 3793 e1000e_setup_rss_hash(adapter); 3794 e1000_setup_rctl(adapter); 3795 e1000_configure_rx(adapter); 3796 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3797 } 3798 3799 /** 3800 * e1000e_power_up_phy - restore link in case the phy was powered down 3801 * @adapter: address of board private structure 3802 * 3803 * The phy may be powered down to save power and turn off link when the 3804 * driver is unloaded and wake on lan is not enabled (among others) 3805 * *** this routine MUST be followed by a call to e1000e_reset *** 3806 **/ 3807 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3808 { 3809 if (adapter->hw.phy.ops.power_up) 3810 adapter->hw.phy.ops.power_up(&adapter->hw); 3811 3812 adapter->hw.mac.ops.setup_link(&adapter->hw); 3813 } 3814 3815 /** 3816 * e1000_power_down_phy - Power down the PHY 3817 * 3818 * Power down the PHY so no link is implied when interface is down. 3819 * The PHY cannot be powered down if management or WoL is active. 3820 */ 3821 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3822 { 3823 if (adapter->hw.phy.ops.power_down) 3824 adapter->hw.phy.ops.power_down(&adapter->hw); 3825 } 3826 3827 /** 3828 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3829 * 3830 * We want to clear all pending descriptors from the TX ring. 3831 * zeroing happens when the HW reads the regs. We assign the ring itself as 3832 * the data of the next descriptor. We don't care about the data we are about 3833 * to reset the HW. 3834 */ 3835 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3836 { 3837 struct e1000_hw *hw = &adapter->hw; 3838 struct e1000_ring *tx_ring = adapter->tx_ring; 3839 struct e1000_tx_desc *tx_desc = NULL; 3840 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3841 u16 size = 512; 3842 3843 tctl = er32(TCTL); 3844 ew32(TCTL, tctl | E1000_TCTL_EN); 3845 tdt = er32(TDT(0)); 3846 BUG_ON(tdt != tx_ring->next_to_use); 3847 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3848 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3849 3850 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3851 tx_desc->upper.data = 0; 3852 /* flush descriptors to memory before notifying the HW */ 3853 wmb(); 3854 tx_ring->next_to_use++; 3855 if (tx_ring->next_to_use == tx_ring->count) 3856 tx_ring->next_to_use = 0; 3857 ew32(TDT(0), tx_ring->next_to_use); 3858 usleep_range(200, 250); 3859 } 3860 3861 /** 3862 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3863 * 3864 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3865 */ 3866 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3867 { 3868 u32 rctl, rxdctl; 3869 struct e1000_hw *hw = &adapter->hw; 3870 3871 rctl = er32(RCTL); 3872 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3873 e1e_flush(); 3874 usleep_range(100, 150); 3875 3876 rxdctl = er32(RXDCTL(0)); 3877 /* zero the lower 14 bits (prefetch and host thresholds) */ 3878 rxdctl &= 0xffffc000; 3879 3880 /* update thresholds: prefetch threshold to 31, host threshold to 1 3881 * and make sure the granularity is "descriptors" and not "cache lines" 3882 */ 3883 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3884 3885 ew32(RXDCTL(0), rxdctl); 3886 /* momentarily enable the RX ring for the changes to take effect */ 3887 ew32(RCTL, rctl | E1000_RCTL_EN); 3888 e1e_flush(); 3889 usleep_range(100, 150); 3890 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3891 } 3892 3893 /** 3894 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3895 * 3896 * In i219, the descriptor rings must be emptied before resetting the HW 3897 * or before changing the device state to D3 during runtime (runtime PM). 3898 * 3899 * Failure to do this will cause the HW to enter a unit hang state which can 3900 * only be released by PCI reset on the device 3901 * 3902 */ 3903 3904 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3905 { 3906 u16 hang_state; 3907 u32 fext_nvm11, tdlen; 3908 struct e1000_hw *hw = &adapter->hw; 3909 3910 /* First, disable MULR fix in FEXTNVM11 */ 3911 fext_nvm11 = er32(FEXTNVM11); 3912 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3913 ew32(FEXTNVM11, fext_nvm11); 3914 /* do nothing if we're not in faulty state, or if the queue is empty */ 3915 tdlen = er32(TDLEN(0)); 3916 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3917 &hang_state); 3918 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3919 return; 3920 e1000_flush_tx_ring(adapter); 3921 /* recheck, maybe the fault is caused by the rx ring */ 3922 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3923 &hang_state); 3924 if (hang_state & FLUSH_DESC_REQUIRED) 3925 e1000_flush_rx_ring(adapter); 3926 } 3927 3928 /** 3929 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3930 * @adapter: board private structure 3931 * 3932 * When the MAC is reset, all hardware bits for timesync will be reset to the 3933 * default values. This function will restore the settings last in place. 3934 * Since the clock SYSTIME registers are reset, we will simply restore the 3935 * cyclecounter to the kernel real clock time. 3936 **/ 3937 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3938 { 3939 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3940 struct e1000_hw *hw = &adapter->hw; 3941 unsigned long flags; 3942 u32 timinca; 3943 s32 ret_val; 3944 3945 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3946 return; 3947 3948 if (info->adjfreq) { 3949 /* restore the previous ptp frequency delta */ 3950 ret_val = info->adjfreq(info, adapter->ptp_delta); 3951 } else { 3952 /* set the default base frequency if no adjustment possible */ 3953 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3954 if (!ret_val) 3955 ew32(TIMINCA, timinca); 3956 } 3957 3958 if (ret_val) { 3959 dev_warn(&adapter->pdev->dev, 3960 "Failed to restore TIMINCA clock rate delta: %d\n", 3961 ret_val); 3962 return; 3963 } 3964 3965 /* reset the systim ns time counter */ 3966 spin_lock_irqsave(&adapter->systim_lock, flags); 3967 timecounter_init(&adapter->tc, &adapter->cc, 3968 ktime_to_ns(ktime_get_real())); 3969 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3970 3971 /* restore the previous hwtstamp configuration settings */ 3972 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3973 } 3974 3975 /** 3976 * e1000e_reset - bring the hardware into a known good state 3977 * 3978 * This function boots the hardware and enables some settings that 3979 * require a configuration cycle of the hardware - those cannot be 3980 * set/changed during runtime. After reset the device needs to be 3981 * properly configured for Rx, Tx etc. 3982 */ 3983 void e1000e_reset(struct e1000_adapter *adapter) 3984 { 3985 struct e1000_mac_info *mac = &adapter->hw.mac; 3986 struct e1000_fc_info *fc = &adapter->hw.fc; 3987 struct e1000_hw *hw = &adapter->hw; 3988 u32 tx_space, min_tx_space, min_rx_space; 3989 u32 pba = adapter->pba; 3990 u16 hwm; 3991 3992 /* reset Packet Buffer Allocation to default */ 3993 ew32(PBA, pba); 3994 3995 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3996 /* To maintain wire speed transmits, the Tx FIFO should be 3997 * large enough to accommodate two full transmit packets, 3998 * rounded up to the next 1KB and expressed in KB. Likewise, 3999 * the Rx FIFO should be large enough to accommodate at least 4000 * one full receive packet and is similarly rounded up and 4001 * expressed in KB. 4002 */ 4003 pba = er32(PBA); 4004 /* upper 16 bits has Tx packet buffer allocation size in KB */ 4005 tx_space = pba >> 16; 4006 /* lower 16 bits has Rx packet buffer allocation size in KB */ 4007 pba &= 0xffff; 4008 /* the Tx fifo also stores 16 bytes of information about the Tx 4009 * but don't include ethernet FCS because hardware appends it 4010 */ 4011 min_tx_space = (adapter->max_frame_size + 4012 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 4013 min_tx_space = ALIGN(min_tx_space, 1024); 4014 min_tx_space >>= 10; 4015 /* software strips receive CRC, so leave room for it */ 4016 min_rx_space = adapter->max_frame_size; 4017 min_rx_space = ALIGN(min_rx_space, 1024); 4018 min_rx_space >>= 10; 4019 4020 /* If current Tx allocation is less than the min Tx FIFO size, 4021 * and the min Tx FIFO size is less than the current Rx FIFO 4022 * allocation, take space away from current Rx allocation 4023 */ 4024 if ((tx_space < min_tx_space) && 4025 ((min_tx_space - tx_space) < pba)) { 4026 pba -= min_tx_space - tx_space; 4027 4028 /* if short on Rx space, Rx wins and must trump Tx 4029 * adjustment 4030 */ 4031 if (pba < min_rx_space) 4032 pba = min_rx_space; 4033 } 4034 4035 ew32(PBA, pba); 4036 } 4037 4038 /* flow control settings 4039 * 4040 * The high water mark must be low enough to fit one full frame 4041 * (or the size used for early receive) above it in the Rx FIFO. 4042 * Set it to the lower of: 4043 * - 90% of the Rx FIFO size, and 4044 * - the full Rx FIFO size minus one full frame 4045 */ 4046 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4047 fc->pause_time = 0xFFFF; 4048 else 4049 fc->pause_time = E1000_FC_PAUSE_TIME; 4050 fc->send_xon = true; 4051 fc->current_mode = fc->requested_mode; 4052 4053 switch (hw->mac.type) { 4054 case e1000_ich9lan: 4055 case e1000_ich10lan: 4056 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4057 pba = 14; 4058 ew32(PBA, pba); 4059 fc->high_water = 0x2800; 4060 fc->low_water = fc->high_water - 8; 4061 break; 4062 } 4063 /* fall-through */ 4064 default: 4065 hwm = min(((pba << 10) * 9 / 10), 4066 ((pba << 10) - adapter->max_frame_size)); 4067 4068 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4069 fc->low_water = fc->high_water - 8; 4070 break; 4071 case e1000_pchlan: 4072 /* Workaround PCH LOM adapter hangs with certain network 4073 * loads. If hangs persist, try disabling Tx flow control. 4074 */ 4075 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4076 fc->high_water = 0x3500; 4077 fc->low_water = 0x1500; 4078 } else { 4079 fc->high_water = 0x5000; 4080 fc->low_water = 0x3000; 4081 } 4082 fc->refresh_time = 0x1000; 4083 break; 4084 case e1000_pch2lan: 4085 case e1000_pch_lpt: 4086 case e1000_pch_spt: 4087 case e1000_pch_cnp: 4088 /* fall-through */ 4089 case e1000_pch_tgp: 4090 case e1000_pch_adp: 4091 fc->refresh_time = 0xFFFF; 4092 fc->pause_time = 0xFFFF; 4093 4094 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4095 fc->high_water = 0x05C20; 4096 fc->low_water = 0x05048; 4097 break; 4098 } 4099 4100 pba = 14; 4101 ew32(PBA, pba); 4102 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4103 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4104 break; 4105 } 4106 4107 /* Alignment of Tx data is on an arbitrary byte boundary with the 4108 * maximum size per Tx descriptor limited only to the transmit 4109 * allocation of the packet buffer minus 96 bytes with an upper 4110 * limit of 24KB due to receive synchronization limitations. 4111 */ 4112 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4113 24 << 10); 4114 4115 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4116 * fit in receive buffer. 4117 */ 4118 if (adapter->itr_setting & 0x3) { 4119 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4120 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4121 dev_info(&adapter->pdev->dev, 4122 "Interrupt Throttle Rate off\n"); 4123 adapter->flags2 |= FLAG2_DISABLE_AIM; 4124 e1000e_write_itr(adapter, 0); 4125 } 4126 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4127 dev_info(&adapter->pdev->dev, 4128 "Interrupt Throttle Rate on\n"); 4129 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4130 adapter->itr = 20000; 4131 e1000e_write_itr(adapter, adapter->itr); 4132 } 4133 } 4134 4135 if (hw->mac.type >= e1000_pch_spt) 4136 e1000_flush_desc_rings(adapter); 4137 /* Allow time for pending master requests to run */ 4138 mac->ops.reset_hw(hw); 4139 4140 /* For parts with AMT enabled, let the firmware know 4141 * that the network interface is in control 4142 */ 4143 if (adapter->flags & FLAG_HAS_AMT) 4144 e1000e_get_hw_control(adapter); 4145 4146 ew32(WUC, 0); 4147 4148 if (mac->ops.init_hw(hw)) 4149 e_err("Hardware Error\n"); 4150 4151 e1000_update_mng_vlan(adapter); 4152 4153 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4154 ew32(VET, ETH_P_8021Q); 4155 4156 e1000e_reset_adaptive(hw); 4157 4158 /* restore systim and hwtstamp settings */ 4159 e1000e_systim_reset(adapter); 4160 4161 /* Set EEE advertisement as appropriate */ 4162 if (adapter->flags2 & FLAG2_HAS_EEE) { 4163 s32 ret_val; 4164 u16 adv_addr; 4165 4166 switch (hw->phy.type) { 4167 case e1000_phy_82579: 4168 adv_addr = I82579_EEE_ADVERTISEMENT; 4169 break; 4170 case e1000_phy_i217: 4171 adv_addr = I217_EEE_ADVERTISEMENT; 4172 break; 4173 default: 4174 dev_err(&adapter->pdev->dev, 4175 "Invalid PHY type setting EEE advertisement\n"); 4176 return; 4177 } 4178 4179 ret_val = hw->phy.ops.acquire(hw); 4180 if (ret_val) { 4181 dev_err(&adapter->pdev->dev, 4182 "EEE advertisement - unable to acquire PHY\n"); 4183 return; 4184 } 4185 4186 e1000_write_emi_reg_locked(hw, adv_addr, 4187 hw->dev_spec.ich8lan.eee_disable ? 4188 0 : adapter->eee_advert); 4189 4190 hw->phy.ops.release(hw); 4191 } 4192 4193 if (!netif_running(adapter->netdev) && 4194 !test_bit(__E1000_TESTING, &adapter->state)) 4195 e1000_power_down_phy(adapter); 4196 4197 e1000_get_phy_info(hw); 4198 4199 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4200 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4201 u16 phy_data = 0; 4202 /* speed up time to link by disabling smart power down, ignore 4203 * the return value of this function because there is nothing 4204 * different we would do if it failed 4205 */ 4206 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4207 phy_data &= ~IGP02E1000_PM_SPD; 4208 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4209 } 4210 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4211 u32 reg; 4212 4213 /* Fextnvm7 @ 0xe4[2] = 1 */ 4214 reg = er32(FEXTNVM7); 4215 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4216 ew32(FEXTNVM7, reg); 4217 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4218 reg = er32(FEXTNVM9); 4219 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4220 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4221 ew32(FEXTNVM9, reg); 4222 } 4223 4224 } 4225 4226 /** 4227 * e1000e_trigger_lsc - trigger an LSC interrupt 4228 * @adapter: 4229 * 4230 * Fire a link status change interrupt to start the watchdog. 4231 **/ 4232 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4233 { 4234 struct e1000_hw *hw = &adapter->hw; 4235 4236 if (adapter->msix_entries) 4237 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4238 else 4239 ew32(ICS, E1000_ICS_LSC); 4240 } 4241 4242 void e1000e_up(struct e1000_adapter *adapter) 4243 { 4244 /* hardware has been reset, we need to reload some things */ 4245 e1000_configure(adapter); 4246 4247 clear_bit(__E1000_DOWN, &adapter->state); 4248 4249 if (adapter->msix_entries) 4250 e1000_configure_msix(adapter); 4251 e1000_irq_enable(adapter); 4252 4253 /* Tx queue started by watchdog timer when link is up */ 4254 4255 e1000e_trigger_lsc(adapter); 4256 } 4257 4258 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4259 { 4260 struct e1000_hw *hw = &adapter->hw; 4261 4262 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4263 return; 4264 4265 /* flush pending descriptor writebacks to memory */ 4266 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4267 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4268 4269 /* execute the writes immediately */ 4270 e1e_flush(); 4271 4272 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4273 * write is successful 4274 */ 4275 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4276 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4277 4278 /* execute the writes immediately */ 4279 e1e_flush(); 4280 } 4281 4282 static void e1000e_update_stats(struct e1000_adapter *adapter); 4283 4284 /** 4285 * e1000e_down - quiesce the device and optionally reset the hardware 4286 * @adapter: board private structure 4287 * @reset: boolean flag to reset the hardware or not 4288 */ 4289 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4290 { 4291 struct net_device *netdev = adapter->netdev; 4292 struct e1000_hw *hw = &adapter->hw; 4293 u32 tctl, rctl; 4294 4295 /* signal that we're down so the interrupt handler does not 4296 * reschedule our watchdog timer 4297 */ 4298 set_bit(__E1000_DOWN, &adapter->state); 4299 4300 netif_carrier_off(netdev); 4301 4302 /* disable receives in the hardware */ 4303 rctl = er32(RCTL); 4304 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4305 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4306 /* flush and sleep below */ 4307 4308 netif_stop_queue(netdev); 4309 4310 /* disable transmits in the hardware */ 4311 tctl = er32(TCTL); 4312 tctl &= ~E1000_TCTL_EN; 4313 ew32(TCTL, tctl); 4314 4315 /* flush both disables and wait for them to finish */ 4316 e1e_flush(); 4317 usleep_range(10000, 11000); 4318 4319 e1000_irq_disable(adapter); 4320 4321 napi_synchronize(&adapter->napi); 4322 4323 del_timer_sync(&adapter->watchdog_timer); 4324 del_timer_sync(&adapter->phy_info_timer); 4325 4326 spin_lock(&adapter->stats64_lock); 4327 e1000e_update_stats(adapter); 4328 spin_unlock(&adapter->stats64_lock); 4329 4330 e1000e_flush_descriptors(adapter); 4331 4332 adapter->link_speed = 0; 4333 adapter->link_duplex = 0; 4334 4335 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4336 if ((hw->mac.type >= e1000_pch2lan) && 4337 (adapter->netdev->mtu > ETH_DATA_LEN) && 4338 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4339 e_dbg("failed to disable jumbo frame workaround mode\n"); 4340 4341 if (!pci_channel_offline(adapter->pdev)) { 4342 if (reset) 4343 e1000e_reset(adapter); 4344 else if (hw->mac.type >= e1000_pch_spt) 4345 e1000_flush_desc_rings(adapter); 4346 } 4347 e1000_clean_tx_ring(adapter->tx_ring); 4348 e1000_clean_rx_ring(adapter->rx_ring); 4349 } 4350 4351 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4352 { 4353 might_sleep(); 4354 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4355 usleep_range(1000, 1100); 4356 e1000e_down(adapter, true); 4357 e1000e_up(adapter); 4358 clear_bit(__E1000_RESETTING, &adapter->state); 4359 } 4360 4361 /** 4362 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4363 * @hw: pointer to the HW structure 4364 * @systim: PHC time value read, sanitized and returned 4365 * @sts: structure to hold system time before and after reading SYSTIML, 4366 * may be NULL 4367 * 4368 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4369 * check to see that the time is incrementing at a reasonable 4370 * rate and is a multiple of incvalue. 4371 **/ 4372 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4373 struct ptp_system_timestamp *sts) 4374 { 4375 u64 time_delta, rem, temp; 4376 u64 systim_next; 4377 u32 incvalue; 4378 int i; 4379 4380 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4381 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4382 /* latch SYSTIMH on read of SYSTIML */ 4383 ptp_read_system_prets(sts); 4384 systim_next = (u64)er32(SYSTIML); 4385 ptp_read_system_postts(sts); 4386 systim_next |= (u64)er32(SYSTIMH) << 32; 4387 4388 time_delta = systim_next - systim; 4389 temp = time_delta; 4390 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4391 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4392 4393 systim = systim_next; 4394 4395 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4396 break; 4397 } 4398 4399 return systim; 4400 } 4401 4402 /** 4403 * e1000e_read_systim - read SYSTIM register 4404 * @adapter: board private structure 4405 * @sts: structure which will contain system time before and after reading 4406 * SYSTIML, may be NULL 4407 **/ 4408 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4409 struct ptp_system_timestamp *sts) 4410 { 4411 struct e1000_hw *hw = &adapter->hw; 4412 u32 systimel, systimel_2, systimeh; 4413 u64 systim; 4414 /* SYSTIMH latching upon SYSTIML read does not work well. 4415 * This means that if SYSTIML overflows after we read it but before 4416 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4417 * will experience a huge non linear increment in the systime value 4418 * to fix that we test for overflow and if true, we re-read systime. 4419 */ 4420 ptp_read_system_prets(sts); 4421 systimel = er32(SYSTIML); 4422 ptp_read_system_postts(sts); 4423 systimeh = er32(SYSTIMH); 4424 /* Is systimel is so large that overflow is possible? */ 4425 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4426 ptp_read_system_prets(sts); 4427 systimel_2 = er32(SYSTIML); 4428 ptp_read_system_postts(sts); 4429 if (systimel > systimel_2) { 4430 /* There was an overflow, read again SYSTIMH, and use 4431 * systimel_2 4432 */ 4433 systimeh = er32(SYSTIMH); 4434 systimel = systimel_2; 4435 } 4436 } 4437 systim = (u64)systimel; 4438 systim |= (u64)systimeh << 32; 4439 4440 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4441 systim = e1000e_sanitize_systim(hw, systim, sts); 4442 4443 return systim; 4444 } 4445 4446 /** 4447 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4448 * @cc: cyclecounter structure 4449 **/ 4450 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4451 { 4452 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4453 cc); 4454 4455 return e1000e_read_systim(adapter, NULL); 4456 } 4457 4458 /** 4459 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4460 * @adapter: board private structure to initialize 4461 * 4462 * e1000_sw_init initializes the Adapter private data structure. 4463 * Fields are initialized based on PCI device information and 4464 * OS network device settings (MTU size). 4465 **/ 4466 static int e1000_sw_init(struct e1000_adapter *adapter) 4467 { 4468 struct net_device *netdev = adapter->netdev; 4469 4470 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4471 adapter->rx_ps_bsize0 = 128; 4472 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4473 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4474 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4475 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4476 4477 spin_lock_init(&adapter->stats64_lock); 4478 4479 e1000e_set_interrupt_capability(adapter); 4480 4481 if (e1000_alloc_queues(adapter)) 4482 return -ENOMEM; 4483 4484 /* Setup hardware time stamping cyclecounter */ 4485 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4486 adapter->cc.read = e1000e_cyclecounter_read; 4487 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4488 adapter->cc.mult = 1; 4489 /* cc.shift set in e1000e_get_base_tininca() */ 4490 4491 spin_lock_init(&adapter->systim_lock); 4492 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4493 } 4494 4495 /* Explicitly disable IRQ since the NIC can be in any state. */ 4496 e1000_irq_disable(adapter); 4497 4498 set_bit(__E1000_DOWN, &adapter->state); 4499 return 0; 4500 } 4501 4502 /** 4503 * e1000_intr_msi_test - Interrupt Handler 4504 * @irq: interrupt number 4505 * @data: pointer to a network interface device structure 4506 **/ 4507 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4508 { 4509 struct net_device *netdev = data; 4510 struct e1000_adapter *adapter = netdev_priv(netdev); 4511 struct e1000_hw *hw = &adapter->hw; 4512 u32 icr = er32(ICR); 4513 4514 e_dbg("icr is %08X\n", icr); 4515 if (icr & E1000_ICR_RXSEQ) { 4516 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4517 /* Force memory writes to complete before acknowledging the 4518 * interrupt is handled. 4519 */ 4520 wmb(); 4521 } 4522 4523 return IRQ_HANDLED; 4524 } 4525 4526 /** 4527 * e1000_test_msi_interrupt - Returns 0 for successful test 4528 * @adapter: board private struct 4529 * 4530 * code flow taken from tg3.c 4531 **/ 4532 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4533 { 4534 struct net_device *netdev = adapter->netdev; 4535 struct e1000_hw *hw = &adapter->hw; 4536 int err; 4537 4538 /* poll_enable hasn't been called yet, so don't need disable */ 4539 /* clear any pending events */ 4540 er32(ICR); 4541 4542 /* free the real vector and request a test handler */ 4543 e1000_free_irq(adapter); 4544 e1000e_reset_interrupt_capability(adapter); 4545 4546 /* Assume that the test fails, if it succeeds then the test 4547 * MSI irq handler will unset this flag 4548 */ 4549 adapter->flags |= FLAG_MSI_TEST_FAILED; 4550 4551 err = pci_enable_msi(adapter->pdev); 4552 if (err) 4553 goto msi_test_failed; 4554 4555 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4556 netdev->name, netdev); 4557 if (err) { 4558 pci_disable_msi(adapter->pdev); 4559 goto msi_test_failed; 4560 } 4561 4562 /* Force memory writes to complete before enabling and firing an 4563 * interrupt. 4564 */ 4565 wmb(); 4566 4567 e1000_irq_enable(adapter); 4568 4569 /* fire an unusual interrupt on the test handler */ 4570 ew32(ICS, E1000_ICS_RXSEQ); 4571 e1e_flush(); 4572 msleep(100); 4573 4574 e1000_irq_disable(adapter); 4575 4576 rmb(); /* read flags after interrupt has been fired */ 4577 4578 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4579 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4580 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4581 } else { 4582 e_dbg("MSI interrupt test succeeded!\n"); 4583 } 4584 4585 free_irq(adapter->pdev->irq, netdev); 4586 pci_disable_msi(adapter->pdev); 4587 4588 msi_test_failed: 4589 e1000e_set_interrupt_capability(adapter); 4590 return e1000_request_irq(adapter); 4591 } 4592 4593 /** 4594 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4595 * @adapter: board private struct 4596 * 4597 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4598 **/ 4599 static int e1000_test_msi(struct e1000_adapter *adapter) 4600 { 4601 int err; 4602 u16 pci_cmd; 4603 4604 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4605 return 0; 4606 4607 /* disable SERR in case the MSI write causes a master abort */ 4608 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4609 if (pci_cmd & PCI_COMMAND_SERR) 4610 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4611 pci_cmd & ~PCI_COMMAND_SERR); 4612 4613 err = e1000_test_msi_interrupt(adapter); 4614 4615 /* re-enable SERR */ 4616 if (pci_cmd & PCI_COMMAND_SERR) { 4617 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4618 pci_cmd |= PCI_COMMAND_SERR; 4619 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4620 } 4621 4622 return err; 4623 } 4624 4625 /** 4626 * e1000e_open - Called when a network interface is made active 4627 * @netdev: network interface device structure 4628 * 4629 * Returns 0 on success, negative value on failure 4630 * 4631 * The open entry point is called when a network interface is made 4632 * active by the system (IFF_UP). At this point all resources needed 4633 * for transmit and receive operations are allocated, the interrupt 4634 * handler is registered with the OS, the watchdog timer is started, 4635 * and the stack is notified that the interface is ready. 4636 **/ 4637 int e1000e_open(struct net_device *netdev) 4638 { 4639 struct e1000_adapter *adapter = netdev_priv(netdev); 4640 struct e1000_hw *hw = &adapter->hw; 4641 struct pci_dev *pdev = adapter->pdev; 4642 int err; 4643 4644 /* disallow open during test */ 4645 if (test_bit(__E1000_TESTING, &adapter->state)) 4646 return -EBUSY; 4647 4648 pm_runtime_get_sync(&pdev->dev); 4649 4650 netif_carrier_off(netdev); 4651 netif_stop_queue(netdev); 4652 4653 /* allocate transmit descriptors */ 4654 err = e1000e_setup_tx_resources(adapter->tx_ring); 4655 if (err) 4656 goto err_setup_tx; 4657 4658 /* allocate receive descriptors */ 4659 err = e1000e_setup_rx_resources(adapter->rx_ring); 4660 if (err) 4661 goto err_setup_rx; 4662 4663 /* If AMT is enabled, let the firmware know that the network 4664 * interface is now open and reset the part to a known state. 4665 */ 4666 if (adapter->flags & FLAG_HAS_AMT) { 4667 e1000e_get_hw_control(adapter); 4668 e1000e_reset(adapter); 4669 } 4670 4671 e1000e_power_up_phy(adapter); 4672 4673 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4674 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4675 e1000_update_mng_vlan(adapter); 4676 4677 /* DMA latency requirement to workaround jumbo issue */ 4678 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4679 4680 /* before we allocate an interrupt, we must be ready to handle it. 4681 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4682 * as soon as we call pci_request_irq, so we have to setup our 4683 * clean_rx handler before we do so. 4684 */ 4685 e1000_configure(adapter); 4686 4687 err = e1000_request_irq(adapter); 4688 if (err) 4689 goto err_req_irq; 4690 4691 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4692 * ignore e1000e MSI messages, which means we need to test our MSI 4693 * interrupt now 4694 */ 4695 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4696 err = e1000_test_msi(adapter); 4697 if (err) { 4698 e_err("Interrupt allocation failed\n"); 4699 goto err_req_irq; 4700 } 4701 } 4702 4703 /* From here on the code is the same as e1000e_up() */ 4704 clear_bit(__E1000_DOWN, &adapter->state); 4705 4706 napi_enable(&adapter->napi); 4707 4708 e1000_irq_enable(adapter); 4709 4710 adapter->tx_hang_recheck = false; 4711 4712 hw->mac.get_link_status = true; 4713 pm_runtime_put(&pdev->dev); 4714 4715 e1000e_trigger_lsc(adapter); 4716 4717 return 0; 4718 4719 err_req_irq: 4720 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4721 e1000e_release_hw_control(adapter); 4722 e1000_power_down_phy(adapter); 4723 e1000e_free_rx_resources(adapter->rx_ring); 4724 err_setup_rx: 4725 e1000e_free_tx_resources(adapter->tx_ring); 4726 err_setup_tx: 4727 e1000e_reset(adapter); 4728 pm_runtime_put_sync(&pdev->dev); 4729 4730 return err; 4731 } 4732 4733 /** 4734 * e1000e_close - Disables a network interface 4735 * @netdev: network interface device structure 4736 * 4737 * Returns 0, this is not allowed to fail 4738 * 4739 * The close entry point is called when an interface is de-activated 4740 * by the OS. The hardware is still under the drivers control, but 4741 * needs to be disabled. A global MAC reset is issued to stop the 4742 * hardware, and all transmit and receive resources are freed. 4743 **/ 4744 int e1000e_close(struct net_device *netdev) 4745 { 4746 struct e1000_adapter *adapter = netdev_priv(netdev); 4747 struct pci_dev *pdev = adapter->pdev; 4748 int count = E1000_CHECK_RESET_COUNT; 4749 4750 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4751 usleep_range(10000, 11000); 4752 4753 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4754 4755 pm_runtime_get_sync(&pdev->dev); 4756 4757 if (netif_device_present(netdev)) { 4758 e1000e_down(adapter, true); 4759 e1000_free_irq(adapter); 4760 4761 /* Link status message must follow this format */ 4762 netdev_info(netdev, "NIC Link is Down\n"); 4763 } 4764 4765 napi_disable(&adapter->napi); 4766 4767 e1000e_free_tx_resources(adapter->tx_ring); 4768 e1000e_free_rx_resources(adapter->rx_ring); 4769 4770 /* kill manageability vlan ID if supported, but not if a vlan with 4771 * the same ID is registered on the host OS (let 8021q kill it) 4772 */ 4773 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4774 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4775 adapter->mng_vlan_id); 4776 4777 /* If AMT is enabled, let the firmware know that the network 4778 * interface is now closed 4779 */ 4780 if ((adapter->flags & FLAG_HAS_AMT) && 4781 !test_bit(__E1000_TESTING, &adapter->state)) 4782 e1000e_release_hw_control(adapter); 4783 4784 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4785 4786 pm_runtime_put_sync(&pdev->dev); 4787 4788 return 0; 4789 } 4790 4791 /** 4792 * e1000_set_mac - Change the Ethernet Address of the NIC 4793 * @netdev: network interface device structure 4794 * @p: pointer to an address structure 4795 * 4796 * Returns 0 on success, negative on failure 4797 **/ 4798 static int e1000_set_mac(struct net_device *netdev, void *p) 4799 { 4800 struct e1000_adapter *adapter = netdev_priv(netdev); 4801 struct e1000_hw *hw = &adapter->hw; 4802 struct sockaddr *addr = p; 4803 4804 if (!is_valid_ether_addr(addr->sa_data)) 4805 return -EADDRNOTAVAIL; 4806 4807 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4808 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4809 4810 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4811 4812 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4813 /* activate the work around */ 4814 e1000e_set_laa_state_82571(&adapter->hw, 1); 4815 4816 /* Hold a copy of the LAA in RAR[14] This is done so that 4817 * between the time RAR[0] gets clobbered and the time it 4818 * gets fixed (in e1000_watchdog), the actual LAA is in one 4819 * of the RARs and no incoming packets directed to this port 4820 * are dropped. Eventually the LAA will be in RAR[0] and 4821 * RAR[14] 4822 */ 4823 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4824 adapter->hw.mac.rar_entry_count - 1); 4825 } 4826 4827 return 0; 4828 } 4829 4830 /** 4831 * e1000e_update_phy_task - work thread to update phy 4832 * @work: pointer to our work struct 4833 * 4834 * this worker thread exists because we must acquire a 4835 * semaphore to read the phy, which we could msleep while 4836 * waiting for it, and we can't msleep in a timer. 4837 **/ 4838 static void e1000e_update_phy_task(struct work_struct *work) 4839 { 4840 struct e1000_adapter *adapter = container_of(work, 4841 struct e1000_adapter, 4842 update_phy_task); 4843 struct e1000_hw *hw = &adapter->hw; 4844 4845 if (test_bit(__E1000_DOWN, &adapter->state)) 4846 return; 4847 4848 e1000_get_phy_info(hw); 4849 4850 /* Enable EEE on 82579 after link up */ 4851 if (hw->phy.type >= e1000_phy_82579) 4852 e1000_set_eee_pchlan(hw); 4853 } 4854 4855 /** 4856 * e1000_update_phy_info - timre call-back to update PHY info 4857 * @data: pointer to adapter cast into an unsigned long 4858 * 4859 * Need to wait a few seconds after link up to get diagnostic information from 4860 * the phy 4861 **/ 4862 static void e1000_update_phy_info(struct timer_list *t) 4863 { 4864 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4865 4866 if (test_bit(__E1000_DOWN, &adapter->state)) 4867 return; 4868 4869 schedule_work(&adapter->update_phy_task); 4870 } 4871 4872 /** 4873 * e1000e_update_phy_stats - Update the PHY statistics counters 4874 * @adapter: board private structure 4875 * 4876 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4877 **/ 4878 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4879 { 4880 struct e1000_hw *hw = &adapter->hw; 4881 s32 ret_val; 4882 u16 phy_data; 4883 4884 ret_val = hw->phy.ops.acquire(hw); 4885 if (ret_val) 4886 return; 4887 4888 /* A page set is expensive so check if already on desired page. 4889 * If not, set to the page with the PHY status registers. 4890 */ 4891 hw->phy.addr = 1; 4892 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4893 &phy_data); 4894 if (ret_val) 4895 goto release; 4896 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4897 ret_val = hw->phy.ops.set_page(hw, 4898 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4899 if (ret_val) 4900 goto release; 4901 } 4902 4903 /* Single Collision Count */ 4904 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4905 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4906 if (!ret_val) 4907 adapter->stats.scc += phy_data; 4908 4909 /* Excessive Collision Count */ 4910 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4911 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4912 if (!ret_val) 4913 adapter->stats.ecol += phy_data; 4914 4915 /* Multiple Collision Count */ 4916 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4917 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4918 if (!ret_val) 4919 adapter->stats.mcc += phy_data; 4920 4921 /* Late Collision Count */ 4922 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4923 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4924 if (!ret_val) 4925 adapter->stats.latecol += phy_data; 4926 4927 /* Collision Count - also used for adaptive IFS */ 4928 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4929 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4930 if (!ret_val) 4931 hw->mac.collision_delta = phy_data; 4932 4933 /* Defer Count */ 4934 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4935 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4936 if (!ret_val) 4937 adapter->stats.dc += phy_data; 4938 4939 /* Transmit with no CRS */ 4940 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4941 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4942 if (!ret_val) 4943 adapter->stats.tncrs += phy_data; 4944 4945 release: 4946 hw->phy.ops.release(hw); 4947 } 4948 4949 /** 4950 * e1000e_update_stats - Update the board statistics counters 4951 * @adapter: board private structure 4952 **/ 4953 static void e1000e_update_stats(struct e1000_adapter *adapter) 4954 { 4955 struct net_device *netdev = adapter->netdev; 4956 struct e1000_hw *hw = &adapter->hw; 4957 struct pci_dev *pdev = adapter->pdev; 4958 4959 /* Prevent stats update while adapter is being reset, or if the pci 4960 * connection is down. 4961 */ 4962 if (adapter->link_speed == 0) 4963 return; 4964 if (pci_channel_offline(pdev)) 4965 return; 4966 4967 adapter->stats.crcerrs += er32(CRCERRS); 4968 adapter->stats.gprc += er32(GPRC); 4969 adapter->stats.gorc += er32(GORCL); 4970 er32(GORCH); /* Clear gorc */ 4971 adapter->stats.bprc += er32(BPRC); 4972 adapter->stats.mprc += er32(MPRC); 4973 adapter->stats.roc += er32(ROC); 4974 4975 adapter->stats.mpc += er32(MPC); 4976 4977 /* Half-duplex statistics */ 4978 if (adapter->link_duplex == HALF_DUPLEX) { 4979 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4980 e1000e_update_phy_stats(adapter); 4981 } else { 4982 adapter->stats.scc += er32(SCC); 4983 adapter->stats.ecol += er32(ECOL); 4984 adapter->stats.mcc += er32(MCC); 4985 adapter->stats.latecol += er32(LATECOL); 4986 adapter->stats.dc += er32(DC); 4987 4988 hw->mac.collision_delta = er32(COLC); 4989 4990 if ((hw->mac.type != e1000_82574) && 4991 (hw->mac.type != e1000_82583)) 4992 adapter->stats.tncrs += er32(TNCRS); 4993 } 4994 adapter->stats.colc += hw->mac.collision_delta; 4995 } 4996 4997 adapter->stats.xonrxc += er32(XONRXC); 4998 adapter->stats.xontxc += er32(XONTXC); 4999 adapter->stats.xoffrxc += er32(XOFFRXC); 5000 adapter->stats.xofftxc += er32(XOFFTXC); 5001 adapter->stats.gptc += er32(GPTC); 5002 adapter->stats.gotc += er32(GOTCL); 5003 er32(GOTCH); /* Clear gotc */ 5004 adapter->stats.rnbc += er32(RNBC); 5005 adapter->stats.ruc += er32(RUC); 5006 5007 adapter->stats.mptc += er32(MPTC); 5008 adapter->stats.bptc += er32(BPTC); 5009 5010 /* used for adaptive IFS */ 5011 5012 hw->mac.tx_packet_delta = er32(TPT); 5013 adapter->stats.tpt += hw->mac.tx_packet_delta; 5014 5015 adapter->stats.algnerrc += er32(ALGNERRC); 5016 adapter->stats.rxerrc += er32(RXERRC); 5017 adapter->stats.cexterr += er32(CEXTERR); 5018 adapter->stats.tsctc += er32(TSCTC); 5019 adapter->stats.tsctfc += er32(TSCTFC); 5020 5021 /* Fill out the OS statistics structure */ 5022 netdev->stats.multicast = adapter->stats.mprc; 5023 netdev->stats.collisions = adapter->stats.colc; 5024 5025 /* Rx Errors */ 5026 5027 /* RLEC on some newer hardware can be incorrect so build 5028 * our own version based on RUC and ROC 5029 */ 5030 netdev->stats.rx_errors = adapter->stats.rxerrc + 5031 adapter->stats.crcerrs + adapter->stats.algnerrc + 5032 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5033 netdev->stats.rx_length_errors = adapter->stats.ruc + 5034 adapter->stats.roc; 5035 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5036 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5037 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5038 5039 /* Tx Errors */ 5040 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5041 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5042 netdev->stats.tx_window_errors = adapter->stats.latecol; 5043 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5044 5045 /* Tx Dropped needs to be maintained elsewhere */ 5046 5047 /* Management Stats */ 5048 adapter->stats.mgptc += er32(MGTPTC); 5049 adapter->stats.mgprc += er32(MGTPRC); 5050 adapter->stats.mgpdc += er32(MGTPDC); 5051 5052 /* Correctable ECC Errors */ 5053 if (hw->mac.type >= e1000_pch_lpt) { 5054 u32 pbeccsts = er32(PBECCSTS); 5055 5056 adapter->corr_errors += 5057 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5058 adapter->uncorr_errors += 5059 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5060 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5061 } 5062 } 5063 5064 /** 5065 * e1000_phy_read_status - Update the PHY register status snapshot 5066 * @adapter: board private structure 5067 **/ 5068 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5069 { 5070 struct e1000_hw *hw = &adapter->hw; 5071 struct e1000_phy_regs *phy = &adapter->phy_regs; 5072 5073 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5074 (er32(STATUS) & E1000_STATUS_LU) && 5075 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5076 int ret_val; 5077 5078 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5079 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5080 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5081 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5082 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5083 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5084 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5085 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5086 if (ret_val) 5087 e_warn("Error reading PHY register\n"); 5088 } else { 5089 /* Do not read PHY registers if link is not up 5090 * Set values to typical power-on defaults 5091 */ 5092 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5093 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5094 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5095 BMSR_ERCAP); 5096 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5097 ADVERTISE_ALL | ADVERTISE_CSMA); 5098 phy->lpa = 0; 5099 phy->expansion = EXPANSION_ENABLENPAGE; 5100 phy->ctrl1000 = ADVERTISE_1000FULL; 5101 phy->stat1000 = 0; 5102 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5103 } 5104 } 5105 5106 static void e1000_print_link_info(struct e1000_adapter *adapter) 5107 { 5108 struct e1000_hw *hw = &adapter->hw; 5109 u32 ctrl = er32(CTRL); 5110 5111 /* Link status message must follow this format for user tools */ 5112 netdev_info(adapter->netdev, 5113 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5114 adapter->link_speed, 5115 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5116 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5117 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5118 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5119 } 5120 5121 static bool e1000e_has_link(struct e1000_adapter *adapter) 5122 { 5123 struct e1000_hw *hw = &adapter->hw; 5124 bool link_active = false; 5125 s32 ret_val = 0; 5126 5127 /* get_link_status is set on LSC (link status) interrupt or 5128 * Rx sequence error interrupt. get_link_status will stay 5129 * true until the check_for_link establishes link 5130 * for copper adapters ONLY 5131 */ 5132 switch (hw->phy.media_type) { 5133 case e1000_media_type_copper: 5134 if (hw->mac.get_link_status) { 5135 ret_val = hw->mac.ops.check_for_link(hw); 5136 link_active = !hw->mac.get_link_status; 5137 } else { 5138 link_active = true; 5139 } 5140 break; 5141 case e1000_media_type_fiber: 5142 ret_val = hw->mac.ops.check_for_link(hw); 5143 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5144 break; 5145 case e1000_media_type_internal_serdes: 5146 ret_val = hw->mac.ops.check_for_link(hw); 5147 link_active = hw->mac.serdes_has_link; 5148 break; 5149 default: 5150 case e1000_media_type_unknown: 5151 break; 5152 } 5153 5154 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5155 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5156 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5157 e_info("Gigabit has been disabled, downgrading speed\n"); 5158 } 5159 5160 return link_active; 5161 } 5162 5163 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5164 { 5165 /* make sure the receive unit is started */ 5166 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5167 (adapter->flags & FLAG_RESTART_NOW)) { 5168 struct e1000_hw *hw = &adapter->hw; 5169 u32 rctl = er32(RCTL); 5170 5171 ew32(RCTL, rctl | E1000_RCTL_EN); 5172 adapter->flags &= ~FLAG_RESTART_NOW; 5173 } 5174 } 5175 5176 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5177 { 5178 struct e1000_hw *hw = &adapter->hw; 5179 5180 /* With 82574 controllers, PHY needs to be checked periodically 5181 * for hung state and reset, if two calls return true 5182 */ 5183 if (e1000_check_phy_82574(hw)) 5184 adapter->phy_hang_count++; 5185 else 5186 adapter->phy_hang_count = 0; 5187 5188 if (adapter->phy_hang_count > 1) { 5189 adapter->phy_hang_count = 0; 5190 e_dbg("PHY appears hung - resetting\n"); 5191 schedule_work(&adapter->reset_task); 5192 } 5193 } 5194 5195 /** 5196 * e1000_watchdog - Timer Call-back 5197 * @data: pointer to adapter cast into an unsigned long 5198 **/ 5199 static void e1000_watchdog(struct timer_list *t) 5200 { 5201 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5202 5203 /* Do the rest outside of interrupt context */ 5204 schedule_work(&adapter->watchdog_task); 5205 5206 /* TODO: make this use queue_delayed_work() */ 5207 } 5208 5209 static void e1000_watchdog_task(struct work_struct *work) 5210 { 5211 struct e1000_adapter *adapter = container_of(work, 5212 struct e1000_adapter, 5213 watchdog_task); 5214 struct net_device *netdev = adapter->netdev; 5215 struct e1000_mac_info *mac = &adapter->hw.mac; 5216 struct e1000_phy_info *phy = &adapter->hw.phy; 5217 struct e1000_ring *tx_ring = adapter->tx_ring; 5218 u32 dmoff_exit_timeout = 100, tries = 0; 5219 struct e1000_hw *hw = &adapter->hw; 5220 u32 link, tctl, pcim_state; 5221 5222 if (test_bit(__E1000_DOWN, &adapter->state)) 5223 return; 5224 5225 link = e1000e_has_link(adapter); 5226 if ((netif_carrier_ok(netdev)) && link) { 5227 /* Cancel scheduled suspend requests. */ 5228 pm_runtime_resume(netdev->dev.parent); 5229 5230 e1000e_enable_receives(adapter); 5231 goto link_up; 5232 } 5233 5234 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5235 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5236 e1000_update_mng_vlan(adapter); 5237 5238 if (link) { 5239 if (!netif_carrier_ok(netdev)) { 5240 bool txb2b = true; 5241 5242 /* Cancel scheduled suspend requests. */ 5243 pm_runtime_resume(netdev->dev.parent); 5244 5245 /* Checking if MAC is in DMoff state*/ 5246 pcim_state = er32(STATUS); 5247 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5248 if (tries++ == dmoff_exit_timeout) { 5249 e_dbg("Error in exiting dmoff\n"); 5250 break; 5251 } 5252 usleep_range(10000, 20000); 5253 pcim_state = er32(STATUS); 5254 5255 /* Checking if MAC exited DMoff state */ 5256 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5257 e1000_phy_hw_reset(&adapter->hw); 5258 } 5259 5260 /* update snapshot of PHY registers on LSC */ 5261 e1000_phy_read_status(adapter); 5262 mac->ops.get_link_up_info(&adapter->hw, 5263 &adapter->link_speed, 5264 &adapter->link_duplex); 5265 e1000_print_link_info(adapter); 5266 5267 /* check if SmartSpeed worked */ 5268 e1000e_check_downshift(hw); 5269 if (phy->speed_downgraded) 5270 netdev_warn(netdev, 5271 "Link Speed was downgraded by SmartSpeed\n"); 5272 5273 /* On supported PHYs, check for duplex mismatch only 5274 * if link has autonegotiated at 10/100 half 5275 */ 5276 if ((hw->phy.type == e1000_phy_igp_3 || 5277 hw->phy.type == e1000_phy_bm) && 5278 hw->mac.autoneg && 5279 (adapter->link_speed == SPEED_10 || 5280 adapter->link_speed == SPEED_100) && 5281 (adapter->link_duplex == HALF_DUPLEX)) { 5282 u16 autoneg_exp; 5283 5284 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5285 5286 if (!(autoneg_exp & EXPANSION_NWAY)) 5287 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5288 } 5289 5290 /* adjust timeout factor according to speed/duplex */ 5291 adapter->tx_timeout_factor = 1; 5292 switch (adapter->link_speed) { 5293 case SPEED_10: 5294 txb2b = false; 5295 adapter->tx_timeout_factor = 16; 5296 break; 5297 case SPEED_100: 5298 txb2b = false; 5299 adapter->tx_timeout_factor = 10; 5300 break; 5301 } 5302 5303 /* workaround: re-program speed mode bit after 5304 * link-up event 5305 */ 5306 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5307 !txb2b) { 5308 u32 tarc0; 5309 5310 tarc0 = er32(TARC(0)); 5311 tarc0 &= ~SPEED_MODE_BIT; 5312 ew32(TARC(0), tarc0); 5313 } 5314 5315 /* disable TSO for pcie and 10/100 speeds, to avoid 5316 * some hardware issues 5317 */ 5318 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5319 switch (adapter->link_speed) { 5320 case SPEED_10: 5321 case SPEED_100: 5322 e_info("10/100 speed: disabling TSO\n"); 5323 netdev->features &= ~NETIF_F_TSO; 5324 netdev->features &= ~NETIF_F_TSO6; 5325 break; 5326 case SPEED_1000: 5327 netdev->features |= NETIF_F_TSO; 5328 netdev->features |= NETIF_F_TSO6; 5329 break; 5330 default: 5331 /* oops */ 5332 break; 5333 } 5334 if (hw->mac.type == e1000_pch_spt) { 5335 netdev->features &= ~NETIF_F_TSO; 5336 netdev->features &= ~NETIF_F_TSO6; 5337 } 5338 } 5339 5340 /* enable transmits in the hardware, need to do this 5341 * after setting TARC(0) 5342 */ 5343 tctl = er32(TCTL); 5344 tctl |= E1000_TCTL_EN; 5345 ew32(TCTL, tctl); 5346 5347 /* Perform any post-link-up configuration before 5348 * reporting link up. 5349 */ 5350 if (phy->ops.cfg_on_link_up) 5351 phy->ops.cfg_on_link_up(hw); 5352 5353 netif_wake_queue(netdev); 5354 netif_carrier_on(netdev); 5355 5356 if (!test_bit(__E1000_DOWN, &adapter->state)) 5357 mod_timer(&adapter->phy_info_timer, 5358 round_jiffies(jiffies + 2 * HZ)); 5359 } 5360 } else { 5361 if (netif_carrier_ok(netdev)) { 5362 adapter->link_speed = 0; 5363 adapter->link_duplex = 0; 5364 /* Link status message must follow this format */ 5365 netdev_info(netdev, "NIC Link is Down\n"); 5366 netif_carrier_off(netdev); 5367 netif_stop_queue(netdev); 5368 if (!test_bit(__E1000_DOWN, &adapter->state)) 5369 mod_timer(&adapter->phy_info_timer, 5370 round_jiffies(jiffies + 2 * HZ)); 5371 5372 /* 8000ES2LAN requires a Rx packet buffer work-around 5373 * on link down event; reset the controller to flush 5374 * the Rx packet buffer. 5375 */ 5376 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5377 adapter->flags |= FLAG_RESTART_NOW; 5378 else 5379 pm_schedule_suspend(netdev->dev.parent, 5380 LINK_TIMEOUT); 5381 } 5382 } 5383 5384 link_up: 5385 spin_lock(&adapter->stats64_lock); 5386 e1000e_update_stats(adapter); 5387 5388 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5389 adapter->tpt_old = adapter->stats.tpt; 5390 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5391 adapter->colc_old = adapter->stats.colc; 5392 5393 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5394 adapter->gorc_old = adapter->stats.gorc; 5395 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5396 adapter->gotc_old = adapter->stats.gotc; 5397 spin_unlock(&adapter->stats64_lock); 5398 5399 /* If the link is lost the controller stops DMA, but 5400 * if there is queued Tx work it cannot be done. So 5401 * reset the controller to flush the Tx packet buffers. 5402 */ 5403 if (!netif_carrier_ok(netdev) && 5404 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5405 adapter->flags |= FLAG_RESTART_NOW; 5406 5407 /* If reset is necessary, do it outside of interrupt context. */ 5408 if (adapter->flags & FLAG_RESTART_NOW) { 5409 schedule_work(&adapter->reset_task); 5410 /* return immediately since reset is imminent */ 5411 return; 5412 } 5413 5414 e1000e_update_adaptive(&adapter->hw); 5415 5416 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5417 if (adapter->itr_setting == 4) { 5418 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5419 * Total asymmetrical Tx or Rx gets ITR=8000; 5420 * everyone else is between 2000-8000. 5421 */ 5422 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5423 u32 dif = (adapter->gotc > adapter->gorc ? 5424 adapter->gotc - adapter->gorc : 5425 adapter->gorc - adapter->gotc) / 10000; 5426 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5427 5428 e1000e_write_itr(adapter, itr); 5429 } 5430 5431 /* Cause software interrupt to ensure Rx ring is cleaned */ 5432 if (adapter->msix_entries) 5433 ew32(ICS, adapter->rx_ring->ims_val); 5434 else 5435 ew32(ICS, E1000_ICS_RXDMT0); 5436 5437 /* flush pending descriptors to memory before detecting Tx hang */ 5438 e1000e_flush_descriptors(adapter); 5439 5440 /* Force detection of hung controller every watchdog period */ 5441 adapter->detect_tx_hung = true; 5442 5443 /* With 82571 controllers, LAA may be overwritten due to controller 5444 * reset from the other port. Set the appropriate LAA in RAR[0] 5445 */ 5446 if (e1000e_get_laa_state_82571(hw)) 5447 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5448 5449 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5450 e1000e_check_82574_phy_workaround(adapter); 5451 5452 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5453 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5454 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5455 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5456 er32(RXSTMPH); 5457 adapter->rx_hwtstamp_cleared++; 5458 } else { 5459 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5460 } 5461 } 5462 5463 /* Reset the timer */ 5464 if (!test_bit(__E1000_DOWN, &adapter->state)) 5465 mod_timer(&adapter->watchdog_timer, 5466 round_jiffies(jiffies + 2 * HZ)); 5467 } 5468 5469 #define E1000_TX_FLAGS_CSUM 0x00000001 5470 #define E1000_TX_FLAGS_VLAN 0x00000002 5471 #define E1000_TX_FLAGS_TSO 0x00000004 5472 #define E1000_TX_FLAGS_IPV4 0x00000008 5473 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5474 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5475 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5476 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5477 5478 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5479 __be16 protocol) 5480 { 5481 struct e1000_context_desc *context_desc; 5482 struct e1000_buffer *buffer_info; 5483 unsigned int i; 5484 u32 cmd_length = 0; 5485 u16 ipcse = 0, mss; 5486 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5487 int err; 5488 5489 if (!skb_is_gso(skb)) 5490 return 0; 5491 5492 err = skb_cow_head(skb, 0); 5493 if (err < 0) 5494 return err; 5495 5496 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5497 mss = skb_shinfo(skb)->gso_size; 5498 if (protocol == htons(ETH_P_IP)) { 5499 struct iphdr *iph = ip_hdr(skb); 5500 iph->tot_len = 0; 5501 iph->check = 0; 5502 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5503 0, IPPROTO_TCP, 0); 5504 cmd_length = E1000_TXD_CMD_IP; 5505 ipcse = skb_transport_offset(skb) - 1; 5506 } else if (skb_is_gso_v6(skb)) { 5507 tcp_v6_gso_csum_prep(skb); 5508 ipcse = 0; 5509 } 5510 ipcss = skb_network_offset(skb); 5511 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5512 tucss = skb_transport_offset(skb); 5513 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5514 5515 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5516 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5517 5518 i = tx_ring->next_to_use; 5519 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5520 buffer_info = &tx_ring->buffer_info[i]; 5521 5522 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5523 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5524 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5525 context_desc->upper_setup.tcp_fields.tucss = tucss; 5526 context_desc->upper_setup.tcp_fields.tucso = tucso; 5527 context_desc->upper_setup.tcp_fields.tucse = 0; 5528 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5529 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5530 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5531 5532 buffer_info->time_stamp = jiffies; 5533 buffer_info->next_to_watch = i; 5534 5535 i++; 5536 if (i == tx_ring->count) 5537 i = 0; 5538 tx_ring->next_to_use = i; 5539 5540 return 1; 5541 } 5542 5543 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5544 __be16 protocol) 5545 { 5546 struct e1000_adapter *adapter = tx_ring->adapter; 5547 struct e1000_context_desc *context_desc; 5548 struct e1000_buffer *buffer_info; 5549 unsigned int i; 5550 u8 css; 5551 u32 cmd_len = E1000_TXD_CMD_DEXT; 5552 5553 if (skb->ip_summed != CHECKSUM_PARTIAL) 5554 return false; 5555 5556 switch (protocol) { 5557 case cpu_to_be16(ETH_P_IP): 5558 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5559 cmd_len |= E1000_TXD_CMD_TCP; 5560 break; 5561 case cpu_to_be16(ETH_P_IPV6): 5562 /* XXX not handling all IPV6 headers */ 5563 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5564 cmd_len |= E1000_TXD_CMD_TCP; 5565 break; 5566 default: 5567 if (unlikely(net_ratelimit())) 5568 e_warn("checksum_partial proto=%x!\n", 5569 be16_to_cpu(protocol)); 5570 break; 5571 } 5572 5573 css = skb_checksum_start_offset(skb); 5574 5575 i = tx_ring->next_to_use; 5576 buffer_info = &tx_ring->buffer_info[i]; 5577 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5578 5579 context_desc->lower_setup.ip_config = 0; 5580 context_desc->upper_setup.tcp_fields.tucss = css; 5581 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5582 context_desc->upper_setup.tcp_fields.tucse = 0; 5583 context_desc->tcp_seg_setup.data = 0; 5584 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5585 5586 buffer_info->time_stamp = jiffies; 5587 buffer_info->next_to_watch = i; 5588 5589 i++; 5590 if (i == tx_ring->count) 5591 i = 0; 5592 tx_ring->next_to_use = i; 5593 5594 return true; 5595 } 5596 5597 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5598 unsigned int first, unsigned int max_per_txd, 5599 unsigned int nr_frags) 5600 { 5601 struct e1000_adapter *adapter = tx_ring->adapter; 5602 struct pci_dev *pdev = adapter->pdev; 5603 struct e1000_buffer *buffer_info; 5604 unsigned int len = skb_headlen(skb); 5605 unsigned int offset = 0, size, count = 0, i; 5606 unsigned int f, bytecount, segs; 5607 5608 i = tx_ring->next_to_use; 5609 5610 while (len) { 5611 buffer_info = &tx_ring->buffer_info[i]; 5612 size = min(len, max_per_txd); 5613 5614 buffer_info->length = size; 5615 buffer_info->time_stamp = jiffies; 5616 buffer_info->next_to_watch = i; 5617 buffer_info->dma = dma_map_single(&pdev->dev, 5618 skb->data + offset, 5619 size, DMA_TO_DEVICE); 5620 buffer_info->mapped_as_page = false; 5621 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5622 goto dma_error; 5623 5624 len -= size; 5625 offset += size; 5626 count++; 5627 5628 if (len) { 5629 i++; 5630 if (i == tx_ring->count) 5631 i = 0; 5632 } 5633 } 5634 5635 for (f = 0; f < nr_frags; f++) { 5636 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5637 5638 len = skb_frag_size(frag); 5639 offset = 0; 5640 5641 while (len) { 5642 i++; 5643 if (i == tx_ring->count) 5644 i = 0; 5645 5646 buffer_info = &tx_ring->buffer_info[i]; 5647 size = min(len, max_per_txd); 5648 5649 buffer_info->length = size; 5650 buffer_info->time_stamp = jiffies; 5651 buffer_info->next_to_watch = i; 5652 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5653 offset, size, 5654 DMA_TO_DEVICE); 5655 buffer_info->mapped_as_page = true; 5656 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5657 goto dma_error; 5658 5659 len -= size; 5660 offset += size; 5661 count++; 5662 } 5663 } 5664 5665 segs = skb_shinfo(skb)->gso_segs ? : 1; 5666 /* multiply data chunks by size of headers */ 5667 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5668 5669 tx_ring->buffer_info[i].skb = skb; 5670 tx_ring->buffer_info[i].segs = segs; 5671 tx_ring->buffer_info[i].bytecount = bytecount; 5672 tx_ring->buffer_info[first].next_to_watch = i; 5673 5674 return count; 5675 5676 dma_error: 5677 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5678 buffer_info->dma = 0; 5679 if (count) 5680 count--; 5681 5682 while (count--) { 5683 if (i == 0) 5684 i += tx_ring->count; 5685 i--; 5686 buffer_info = &tx_ring->buffer_info[i]; 5687 e1000_put_txbuf(tx_ring, buffer_info, true); 5688 } 5689 5690 return 0; 5691 } 5692 5693 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5694 { 5695 struct e1000_adapter *adapter = tx_ring->adapter; 5696 struct e1000_tx_desc *tx_desc = NULL; 5697 struct e1000_buffer *buffer_info; 5698 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5699 unsigned int i; 5700 5701 if (tx_flags & E1000_TX_FLAGS_TSO) { 5702 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5703 E1000_TXD_CMD_TSE; 5704 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5705 5706 if (tx_flags & E1000_TX_FLAGS_IPV4) 5707 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5708 } 5709 5710 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5711 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5712 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5713 } 5714 5715 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5716 txd_lower |= E1000_TXD_CMD_VLE; 5717 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5718 } 5719 5720 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5721 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5722 5723 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5724 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5725 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5726 } 5727 5728 i = tx_ring->next_to_use; 5729 5730 do { 5731 buffer_info = &tx_ring->buffer_info[i]; 5732 tx_desc = E1000_TX_DESC(*tx_ring, i); 5733 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5734 tx_desc->lower.data = cpu_to_le32(txd_lower | 5735 buffer_info->length); 5736 tx_desc->upper.data = cpu_to_le32(txd_upper); 5737 5738 i++; 5739 if (i == tx_ring->count) 5740 i = 0; 5741 } while (--count > 0); 5742 5743 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5744 5745 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5746 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5747 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5748 5749 /* Force memory writes to complete before letting h/w 5750 * know there are new descriptors to fetch. (Only 5751 * applicable for weak-ordered memory model archs, 5752 * such as IA-64). 5753 */ 5754 wmb(); 5755 5756 tx_ring->next_to_use = i; 5757 } 5758 5759 #define MINIMUM_DHCP_PACKET_SIZE 282 5760 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5761 struct sk_buff *skb) 5762 { 5763 struct e1000_hw *hw = &adapter->hw; 5764 u16 length, offset; 5765 5766 if (skb_vlan_tag_present(skb) && 5767 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5768 (adapter->hw.mng_cookie.status & 5769 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5770 return 0; 5771 5772 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5773 return 0; 5774 5775 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5776 return 0; 5777 5778 { 5779 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5780 struct udphdr *udp; 5781 5782 if (ip->protocol != IPPROTO_UDP) 5783 return 0; 5784 5785 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5786 if (ntohs(udp->dest) != 67) 5787 return 0; 5788 5789 offset = (u8 *)udp + 8 - skb->data; 5790 length = skb->len - offset; 5791 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5792 } 5793 5794 return 0; 5795 } 5796 5797 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5798 { 5799 struct e1000_adapter *adapter = tx_ring->adapter; 5800 5801 netif_stop_queue(adapter->netdev); 5802 /* Herbert's original patch had: 5803 * smp_mb__after_netif_stop_queue(); 5804 * but since that doesn't exist yet, just open code it. 5805 */ 5806 smp_mb(); 5807 5808 /* We need to check again in a case another CPU has just 5809 * made room available. 5810 */ 5811 if (e1000_desc_unused(tx_ring) < size) 5812 return -EBUSY; 5813 5814 /* A reprieve! */ 5815 netif_start_queue(adapter->netdev); 5816 ++adapter->restart_queue; 5817 return 0; 5818 } 5819 5820 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5821 { 5822 BUG_ON(size > tx_ring->count); 5823 5824 if (e1000_desc_unused(tx_ring) >= size) 5825 return 0; 5826 return __e1000_maybe_stop_tx(tx_ring, size); 5827 } 5828 5829 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5830 struct net_device *netdev) 5831 { 5832 struct e1000_adapter *adapter = netdev_priv(netdev); 5833 struct e1000_ring *tx_ring = adapter->tx_ring; 5834 unsigned int first; 5835 unsigned int tx_flags = 0; 5836 unsigned int len = skb_headlen(skb); 5837 unsigned int nr_frags; 5838 unsigned int mss; 5839 int count = 0; 5840 int tso; 5841 unsigned int f; 5842 __be16 protocol = vlan_get_protocol(skb); 5843 5844 if (test_bit(__E1000_DOWN, &adapter->state)) { 5845 dev_kfree_skb_any(skb); 5846 return NETDEV_TX_OK; 5847 } 5848 5849 if (skb->len <= 0) { 5850 dev_kfree_skb_any(skb); 5851 return NETDEV_TX_OK; 5852 } 5853 5854 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5855 * pad skb in order to meet this minimum size requirement 5856 */ 5857 if (skb_put_padto(skb, 17)) 5858 return NETDEV_TX_OK; 5859 5860 mss = skb_shinfo(skb)->gso_size; 5861 if (mss) { 5862 u8 hdr_len; 5863 5864 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5865 * points to just header, pull a few bytes of payload from 5866 * frags into skb->data 5867 */ 5868 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5869 /* we do this workaround for ES2LAN, but it is un-necessary, 5870 * avoiding it could save a lot of cycles 5871 */ 5872 if (skb->data_len && (hdr_len == len)) { 5873 unsigned int pull_size; 5874 5875 pull_size = min_t(unsigned int, 4, skb->data_len); 5876 if (!__pskb_pull_tail(skb, pull_size)) { 5877 e_err("__pskb_pull_tail failed.\n"); 5878 dev_kfree_skb_any(skb); 5879 return NETDEV_TX_OK; 5880 } 5881 len = skb_headlen(skb); 5882 } 5883 } 5884 5885 /* reserve a descriptor for the offload context */ 5886 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5887 count++; 5888 count++; 5889 5890 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5891 5892 nr_frags = skb_shinfo(skb)->nr_frags; 5893 for (f = 0; f < nr_frags; f++) 5894 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5895 adapter->tx_fifo_limit); 5896 5897 if (adapter->hw.mac.tx_pkt_filtering) 5898 e1000_transfer_dhcp_info(adapter, skb); 5899 5900 /* need: count + 2 desc gap to keep tail from touching 5901 * head, otherwise try next time 5902 */ 5903 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5904 return NETDEV_TX_BUSY; 5905 5906 if (skb_vlan_tag_present(skb)) { 5907 tx_flags |= E1000_TX_FLAGS_VLAN; 5908 tx_flags |= (skb_vlan_tag_get(skb) << 5909 E1000_TX_FLAGS_VLAN_SHIFT); 5910 } 5911 5912 first = tx_ring->next_to_use; 5913 5914 tso = e1000_tso(tx_ring, skb, protocol); 5915 if (tso < 0) { 5916 dev_kfree_skb_any(skb); 5917 return NETDEV_TX_OK; 5918 } 5919 5920 if (tso) 5921 tx_flags |= E1000_TX_FLAGS_TSO; 5922 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5923 tx_flags |= E1000_TX_FLAGS_CSUM; 5924 5925 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5926 * 82571 hardware supports TSO capabilities for IPv6 as well... 5927 * no longer assume, we must. 5928 */ 5929 if (protocol == htons(ETH_P_IP)) 5930 tx_flags |= E1000_TX_FLAGS_IPV4; 5931 5932 if (unlikely(skb->no_fcs)) 5933 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5934 5935 /* if count is 0 then mapping error has occurred */ 5936 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5937 nr_frags); 5938 if (count) { 5939 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5940 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5941 if (!adapter->tx_hwtstamp_skb) { 5942 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5943 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5944 adapter->tx_hwtstamp_skb = skb_get(skb); 5945 adapter->tx_hwtstamp_start = jiffies; 5946 schedule_work(&adapter->tx_hwtstamp_work); 5947 } else { 5948 adapter->tx_hwtstamp_skipped++; 5949 } 5950 } 5951 5952 skb_tx_timestamp(skb); 5953 5954 netdev_sent_queue(netdev, skb->len); 5955 e1000_tx_queue(tx_ring, tx_flags, count); 5956 /* Make sure there is space in the ring for the next send. */ 5957 e1000_maybe_stop_tx(tx_ring, 5958 (MAX_SKB_FRAGS * 5959 DIV_ROUND_UP(PAGE_SIZE, 5960 adapter->tx_fifo_limit) + 2)); 5961 5962 if (!netdev_xmit_more() || 5963 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5964 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5965 e1000e_update_tdt_wa(tx_ring, 5966 tx_ring->next_to_use); 5967 else 5968 writel(tx_ring->next_to_use, tx_ring->tail); 5969 } 5970 } else { 5971 dev_kfree_skb_any(skb); 5972 tx_ring->buffer_info[first].time_stamp = 0; 5973 tx_ring->next_to_use = first; 5974 } 5975 5976 return NETDEV_TX_OK; 5977 } 5978 5979 /** 5980 * e1000_tx_timeout - Respond to a Tx Hang 5981 * @netdev: network interface device structure 5982 **/ 5983 static void e1000_tx_timeout(struct net_device *netdev, unsigned int txqueue) 5984 { 5985 struct e1000_adapter *adapter = netdev_priv(netdev); 5986 5987 /* Do the reset outside of interrupt context */ 5988 adapter->tx_timeout_count++; 5989 schedule_work(&adapter->reset_task); 5990 } 5991 5992 static void e1000_reset_task(struct work_struct *work) 5993 { 5994 struct e1000_adapter *adapter; 5995 adapter = container_of(work, struct e1000_adapter, reset_task); 5996 5997 /* don't run the task if already down */ 5998 if (test_bit(__E1000_DOWN, &adapter->state)) 5999 return; 6000 6001 if (!(adapter->flags & FLAG_RESTART_NOW)) { 6002 e1000e_dump(adapter); 6003 e_err("Reset adapter unexpectedly\n"); 6004 } 6005 e1000e_reinit_locked(adapter); 6006 } 6007 6008 /** 6009 * e1000_get_stats64 - Get System Network Statistics 6010 * @netdev: network interface device structure 6011 * @stats: rtnl_link_stats64 pointer 6012 * 6013 * Returns the address of the device statistics structure. 6014 **/ 6015 void e1000e_get_stats64(struct net_device *netdev, 6016 struct rtnl_link_stats64 *stats) 6017 { 6018 struct e1000_adapter *adapter = netdev_priv(netdev); 6019 6020 spin_lock(&adapter->stats64_lock); 6021 e1000e_update_stats(adapter); 6022 /* Fill out the OS statistics structure */ 6023 stats->rx_bytes = adapter->stats.gorc; 6024 stats->rx_packets = adapter->stats.gprc; 6025 stats->tx_bytes = adapter->stats.gotc; 6026 stats->tx_packets = adapter->stats.gptc; 6027 stats->multicast = adapter->stats.mprc; 6028 stats->collisions = adapter->stats.colc; 6029 6030 /* Rx Errors */ 6031 6032 /* RLEC on some newer hardware can be incorrect so build 6033 * our own version based on RUC and ROC 6034 */ 6035 stats->rx_errors = adapter->stats.rxerrc + 6036 adapter->stats.crcerrs + adapter->stats.algnerrc + 6037 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6038 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6039 stats->rx_crc_errors = adapter->stats.crcerrs; 6040 stats->rx_frame_errors = adapter->stats.algnerrc; 6041 stats->rx_missed_errors = adapter->stats.mpc; 6042 6043 /* Tx Errors */ 6044 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6045 stats->tx_aborted_errors = adapter->stats.ecol; 6046 stats->tx_window_errors = adapter->stats.latecol; 6047 stats->tx_carrier_errors = adapter->stats.tncrs; 6048 6049 /* Tx Dropped needs to be maintained elsewhere */ 6050 6051 spin_unlock(&adapter->stats64_lock); 6052 } 6053 6054 /** 6055 * e1000_change_mtu - Change the Maximum Transfer Unit 6056 * @netdev: network interface device structure 6057 * @new_mtu: new value for maximum frame size 6058 * 6059 * Returns 0 on success, negative on failure 6060 **/ 6061 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6062 { 6063 struct e1000_adapter *adapter = netdev_priv(netdev); 6064 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6065 6066 /* Jumbo frame support */ 6067 if ((new_mtu > ETH_DATA_LEN) && 6068 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6069 e_err("Jumbo Frames not supported.\n"); 6070 return -EINVAL; 6071 } 6072 6073 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6074 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6075 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6076 (new_mtu > ETH_DATA_LEN)) { 6077 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6078 return -EINVAL; 6079 } 6080 6081 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6082 usleep_range(1000, 1100); 6083 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6084 adapter->max_frame_size = max_frame; 6085 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6086 netdev->mtu, new_mtu); 6087 netdev->mtu = new_mtu; 6088 6089 pm_runtime_get_sync(netdev->dev.parent); 6090 6091 if (netif_running(netdev)) 6092 e1000e_down(adapter, true); 6093 6094 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6095 * means we reserve 2 more, this pushes us to allocate from the next 6096 * larger slab size. 6097 * i.e. RXBUFFER_2048 --> size-4096 slab 6098 * However with the new *_jumbo_rx* routines, jumbo receives will use 6099 * fragmented skbs 6100 */ 6101 6102 if (max_frame <= 2048) 6103 adapter->rx_buffer_len = 2048; 6104 else 6105 adapter->rx_buffer_len = 4096; 6106 6107 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6108 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6109 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6110 6111 if (netif_running(netdev)) 6112 e1000e_up(adapter); 6113 else 6114 e1000e_reset(adapter); 6115 6116 pm_runtime_put_sync(netdev->dev.parent); 6117 6118 clear_bit(__E1000_RESETTING, &adapter->state); 6119 6120 return 0; 6121 } 6122 6123 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6124 int cmd) 6125 { 6126 struct e1000_adapter *adapter = netdev_priv(netdev); 6127 struct mii_ioctl_data *data = if_mii(ifr); 6128 6129 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6130 return -EOPNOTSUPP; 6131 6132 switch (cmd) { 6133 case SIOCGMIIPHY: 6134 data->phy_id = adapter->hw.phy.addr; 6135 break; 6136 case SIOCGMIIREG: 6137 e1000_phy_read_status(adapter); 6138 6139 switch (data->reg_num & 0x1F) { 6140 case MII_BMCR: 6141 data->val_out = adapter->phy_regs.bmcr; 6142 break; 6143 case MII_BMSR: 6144 data->val_out = adapter->phy_regs.bmsr; 6145 break; 6146 case MII_PHYSID1: 6147 data->val_out = (adapter->hw.phy.id >> 16); 6148 break; 6149 case MII_PHYSID2: 6150 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6151 break; 6152 case MII_ADVERTISE: 6153 data->val_out = adapter->phy_regs.advertise; 6154 break; 6155 case MII_LPA: 6156 data->val_out = adapter->phy_regs.lpa; 6157 break; 6158 case MII_EXPANSION: 6159 data->val_out = adapter->phy_regs.expansion; 6160 break; 6161 case MII_CTRL1000: 6162 data->val_out = adapter->phy_regs.ctrl1000; 6163 break; 6164 case MII_STAT1000: 6165 data->val_out = adapter->phy_regs.stat1000; 6166 break; 6167 case MII_ESTATUS: 6168 data->val_out = adapter->phy_regs.estatus; 6169 break; 6170 default: 6171 return -EIO; 6172 } 6173 break; 6174 case SIOCSMIIREG: 6175 default: 6176 return -EOPNOTSUPP; 6177 } 6178 return 0; 6179 } 6180 6181 /** 6182 * e1000e_hwtstamp_ioctl - control hardware time stamping 6183 * @netdev: network interface device structure 6184 * @ifreq: interface request 6185 * 6186 * Outgoing time stamping can be enabled and disabled. Play nice and 6187 * disable it when requested, although it shouldn't cause any overhead 6188 * when no packet needs it. At most one packet in the queue may be 6189 * marked for time stamping, otherwise it would be impossible to tell 6190 * for sure to which packet the hardware time stamp belongs. 6191 * 6192 * Incoming time stamping has to be configured via the hardware filters. 6193 * Not all combinations are supported, in particular event type has to be 6194 * specified. Matching the kind of event packet is not supported, with the 6195 * exception of "all V2 events regardless of level 2 or 4". 6196 **/ 6197 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6198 { 6199 struct e1000_adapter *adapter = netdev_priv(netdev); 6200 struct hwtstamp_config config; 6201 int ret_val; 6202 6203 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6204 return -EFAULT; 6205 6206 ret_val = e1000e_config_hwtstamp(adapter, &config); 6207 if (ret_val) 6208 return ret_val; 6209 6210 switch (config.rx_filter) { 6211 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6212 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6213 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6214 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6215 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6216 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6217 /* With V2 type filters which specify a Sync or Delay Request, 6218 * Path Delay Request/Response messages are also time stamped 6219 * by hardware so notify the caller the requested packets plus 6220 * some others are time stamped. 6221 */ 6222 config.rx_filter = HWTSTAMP_FILTER_SOME; 6223 break; 6224 default: 6225 break; 6226 } 6227 6228 return copy_to_user(ifr->ifr_data, &config, 6229 sizeof(config)) ? -EFAULT : 0; 6230 } 6231 6232 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6233 { 6234 struct e1000_adapter *adapter = netdev_priv(netdev); 6235 6236 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6237 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6238 } 6239 6240 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6241 { 6242 switch (cmd) { 6243 case SIOCGMIIPHY: 6244 case SIOCGMIIREG: 6245 case SIOCSMIIREG: 6246 return e1000_mii_ioctl(netdev, ifr, cmd); 6247 case SIOCSHWTSTAMP: 6248 return e1000e_hwtstamp_set(netdev, ifr); 6249 case SIOCGHWTSTAMP: 6250 return e1000e_hwtstamp_get(netdev, ifr); 6251 default: 6252 return -EOPNOTSUPP; 6253 } 6254 } 6255 6256 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6257 { 6258 struct e1000_hw *hw = &adapter->hw; 6259 u32 i, mac_reg, wuc; 6260 u16 phy_reg, wuc_enable; 6261 int retval; 6262 6263 /* copy MAC RARs to PHY RARs */ 6264 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6265 6266 retval = hw->phy.ops.acquire(hw); 6267 if (retval) { 6268 e_err("Could not acquire PHY\n"); 6269 return retval; 6270 } 6271 6272 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6273 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6274 if (retval) 6275 goto release; 6276 6277 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6278 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6279 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6280 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6281 (u16)(mac_reg & 0xFFFF)); 6282 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6283 (u16)((mac_reg >> 16) & 0xFFFF)); 6284 } 6285 6286 /* configure PHY Rx Control register */ 6287 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6288 mac_reg = er32(RCTL); 6289 if (mac_reg & E1000_RCTL_UPE) 6290 phy_reg |= BM_RCTL_UPE; 6291 if (mac_reg & E1000_RCTL_MPE) 6292 phy_reg |= BM_RCTL_MPE; 6293 phy_reg &= ~(BM_RCTL_MO_MASK); 6294 if (mac_reg & E1000_RCTL_MO_3) 6295 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6296 << BM_RCTL_MO_SHIFT); 6297 if (mac_reg & E1000_RCTL_BAM) 6298 phy_reg |= BM_RCTL_BAM; 6299 if (mac_reg & E1000_RCTL_PMCF) 6300 phy_reg |= BM_RCTL_PMCF; 6301 mac_reg = er32(CTRL); 6302 if (mac_reg & E1000_CTRL_RFCE) 6303 phy_reg |= BM_RCTL_RFCE; 6304 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6305 6306 wuc = E1000_WUC_PME_EN; 6307 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6308 wuc |= E1000_WUC_APME; 6309 6310 /* enable PHY wakeup in MAC register */ 6311 ew32(WUFC, wufc); 6312 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6313 E1000_WUC_PME_STATUS | wuc)); 6314 6315 /* configure and enable PHY wakeup in PHY registers */ 6316 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6317 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6318 6319 /* activate PHY wakeup */ 6320 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6321 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6322 if (retval) 6323 e_err("Could not set PHY Host Wakeup bit\n"); 6324 release: 6325 hw->phy.ops.release(hw); 6326 6327 return retval; 6328 } 6329 6330 static void e1000e_flush_lpic(struct pci_dev *pdev) 6331 { 6332 struct net_device *netdev = pci_get_drvdata(pdev); 6333 struct e1000_adapter *adapter = netdev_priv(netdev); 6334 struct e1000_hw *hw = &adapter->hw; 6335 u32 ret_val; 6336 6337 pm_runtime_get_sync(netdev->dev.parent); 6338 6339 ret_val = hw->phy.ops.acquire(hw); 6340 if (ret_val) 6341 goto fl_out; 6342 6343 pr_info("EEE TX LPI TIMER: %08X\n", 6344 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6345 6346 hw->phy.ops.release(hw); 6347 6348 fl_out: 6349 pm_runtime_put_sync(netdev->dev.parent); 6350 } 6351 6352 #ifdef CONFIG_PM_SLEEP 6353 /* S0ix implementation */ 6354 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6355 { 6356 struct e1000_hw *hw = &adapter->hw; 6357 u32 mac_data; 6358 u16 phy_data; 6359 6360 /* Disable the periodic inband message, 6361 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6362 */ 6363 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6364 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6365 phy_data |= BIT(10); 6366 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6367 6368 /* Make sure we don't exit K1 every time a new packet arrives 6369 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6370 */ 6371 e1e_rphy(hw, I217_CGFREG, &phy_data); 6372 phy_data |= BIT(5); 6373 e1e_wphy(hw, I217_CGFREG, phy_data); 6374 6375 /* Change the MAC/PHY interface to SMBus 6376 * Force the SMBus in PHY page769_23[0] = 1 6377 * Force the SMBus in MAC CTRL_EXT[11] = 1 6378 */ 6379 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6380 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6381 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6382 mac_data = er32(CTRL_EXT); 6383 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6384 ew32(CTRL_EXT, mac_data); 6385 6386 /* DFT control: PHY bit: page769_20[0] = 1 6387 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6388 */ 6389 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6390 phy_data |= BIT(0); 6391 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6392 6393 mac_data = er32(EXTCNF_CTRL); 6394 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6395 ew32(EXTCNF_CTRL, mac_data); 6396 6397 /* Check MAC Tx/Rx packet buffer pointers. 6398 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6399 * pending traffic indication that would prevent power gating. 6400 */ 6401 mac_data = er32(TDFH); 6402 if (mac_data) 6403 ew32(TDFH, 0); 6404 mac_data = er32(TDFT); 6405 if (mac_data) 6406 ew32(TDFT, 0); 6407 mac_data = er32(TDFHS); 6408 if (mac_data) 6409 ew32(TDFHS, 0); 6410 mac_data = er32(TDFTS); 6411 if (mac_data) 6412 ew32(TDFTS, 0); 6413 mac_data = er32(TDFPC); 6414 if (mac_data) 6415 ew32(TDFPC, 0); 6416 mac_data = er32(RDFH); 6417 if (mac_data) 6418 ew32(RDFH, 0); 6419 mac_data = er32(RDFT); 6420 if (mac_data) 6421 ew32(RDFT, 0); 6422 mac_data = er32(RDFHS); 6423 if (mac_data) 6424 ew32(RDFHS, 0); 6425 mac_data = er32(RDFTS); 6426 if (mac_data) 6427 ew32(RDFTS, 0); 6428 mac_data = er32(RDFPC); 6429 if (mac_data) 6430 ew32(RDFPC, 0); 6431 6432 /* Enable the Dynamic Power Gating in the MAC */ 6433 mac_data = er32(FEXTNVM7); 6434 mac_data |= BIT(22); 6435 ew32(FEXTNVM7, mac_data); 6436 6437 /* Disable the time synchronization clock */ 6438 mac_data = er32(FEXTNVM7); 6439 mac_data |= BIT(31); 6440 mac_data &= ~BIT(0); 6441 ew32(FEXTNVM7, mac_data); 6442 6443 /* Dynamic Power Gating Enable */ 6444 mac_data = er32(CTRL_EXT); 6445 mac_data |= BIT(3); 6446 ew32(CTRL_EXT, mac_data); 6447 6448 /* Disable disconnected cable conditioning for Power Gating */ 6449 mac_data = er32(DPGFR); 6450 mac_data |= BIT(2); 6451 ew32(DPGFR, mac_data); 6452 6453 /* Don't wake from dynamic Power Gating with clock request */ 6454 mac_data = er32(FEXTNVM12); 6455 mac_data |= BIT(12); 6456 ew32(FEXTNVM12, mac_data); 6457 6458 /* Ungate PGCB clock */ 6459 mac_data = er32(FEXTNVM9); 6460 mac_data |= BIT(28); 6461 ew32(FEXTNVM9, mac_data); 6462 6463 /* Enable K1 off to enable mPHY Power Gating */ 6464 mac_data = er32(FEXTNVM6); 6465 mac_data |= BIT(31); 6466 ew32(FEXTNVM12, mac_data); 6467 6468 /* Enable mPHY power gating for any link and speed */ 6469 mac_data = er32(FEXTNVM8); 6470 mac_data |= BIT(9); 6471 ew32(FEXTNVM8, mac_data); 6472 6473 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6474 mac_data = er32(CTRL_EXT); 6475 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6476 ew32(CTRL_EXT, mac_data); 6477 6478 /* No MAC DPG gating SLP_S0 in modern standby 6479 * Switch the logic of the lanphypc to use PMC counter 6480 */ 6481 mac_data = er32(FEXTNVM5); 6482 mac_data |= BIT(7); 6483 ew32(FEXTNVM5, mac_data); 6484 } 6485 6486 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6487 { 6488 struct e1000_hw *hw = &adapter->hw; 6489 u32 mac_data; 6490 u16 phy_data; 6491 6492 /* Disable the Dynamic Power Gating in the MAC */ 6493 mac_data = er32(FEXTNVM7); 6494 mac_data &= 0xFFBFFFFF; 6495 ew32(FEXTNVM7, mac_data); 6496 6497 /* Enable the time synchronization clock */ 6498 mac_data = er32(FEXTNVM7); 6499 mac_data |= BIT(0); 6500 ew32(FEXTNVM7, mac_data); 6501 6502 /* Disable mPHY power gating for any link and speed */ 6503 mac_data = er32(FEXTNVM8); 6504 mac_data &= ~BIT(9); 6505 ew32(FEXTNVM8, mac_data); 6506 6507 /* Disable K1 off */ 6508 mac_data = er32(FEXTNVM6); 6509 mac_data &= ~BIT(31); 6510 ew32(FEXTNVM12, mac_data); 6511 6512 /* Disable Ungate PGCB clock */ 6513 mac_data = er32(FEXTNVM9); 6514 mac_data &= ~BIT(28); 6515 ew32(FEXTNVM9, mac_data); 6516 6517 /* Cancel not waking from dynamic 6518 * Power Gating with clock request 6519 */ 6520 mac_data = er32(FEXTNVM12); 6521 mac_data &= ~BIT(12); 6522 ew32(FEXTNVM12, mac_data); 6523 6524 /* Cancel disable disconnected cable conditioning 6525 * for Power Gating 6526 */ 6527 mac_data = er32(DPGFR); 6528 mac_data &= ~BIT(2); 6529 ew32(DPGFR, mac_data); 6530 6531 /* Disable Dynamic Power Gating */ 6532 mac_data = er32(CTRL_EXT); 6533 mac_data &= 0xFFFFFFF7; 6534 ew32(CTRL_EXT, mac_data); 6535 6536 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6537 mac_data = er32(CTRL_EXT); 6538 mac_data &= 0xFFF7FFFF; 6539 ew32(CTRL_EXT, mac_data); 6540 6541 /* Revert the lanphypc logic to use the internal Gbe counter 6542 * and not the PMC counter 6543 */ 6544 mac_data = er32(FEXTNVM5); 6545 mac_data &= 0xFFFFFF7F; 6546 ew32(FEXTNVM5, mac_data); 6547 6548 /* Enable the periodic inband message, 6549 * Request PCIe clock in K1 page770_17[10:9] =01b 6550 */ 6551 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6552 phy_data &= 0xFBFF; 6553 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6554 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6555 6556 /* Return back configuration 6557 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6558 */ 6559 e1e_rphy(hw, I217_CGFREG, &phy_data); 6560 phy_data &= 0xFFDF; 6561 e1e_wphy(hw, I217_CGFREG, phy_data); 6562 6563 /* Change the MAC/PHY interface to Kumeran 6564 * Unforce the SMBus in PHY page769_23[0] = 0 6565 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6566 */ 6567 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6568 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6569 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6570 mac_data = er32(CTRL_EXT); 6571 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6572 ew32(CTRL_EXT, mac_data); 6573 } 6574 #endif /* CONFIG_PM_SLEEP */ 6575 6576 static int e1000e_pm_freeze(struct device *dev) 6577 { 6578 struct net_device *netdev = dev_get_drvdata(dev); 6579 struct e1000_adapter *adapter = netdev_priv(netdev); 6580 bool present; 6581 6582 rtnl_lock(); 6583 6584 present = netif_device_present(netdev); 6585 netif_device_detach(netdev); 6586 6587 if (present && netif_running(netdev)) { 6588 int count = E1000_CHECK_RESET_COUNT; 6589 6590 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6591 usleep_range(10000, 11000); 6592 6593 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6594 6595 /* Quiesce the device without resetting the hardware */ 6596 e1000e_down(adapter, false); 6597 e1000_free_irq(adapter); 6598 } 6599 rtnl_unlock(); 6600 6601 e1000e_reset_interrupt_capability(adapter); 6602 6603 /* Allow time for pending master requests to run */ 6604 e1000e_disable_pcie_master(&adapter->hw); 6605 6606 return 0; 6607 } 6608 6609 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6610 { 6611 struct net_device *netdev = pci_get_drvdata(pdev); 6612 struct e1000_adapter *adapter = netdev_priv(netdev); 6613 struct e1000_hw *hw = &adapter->hw; 6614 u32 ctrl, ctrl_ext, rctl, status; 6615 /* Runtime suspend should only enable wakeup for link changes */ 6616 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6617 int retval = 0; 6618 6619 status = er32(STATUS); 6620 if (status & E1000_STATUS_LU) 6621 wufc &= ~E1000_WUFC_LNKC; 6622 6623 if (wufc) { 6624 e1000_setup_rctl(adapter); 6625 e1000e_set_rx_mode(netdev); 6626 6627 /* turn on all-multi mode if wake on multicast is enabled */ 6628 if (wufc & E1000_WUFC_MC) { 6629 rctl = er32(RCTL); 6630 rctl |= E1000_RCTL_MPE; 6631 ew32(RCTL, rctl); 6632 } 6633 6634 ctrl = er32(CTRL); 6635 ctrl |= E1000_CTRL_ADVD3WUC; 6636 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6637 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6638 ew32(CTRL, ctrl); 6639 6640 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6641 adapter->hw.phy.media_type == 6642 e1000_media_type_internal_serdes) { 6643 /* keep the laser running in D3 */ 6644 ctrl_ext = er32(CTRL_EXT); 6645 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6646 ew32(CTRL_EXT, ctrl_ext); 6647 } 6648 6649 if (!runtime) 6650 e1000e_power_up_phy(adapter); 6651 6652 if (adapter->flags & FLAG_IS_ICH) 6653 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6654 6655 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6656 /* enable wakeup by the PHY */ 6657 retval = e1000_init_phy_wakeup(adapter, wufc); 6658 if (retval) 6659 return retval; 6660 } else { 6661 /* enable wakeup by the MAC */ 6662 ew32(WUFC, wufc); 6663 ew32(WUC, E1000_WUC_PME_EN); 6664 } 6665 } else { 6666 ew32(WUC, 0); 6667 ew32(WUFC, 0); 6668 6669 e1000_power_down_phy(adapter); 6670 } 6671 6672 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6673 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6674 } else if (hw->mac.type >= e1000_pch_lpt) { 6675 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6676 /* ULP does not support wake from unicast, multicast 6677 * or broadcast. 6678 */ 6679 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6680 6681 if (retval) 6682 return retval; 6683 } 6684 6685 /* Ensure that the appropriate bits are set in LPI_CTRL 6686 * for EEE in Sx 6687 */ 6688 if ((hw->phy.type >= e1000_phy_i217) && 6689 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6690 u16 lpi_ctrl = 0; 6691 6692 retval = hw->phy.ops.acquire(hw); 6693 if (!retval) { 6694 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6695 &lpi_ctrl); 6696 if (!retval) { 6697 if (adapter->eee_advert & 6698 hw->dev_spec.ich8lan.eee_lp_ability & 6699 I82579_EEE_100_SUPPORTED) 6700 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6701 if (adapter->eee_advert & 6702 hw->dev_spec.ich8lan.eee_lp_ability & 6703 I82579_EEE_1000_SUPPORTED) 6704 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6705 6706 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6707 lpi_ctrl); 6708 } 6709 } 6710 hw->phy.ops.release(hw); 6711 } 6712 6713 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6714 * would have already happened in close and is redundant. 6715 */ 6716 e1000e_release_hw_control(adapter); 6717 6718 pci_clear_master(pdev); 6719 6720 /* The pci-e switch on some quad port adapters will report a 6721 * correctable error when the MAC transitions from D0 to D3. To 6722 * prevent this we need to mask off the correctable errors on the 6723 * downstream port of the pci-e switch. 6724 * 6725 * We don't have the associated upstream bridge while assigning 6726 * the PCI device into guest. For example, the KVM on power is 6727 * one of the cases. 6728 */ 6729 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6730 struct pci_dev *us_dev = pdev->bus->self; 6731 u16 devctl; 6732 6733 if (!us_dev) 6734 return 0; 6735 6736 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6737 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6738 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6739 6740 pci_save_state(pdev); 6741 pci_prepare_to_sleep(pdev); 6742 6743 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6744 } 6745 6746 return 0; 6747 } 6748 6749 /** 6750 * __e1000e_disable_aspm - Disable ASPM states 6751 * @pdev: pointer to PCI device struct 6752 * @state: bit-mask of ASPM states to disable 6753 * @locked: indication if this context holds pci_bus_sem locked. 6754 * 6755 * Some devices *must* have certain ASPM states disabled per hardware errata. 6756 **/ 6757 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6758 { 6759 struct pci_dev *parent = pdev->bus->self; 6760 u16 aspm_dis_mask = 0; 6761 u16 pdev_aspmc, parent_aspmc; 6762 6763 switch (state) { 6764 case PCIE_LINK_STATE_L0S: 6765 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6766 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6767 /* fall-through - can't have L1 without L0s */ 6768 case PCIE_LINK_STATE_L1: 6769 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6770 break; 6771 default: 6772 return; 6773 } 6774 6775 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6776 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6777 6778 if (parent) { 6779 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6780 &parent_aspmc); 6781 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6782 } 6783 6784 /* Nothing to do if the ASPM states to be disabled already are */ 6785 if (!(pdev_aspmc & aspm_dis_mask) && 6786 (!parent || !(parent_aspmc & aspm_dis_mask))) 6787 return; 6788 6789 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6790 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6791 "L0s" : "", 6792 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6793 "L1" : ""); 6794 6795 #ifdef CONFIG_PCIEASPM 6796 if (locked) 6797 pci_disable_link_state_locked(pdev, state); 6798 else 6799 pci_disable_link_state(pdev, state); 6800 6801 /* Double-check ASPM control. If not disabled by the above, the 6802 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6803 * not enabled); override by writing PCI config space directly. 6804 */ 6805 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6806 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6807 6808 if (!(aspm_dis_mask & pdev_aspmc)) 6809 return; 6810 #endif 6811 6812 /* Both device and parent should have the same ASPM setting. 6813 * Disable ASPM in downstream component first and then upstream. 6814 */ 6815 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6816 6817 if (parent) 6818 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6819 aspm_dis_mask); 6820 } 6821 6822 /** 6823 * e1000e_disable_aspm - Disable ASPM states. 6824 * @pdev: pointer to PCI device struct 6825 * @state: bit-mask of ASPM states to disable 6826 * 6827 * This function acquires the pci_bus_sem! 6828 * Some devices *must* have certain ASPM states disabled per hardware errata. 6829 **/ 6830 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6831 { 6832 __e1000e_disable_aspm(pdev, state, 0); 6833 } 6834 6835 /** 6836 * e1000e_disable_aspm_locked Disable ASPM states. 6837 * @pdev: pointer to PCI device struct 6838 * @state: bit-mask of ASPM states to disable 6839 * 6840 * This function must be called with pci_bus_sem acquired! 6841 * Some devices *must* have certain ASPM states disabled per hardware errata. 6842 **/ 6843 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6844 { 6845 __e1000e_disable_aspm(pdev, state, 1); 6846 } 6847 6848 static int e1000e_pm_thaw(struct device *dev) 6849 { 6850 struct net_device *netdev = dev_get_drvdata(dev); 6851 struct e1000_adapter *adapter = netdev_priv(netdev); 6852 int rc = 0; 6853 6854 e1000e_set_interrupt_capability(adapter); 6855 6856 rtnl_lock(); 6857 if (netif_running(netdev)) { 6858 rc = e1000_request_irq(adapter); 6859 if (rc) 6860 goto err_irq; 6861 6862 e1000e_up(adapter); 6863 } 6864 6865 netif_device_attach(netdev); 6866 err_irq: 6867 rtnl_unlock(); 6868 6869 return rc; 6870 } 6871 6872 #ifdef CONFIG_PM 6873 static int __e1000_resume(struct pci_dev *pdev) 6874 { 6875 struct net_device *netdev = pci_get_drvdata(pdev); 6876 struct e1000_adapter *adapter = netdev_priv(netdev); 6877 struct e1000_hw *hw = &adapter->hw; 6878 u16 aspm_disable_flag = 0; 6879 6880 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6881 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6882 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6883 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6884 if (aspm_disable_flag) 6885 e1000e_disable_aspm(pdev, aspm_disable_flag); 6886 6887 pci_set_master(pdev); 6888 6889 if (hw->mac.type >= e1000_pch2lan) 6890 e1000_resume_workarounds_pchlan(&adapter->hw); 6891 6892 e1000e_power_up_phy(adapter); 6893 6894 /* report the system wakeup cause from S3/S4 */ 6895 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6896 u16 phy_data; 6897 6898 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6899 if (phy_data) { 6900 e_info("PHY Wakeup cause - %s\n", 6901 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6902 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6903 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6904 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6905 phy_data & E1000_WUS_LNKC ? 6906 "Link Status Change" : "other"); 6907 } 6908 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6909 } else { 6910 u32 wus = er32(WUS); 6911 6912 if (wus) { 6913 e_info("MAC Wakeup cause - %s\n", 6914 wus & E1000_WUS_EX ? "Unicast Packet" : 6915 wus & E1000_WUS_MC ? "Multicast Packet" : 6916 wus & E1000_WUS_BC ? "Broadcast Packet" : 6917 wus & E1000_WUS_MAG ? "Magic Packet" : 6918 wus & E1000_WUS_LNKC ? "Link Status Change" : 6919 "other"); 6920 } 6921 ew32(WUS, ~0); 6922 } 6923 6924 e1000e_reset(adapter); 6925 6926 e1000_init_manageability_pt(adapter); 6927 6928 /* If the controller has AMT, do not set DRV_LOAD until the interface 6929 * is up. For all other cases, let the f/w know that the h/w is now 6930 * under the control of the driver. 6931 */ 6932 if (!(adapter->flags & FLAG_HAS_AMT)) 6933 e1000e_get_hw_control(adapter); 6934 6935 return 0; 6936 } 6937 6938 #ifdef CONFIG_PM_SLEEP 6939 static int e1000e_pm_suspend(struct device *dev) 6940 { 6941 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6942 struct e1000_adapter *adapter = netdev_priv(netdev); 6943 struct pci_dev *pdev = to_pci_dev(dev); 6944 struct e1000_hw *hw = &adapter->hw; 6945 int rc; 6946 6947 e1000e_flush_lpic(pdev); 6948 6949 e1000e_pm_freeze(dev); 6950 6951 rc = __e1000_shutdown(pdev, false); 6952 if (rc) 6953 e1000e_pm_thaw(dev); 6954 6955 /* Introduce S0ix implementation */ 6956 if (hw->mac.type >= e1000_pch_cnp && 6957 !e1000e_check_me(hw->adapter->pdev->device)) 6958 e1000e_s0ix_entry_flow(adapter); 6959 6960 return rc; 6961 } 6962 6963 static int e1000e_pm_resume(struct device *dev) 6964 { 6965 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6966 struct e1000_adapter *adapter = netdev_priv(netdev); 6967 struct pci_dev *pdev = to_pci_dev(dev); 6968 struct e1000_hw *hw = &adapter->hw; 6969 int rc; 6970 6971 /* Introduce S0ix implementation */ 6972 if (hw->mac.type >= e1000_pch_cnp && 6973 !e1000e_check_me(hw->adapter->pdev->device)) 6974 e1000e_s0ix_exit_flow(adapter); 6975 6976 rc = __e1000_resume(pdev); 6977 if (rc) 6978 return rc; 6979 6980 return e1000e_pm_thaw(dev); 6981 } 6982 #endif /* CONFIG_PM_SLEEP */ 6983 6984 static int e1000e_pm_runtime_idle(struct device *dev) 6985 { 6986 struct net_device *netdev = dev_get_drvdata(dev); 6987 struct e1000_adapter *adapter = netdev_priv(netdev); 6988 u16 eee_lp; 6989 6990 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6991 6992 if (!e1000e_has_link(adapter)) { 6993 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6994 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6995 } 6996 6997 return -EBUSY; 6998 } 6999 7000 static int e1000e_pm_runtime_resume(struct device *dev) 7001 { 7002 struct pci_dev *pdev = to_pci_dev(dev); 7003 struct net_device *netdev = pci_get_drvdata(pdev); 7004 struct e1000_adapter *adapter = netdev_priv(netdev); 7005 int rc; 7006 7007 rc = __e1000_resume(pdev); 7008 if (rc) 7009 return rc; 7010 7011 if (netdev->flags & IFF_UP) 7012 e1000e_up(adapter); 7013 7014 return rc; 7015 } 7016 7017 static int e1000e_pm_runtime_suspend(struct device *dev) 7018 { 7019 struct pci_dev *pdev = to_pci_dev(dev); 7020 struct net_device *netdev = pci_get_drvdata(pdev); 7021 struct e1000_adapter *adapter = netdev_priv(netdev); 7022 7023 if (netdev->flags & IFF_UP) { 7024 int count = E1000_CHECK_RESET_COUNT; 7025 7026 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7027 usleep_range(10000, 11000); 7028 7029 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7030 7031 /* Down the device without resetting the hardware */ 7032 e1000e_down(adapter, false); 7033 } 7034 7035 if (__e1000_shutdown(pdev, true)) { 7036 e1000e_pm_runtime_resume(dev); 7037 return -EBUSY; 7038 } 7039 7040 return 0; 7041 } 7042 #endif /* CONFIG_PM */ 7043 7044 static void e1000_shutdown(struct pci_dev *pdev) 7045 { 7046 e1000e_flush_lpic(pdev); 7047 7048 e1000e_pm_freeze(&pdev->dev); 7049 7050 __e1000_shutdown(pdev, false); 7051 } 7052 7053 #ifdef CONFIG_NET_POLL_CONTROLLER 7054 7055 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7056 { 7057 struct net_device *netdev = data; 7058 struct e1000_adapter *adapter = netdev_priv(netdev); 7059 7060 if (adapter->msix_entries) { 7061 int vector, msix_irq; 7062 7063 vector = 0; 7064 msix_irq = adapter->msix_entries[vector].vector; 7065 if (disable_hardirq(msix_irq)) 7066 e1000_intr_msix_rx(msix_irq, netdev); 7067 enable_irq(msix_irq); 7068 7069 vector++; 7070 msix_irq = adapter->msix_entries[vector].vector; 7071 if (disable_hardirq(msix_irq)) 7072 e1000_intr_msix_tx(msix_irq, netdev); 7073 enable_irq(msix_irq); 7074 7075 vector++; 7076 msix_irq = adapter->msix_entries[vector].vector; 7077 if (disable_hardirq(msix_irq)) 7078 e1000_msix_other(msix_irq, netdev); 7079 enable_irq(msix_irq); 7080 } 7081 7082 return IRQ_HANDLED; 7083 } 7084 7085 /** 7086 * e1000_netpoll 7087 * @netdev: network interface device structure 7088 * 7089 * Polling 'interrupt' - used by things like netconsole to send skbs 7090 * without having to re-enable interrupts. It's not called while 7091 * the interrupt routine is executing. 7092 */ 7093 static void e1000_netpoll(struct net_device *netdev) 7094 { 7095 struct e1000_adapter *adapter = netdev_priv(netdev); 7096 7097 switch (adapter->int_mode) { 7098 case E1000E_INT_MODE_MSIX: 7099 e1000_intr_msix(adapter->pdev->irq, netdev); 7100 break; 7101 case E1000E_INT_MODE_MSI: 7102 if (disable_hardirq(adapter->pdev->irq)) 7103 e1000_intr_msi(adapter->pdev->irq, netdev); 7104 enable_irq(adapter->pdev->irq); 7105 break; 7106 default: /* E1000E_INT_MODE_LEGACY */ 7107 if (disable_hardirq(adapter->pdev->irq)) 7108 e1000_intr(adapter->pdev->irq, netdev); 7109 enable_irq(adapter->pdev->irq); 7110 break; 7111 } 7112 } 7113 #endif 7114 7115 /** 7116 * e1000_io_error_detected - called when PCI error is detected 7117 * @pdev: Pointer to PCI device 7118 * @state: The current pci connection state 7119 * 7120 * This function is called after a PCI bus error affecting 7121 * this device has been detected. 7122 */ 7123 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7124 pci_channel_state_t state) 7125 { 7126 e1000e_pm_freeze(&pdev->dev); 7127 7128 if (state == pci_channel_io_perm_failure) 7129 return PCI_ERS_RESULT_DISCONNECT; 7130 7131 pci_disable_device(pdev); 7132 7133 /* Request a slot slot reset. */ 7134 return PCI_ERS_RESULT_NEED_RESET; 7135 } 7136 7137 /** 7138 * e1000_io_slot_reset - called after the pci bus has been reset. 7139 * @pdev: Pointer to PCI device 7140 * 7141 * Restart the card from scratch, as if from a cold-boot. Implementation 7142 * resembles the first-half of the e1000e_pm_resume routine. 7143 */ 7144 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7145 { 7146 struct net_device *netdev = pci_get_drvdata(pdev); 7147 struct e1000_adapter *adapter = netdev_priv(netdev); 7148 struct e1000_hw *hw = &adapter->hw; 7149 u16 aspm_disable_flag = 0; 7150 int err; 7151 pci_ers_result_t result; 7152 7153 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7154 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7155 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7156 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7157 if (aspm_disable_flag) 7158 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7159 7160 err = pci_enable_device_mem(pdev); 7161 if (err) { 7162 dev_err(&pdev->dev, 7163 "Cannot re-enable PCI device after reset.\n"); 7164 result = PCI_ERS_RESULT_DISCONNECT; 7165 } else { 7166 pdev->state_saved = true; 7167 pci_restore_state(pdev); 7168 pci_set_master(pdev); 7169 7170 pci_enable_wake(pdev, PCI_D3hot, 0); 7171 pci_enable_wake(pdev, PCI_D3cold, 0); 7172 7173 e1000e_reset(adapter); 7174 ew32(WUS, ~0); 7175 result = PCI_ERS_RESULT_RECOVERED; 7176 } 7177 7178 return result; 7179 } 7180 7181 /** 7182 * e1000_io_resume - called when traffic can start flowing again. 7183 * @pdev: Pointer to PCI device 7184 * 7185 * This callback is called when the error recovery driver tells us that 7186 * its OK to resume normal operation. Implementation resembles the 7187 * second-half of the e1000e_pm_resume routine. 7188 */ 7189 static void e1000_io_resume(struct pci_dev *pdev) 7190 { 7191 struct net_device *netdev = pci_get_drvdata(pdev); 7192 struct e1000_adapter *adapter = netdev_priv(netdev); 7193 7194 e1000_init_manageability_pt(adapter); 7195 7196 e1000e_pm_thaw(&pdev->dev); 7197 7198 /* If the controller has AMT, do not set DRV_LOAD until the interface 7199 * is up. For all other cases, let the f/w know that the h/w is now 7200 * under the control of the driver. 7201 */ 7202 if (!(adapter->flags & FLAG_HAS_AMT)) 7203 e1000e_get_hw_control(adapter); 7204 } 7205 7206 static void e1000_print_device_info(struct e1000_adapter *adapter) 7207 { 7208 struct e1000_hw *hw = &adapter->hw; 7209 struct net_device *netdev = adapter->netdev; 7210 u32 ret_val; 7211 u8 pba_str[E1000_PBANUM_LENGTH]; 7212 7213 /* print bus type/speed/width info */ 7214 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7215 /* bus width */ 7216 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7217 "Width x1"), 7218 /* MAC address */ 7219 netdev->dev_addr); 7220 e_info("Intel(R) PRO/%s Network Connection\n", 7221 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7222 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7223 E1000_PBANUM_LENGTH); 7224 if (ret_val) 7225 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7226 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7227 hw->mac.type, hw->phy.type, pba_str); 7228 } 7229 7230 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7231 { 7232 struct e1000_hw *hw = &adapter->hw; 7233 int ret_val; 7234 u16 buf = 0; 7235 7236 if (hw->mac.type != e1000_82573) 7237 return; 7238 7239 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7240 le16_to_cpus(&buf); 7241 if (!ret_val && (!(buf & BIT(0)))) { 7242 /* Deep Smart Power Down (DSPD) */ 7243 dev_warn(&adapter->pdev->dev, 7244 "Warning: detected DSPD enabled in EEPROM\n"); 7245 } 7246 } 7247 7248 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7249 netdev_features_t features) 7250 { 7251 struct e1000_adapter *adapter = netdev_priv(netdev); 7252 struct e1000_hw *hw = &adapter->hw; 7253 7254 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7255 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7256 features &= ~NETIF_F_RXFCS; 7257 7258 /* Since there is no support for separate Rx/Tx vlan accel 7259 * enable/disable make sure Tx flag is always in same state as Rx. 7260 */ 7261 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7262 features |= NETIF_F_HW_VLAN_CTAG_TX; 7263 else 7264 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7265 7266 return features; 7267 } 7268 7269 static int e1000_set_features(struct net_device *netdev, 7270 netdev_features_t features) 7271 { 7272 struct e1000_adapter *adapter = netdev_priv(netdev); 7273 netdev_features_t changed = features ^ netdev->features; 7274 7275 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7276 adapter->flags |= FLAG_TSO_FORCE; 7277 7278 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7279 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7280 NETIF_F_RXALL))) 7281 return 0; 7282 7283 if (changed & NETIF_F_RXFCS) { 7284 if (features & NETIF_F_RXFCS) { 7285 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7286 } else { 7287 /* We need to take it back to defaults, which might mean 7288 * stripping is still disabled at the adapter level. 7289 */ 7290 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7291 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7292 else 7293 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7294 } 7295 } 7296 7297 netdev->features = features; 7298 7299 if (netif_running(netdev)) 7300 e1000e_reinit_locked(adapter); 7301 else 7302 e1000e_reset(adapter); 7303 7304 return 1; 7305 } 7306 7307 static const struct net_device_ops e1000e_netdev_ops = { 7308 .ndo_open = e1000e_open, 7309 .ndo_stop = e1000e_close, 7310 .ndo_start_xmit = e1000_xmit_frame, 7311 .ndo_get_stats64 = e1000e_get_stats64, 7312 .ndo_set_rx_mode = e1000e_set_rx_mode, 7313 .ndo_set_mac_address = e1000_set_mac, 7314 .ndo_change_mtu = e1000_change_mtu, 7315 .ndo_do_ioctl = e1000_ioctl, 7316 .ndo_tx_timeout = e1000_tx_timeout, 7317 .ndo_validate_addr = eth_validate_addr, 7318 7319 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7320 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7321 #ifdef CONFIG_NET_POLL_CONTROLLER 7322 .ndo_poll_controller = e1000_netpoll, 7323 #endif 7324 .ndo_set_features = e1000_set_features, 7325 .ndo_fix_features = e1000_fix_features, 7326 .ndo_features_check = passthru_features_check, 7327 }; 7328 7329 /** 7330 * e1000_probe - Device Initialization Routine 7331 * @pdev: PCI device information struct 7332 * @ent: entry in e1000_pci_tbl 7333 * 7334 * Returns 0 on success, negative on failure 7335 * 7336 * e1000_probe initializes an adapter identified by a pci_dev structure. 7337 * The OS initialization, configuring of the adapter private structure, 7338 * and a hardware reset occur. 7339 **/ 7340 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7341 { 7342 struct net_device *netdev; 7343 struct e1000_adapter *adapter; 7344 struct e1000_hw *hw; 7345 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7346 resource_size_t mmio_start, mmio_len; 7347 resource_size_t flash_start, flash_len; 7348 static int cards_found; 7349 u16 aspm_disable_flag = 0; 7350 int bars, i, err, pci_using_dac; 7351 u16 eeprom_data = 0; 7352 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7353 s32 ret_val = 0; 7354 7355 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7356 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7357 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7358 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7359 if (aspm_disable_flag) 7360 e1000e_disable_aspm(pdev, aspm_disable_flag); 7361 7362 err = pci_enable_device_mem(pdev); 7363 if (err) 7364 return err; 7365 7366 pci_using_dac = 0; 7367 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7368 if (!err) { 7369 pci_using_dac = 1; 7370 } else { 7371 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7372 if (err) { 7373 dev_err(&pdev->dev, 7374 "No usable DMA configuration, aborting\n"); 7375 goto err_dma; 7376 } 7377 } 7378 7379 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7380 err = pci_request_selected_regions_exclusive(pdev, bars, 7381 e1000e_driver_name); 7382 if (err) 7383 goto err_pci_reg; 7384 7385 /* AER (Advanced Error Reporting) hooks */ 7386 pci_enable_pcie_error_reporting(pdev); 7387 7388 pci_set_master(pdev); 7389 /* PCI config space info */ 7390 err = pci_save_state(pdev); 7391 if (err) 7392 goto err_alloc_etherdev; 7393 7394 err = -ENOMEM; 7395 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7396 if (!netdev) 7397 goto err_alloc_etherdev; 7398 7399 SET_NETDEV_DEV(netdev, &pdev->dev); 7400 7401 netdev->irq = pdev->irq; 7402 7403 pci_set_drvdata(pdev, netdev); 7404 adapter = netdev_priv(netdev); 7405 hw = &adapter->hw; 7406 adapter->netdev = netdev; 7407 adapter->pdev = pdev; 7408 adapter->ei = ei; 7409 adapter->pba = ei->pba; 7410 adapter->flags = ei->flags; 7411 adapter->flags2 = ei->flags2; 7412 adapter->hw.adapter = adapter; 7413 adapter->hw.mac.type = ei->mac; 7414 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7415 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7416 7417 mmio_start = pci_resource_start(pdev, 0); 7418 mmio_len = pci_resource_len(pdev, 0); 7419 7420 err = -EIO; 7421 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7422 if (!adapter->hw.hw_addr) 7423 goto err_ioremap; 7424 7425 if ((adapter->flags & FLAG_HAS_FLASH) && 7426 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7427 (hw->mac.type < e1000_pch_spt)) { 7428 flash_start = pci_resource_start(pdev, 1); 7429 flash_len = pci_resource_len(pdev, 1); 7430 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7431 if (!adapter->hw.flash_address) 7432 goto err_flashmap; 7433 } 7434 7435 /* Set default EEE advertisement */ 7436 if (adapter->flags2 & FLAG2_HAS_EEE) 7437 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7438 7439 /* construct the net_device struct */ 7440 netdev->netdev_ops = &e1000e_netdev_ops; 7441 e1000e_set_ethtool_ops(netdev); 7442 netdev->watchdog_timeo = 5 * HZ; 7443 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7444 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7445 7446 netdev->mem_start = mmio_start; 7447 netdev->mem_end = mmio_start + mmio_len; 7448 7449 adapter->bd_number = cards_found++; 7450 7451 e1000e_check_options(adapter); 7452 7453 /* setup adapter struct */ 7454 err = e1000_sw_init(adapter); 7455 if (err) 7456 goto err_sw_init; 7457 7458 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7459 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7460 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7461 7462 err = ei->get_variants(adapter); 7463 if (err) 7464 goto err_hw_init; 7465 7466 if ((adapter->flags & FLAG_IS_ICH) && 7467 (adapter->flags & FLAG_READ_ONLY_NVM) && 7468 (hw->mac.type < e1000_pch_spt)) 7469 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7470 7471 hw->mac.ops.get_bus_info(&adapter->hw); 7472 7473 adapter->hw.phy.autoneg_wait_to_complete = 0; 7474 7475 /* Copper options */ 7476 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7477 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7478 adapter->hw.phy.disable_polarity_correction = 0; 7479 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7480 } 7481 7482 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7483 dev_info(&pdev->dev, 7484 "PHY reset is blocked due to SOL/IDER session.\n"); 7485 7486 /* Set initial default active device features */ 7487 netdev->features = (NETIF_F_SG | 7488 NETIF_F_HW_VLAN_CTAG_RX | 7489 NETIF_F_HW_VLAN_CTAG_TX | 7490 NETIF_F_TSO | 7491 NETIF_F_TSO6 | 7492 NETIF_F_RXHASH | 7493 NETIF_F_RXCSUM | 7494 NETIF_F_HW_CSUM); 7495 7496 /* Set user-changeable features (subset of all device features) */ 7497 netdev->hw_features = netdev->features; 7498 netdev->hw_features |= NETIF_F_RXFCS; 7499 netdev->priv_flags |= IFF_SUPP_NOFCS; 7500 netdev->hw_features |= NETIF_F_RXALL; 7501 7502 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7503 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7504 7505 netdev->vlan_features |= (NETIF_F_SG | 7506 NETIF_F_TSO | 7507 NETIF_F_TSO6 | 7508 NETIF_F_HW_CSUM); 7509 7510 netdev->priv_flags |= IFF_UNICAST_FLT; 7511 7512 if (pci_using_dac) { 7513 netdev->features |= NETIF_F_HIGHDMA; 7514 netdev->vlan_features |= NETIF_F_HIGHDMA; 7515 } 7516 7517 /* MTU range: 68 - max_hw_frame_size */ 7518 netdev->min_mtu = ETH_MIN_MTU; 7519 netdev->max_mtu = adapter->max_hw_frame_size - 7520 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7521 7522 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7523 adapter->flags |= FLAG_MNG_PT_ENABLED; 7524 7525 /* before reading the NVM, reset the controller to 7526 * put the device in a known good starting state 7527 */ 7528 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7529 7530 /* systems with ASPM and others may see the checksum fail on the first 7531 * attempt. Let's give it a few tries 7532 */ 7533 for (i = 0;; i++) { 7534 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7535 break; 7536 if (i == 2) { 7537 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7538 err = -EIO; 7539 goto err_eeprom; 7540 } 7541 } 7542 7543 e1000_eeprom_checks(adapter); 7544 7545 /* copy the MAC address */ 7546 if (e1000e_read_mac_addr(&adapter->hw)) 7547 dev_err(&pdev->dev, 7548 "NVM Read Error while reading MAC address\n"); 7549 7550 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7551 7552 if (!is_valid_ether_addr(netdev->dev_addr)) { 7553 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7554 netdev->dev_addr); 7555 err = -EIO; 7556 goto err_eeprom; 7557 } 7558 7559 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7560 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7561 7562 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7563 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7564 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7565 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7566 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7567 7568 /* Initialize link parameters. User can change them with ethtool */ 7569 adapter->hw.mac.autoneg = 1; 7570 adapter->fc_autoneg = true; 7571 adapter->hw.fc.requested_mode = e1000_fc_default; 7572 adapter->hw.fc.current_mode = e1000_fc_default; 7573 adapter->hw.phy.autoneg_advertised = 0x2f; 7574 7575 /* Initial Wake on LAN setting - If APM wake is enabled in 7576 * the EEPROM, enable the ACPI Magic Packet filter 7577 */ 7578 if (adapter->flags & FLAG_APME_IN_WUC) { 7579 /* APME bit in EEPROM is mapped to WUC.APME */ 7580 eeprom_data = er32(WUC); 7581 eeprom_apme_mask = E1000_WUC_APME; 7582 if ((hw->mac.type > e1000_ich10lan) && 7583 (eeprom_data & E1000_WUC_PHY_WAKE)) 7584 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7585 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7586 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7587 (adapter->hw.bus.func == 1)) 7588 ret_val = e1000_read_nvm(&adapter->hw, 7589 NVM_INIT_CONTROL3_PORT_B, 7590 1, &eeprom_data); 7591 else 7592 ret_val = e1000_read_nvm(&adapter->hw, 7593 NVM_INIT_CONTROL3_PORT_A, 7594 1, &eeprom_data); 7595 } 7596 7597 /* fetch WoL from EEPROM */ 7598 if (ret_val) 7599 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7600 else if (eeprom_data & eeprom_apme_mask) 7601 adapter->eeprom_wol |= E1000_WUFC_MAG; 7602 7603 /* now that we have the eeprom settings, apply the special cases 7604 * where the eeprom may be wrong or the board simply won't support 7605 * wake on lan on a particular port 7606 */ 7607 if (!(adapter->flags & FLAG_HAS_WOL)) 7608 adapter->eeprom_wol = 0; 7609 7610 /* initialize the wol settings based on the eeprom settings */ 7611 adapter->wol = adapter->eeprom_wol; 7612 7613 /* make sure adapter isn't asleep if manageability is enabled */ 7614 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7615 (hw->mac.ops.check_mng_mode(hw))) 7616 device_wakeup_enable(&pdev->dev); 7617 7618 /* save off EEPROM version number */ 7619 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7620 7621 if (ret_val) { 7622 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7623 adapter->eeprom_vers = 0; 7624 } 7625 7626 /* init PTP hardware clock */ 7627 e1000e_ptp_init(adapter); 7628 7629 /* reset the hardware with the new settings */ 7630 e1000e_reset(adapter); 7631 7632 /* If the controller has AMT, do not set DRV_LOAD until the interface 7633 * is up. For all other cases, let the f/w know that the h/w is now 7634 * under the control of the driver. 7635 */ 7636 if (!(adapter->flags & FLAG_HAS_AMT)) 7637 e1000e_get_hw_control(adapter); 7638 7639 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7640 err = register_netdev(netdev); 7641 if (err) 7642 goto err_register; 7643 7644 /* carrier off reporting is important to ethtool even BEFORE open */ 7645 netif_carrier_off(netdev); 7646 7647 e1000_print_device_info(adapter); 7648 7649 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 7650 7651 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp) 7652 pm_runtime_put_noidle(&pdev->dev); 7653 7654 return 0; 7655 7656 err_register: 7657 if (!(adapter->flags & FLAG_HAS_AMT)) 7658 e1000e_release_hw_control(adapter); 7659 err_eeprom: 7660 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7661 e1000_phy_hw_reset(&adapter->hw); 7662 err_hw_init: 7663 kfree(adapter->tx_ring); 7664 kfree(adapter->rx_ring); 7665 err_sw_init: 7666 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7667 iounmap(adapter->hw.flash_address); 7668 e1000e_reset_interrupt_capability(adapter); 7669 err_flashmap: 7670 iounmap(adapter->hw.hw_addr); 7671 err_ioremap: 7672 free_netdev(netdev); 7673 err_alloc_etherdev: 7674 pci_release_mem_regions(pdev); 7675 err_pci_reg: 7676 err_dma: 7677 pci_disable_device(pdev); 7678 return err; 7679 } 7680 7681 /** 7682 * e1000_remove - Device Removal Routine 7683 * @pdev: PCI device information struct 7684 * 7685 * e1000_remove is called by the PCI subsystem to alert the driver 7686 * that it should release a PCI device. The could be caused by a 7687 * Hot-Plug event, or because the driver is going to be removed from 7688 * memory. 7689 **/ 7690 static void e1000_remove(struct pci_dev *pdev) 7691 { 7692 struct net_device *netdev = pci_get_drvdata(pdev); 7693 struct e1000_adapter *adapter = netdev_priv(netdev); 7694 7695 e1000e_ptp_remove(adapter); 7696 7697 /* The timers may be rescheduled, so explicitly disable them 7698 * from being rescheduled. 7699 */ 7700 set_bit(__E1000_DOWN, &adapter->state); 7701 del_timer_sync(&adapter->watchdog_timer); 7702 del_timer_sync(&adapter->phy_info_timer); 7703 7704 cancel_work_sync(&adapter->reset_task); 7705 cancel_work_sync(&adapter->watchdog_task); 7706 cancel_work_sync(&adapter->downshift_task); 7707 cancel_work_sync(&adapter->update_phy_task); 7708 cancel_work_sync(&adapter->print_hang_task); 7709 7710 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7711 cancel_work_sync(&adapter->tx_hwtstamp_work); 7712 if (adapter->tx_hwtstamp_skb) { 7713 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7714 adapter->tx_hwtstamp_skb = NULL; 7715 } 7716 } 7717 7718 unregister_netdev(netdev); 7719 7720 if (pci_dev_run_wake(pdev)) 7721 pm_runtime_get_noresume(&pdev->dev); 7722 7723 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7724 * would have already happened in close and is redundant. 7725 */ 7726 e1000e_release_hw_control(adapter); 7727 7728 e1000e_reset_interrupt_capability(adapter); 7729 kfree(adapter->tx_ring); 7730 kfree(adapter->rx_ring); 7731 7732 iounmap(adapter->hw.hw_addr); 7733 if ((adapter->hw.flash_address) && 7734 (adapter->hw.mac.type < e1000_pch_spt)) 7735 iounmap(adapter->hw.flash_address); 7736 pci_release_mem_regions(pdev); 7737 7738 free_netdev(netdev); 7739 7740 /* AER disable */ 7741 pci_disable_pcie_error_reporting(pdev); 7742 7743 pci_disable_device(pdev); 7744 } 7745 7746 /* PCI Error Recovery (ERS) */ 7747 static const struct pci_error_handlers e1000_err_handler = { 7748 .error_detected = e1000_io_error_detected, 7749 .slot_reset = e1000_io_slot_reset, 7750 .resume = e1000_io_resume, 7751 }; 7752 7753 static const struct pci_device_id e1000_pci_tbl[] = { 7754 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7755 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7757 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7758 board_82571 }, 7759 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7760 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7762 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7763 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7764 7765 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7766 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7767 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7768 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7769 7770 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7771 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7772 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7773 7774 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7775 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7776 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7777 7778 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7779 board_80003es2lan }, 7780 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7781 board_80003es2lan }, 7782 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7783 board_80003es2lan }, 7784 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7785 board_80003es2lan }, 7786 7787 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7788 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7790 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7795 7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7805 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7809 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7813 7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7818 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7821 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp }, 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp }, 7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp }, 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp }, 7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp }, 7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp }, 7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp }, 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp }, 7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp }, 7863 7864 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7865 }; 7866 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7867 7868 static const struct dev_pm_ops e1000_pm_ops = { 7869 #ifdef CONFIG_PM_SLEEP 7870 .suspend = e1000e_pm_suspend, 7871 .resume = e1000e_pm_resume, 7872 .freeze = e1000e_pm_freeze, 7873 .thaw = e1000e_pm_thaw, 7874 .poweroff = e1000e_pm_suspend, 7875 .restore = e1000e_pm_resume, 7876 #endif 7877 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7878 e1000e_pm_runtime_idle) 7879 }; 7880 7881 /* PCI Device API Driver */ 7882 static struct pci_driver e1000_driver = { 7883 .name = e1000e_driver_name, 7884 .id_table = e1000_pci_tbl, 7885 .probe = e1000_probe, 7886 .remove = e1000_remove, 7887 .driver = { 7888 .pm = &e1000_pm_ops, 7889 }, 7890 .shutdown = e1000_shutdown, 7891 .err_handler = &e1000_err_handler 7892 }; 7893 7894 /** 7895 * e1000_init_module - Driver Registration Routine 7896 * 7897 * e1000_init_module is the first routine called when the driver is 7898 * loaded. All it does is register with the PCI subsystem. 7899 **/ 7900 static int __init e1000_init_module(void) 7901 { 7902 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7903 e1000e_driver_version); 7904 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7905 7906 return pci_register_driver(&e1000_driver); 7907 } 7908 module_init(e1000_init_module); 7909 7910 /** 7911 * e1000_exit_module - Driver Exit Cleanup Routine 7912 * 7913 * e1000_exit_module is called just before the driver is removed 7914 * from memory. 7915 **/ 7916 static void __exit e1000_exit_module(void) 7917 { 7918 pci_unregister_driver(&e1000_driver); 7919 } 7920 module_exit(e1000_exit_module); 7921 7922 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7923 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7924 MODULE_LICENSE("GPL v2"); 7925 MODULE_VERSION(DRV_VERSION); 7926 7927 /* netdev.c */ 7928