1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Hardkernel Co., Ltd 4 * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH 5 */ 6 7/dts-v1/; 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include "rk3326.dtsi" 12 13/ { 14 model = "ODROID-GO Advance"; 15 compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; 16 17 chosen { 18 stdout-path = "serial2:115200n8"; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 power-supply = <&vcc_bl>; 24 pwms = <&pwm1 0 25000 0>; 25 }; 26 27 gpio-keys { 28 compatible = "gpio-keys"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&btn_pins>; 31 32 /* 33 * *** ODROIDGO2-Advance Switch layout *** 34 * |------------------------------------------------| 35 * | sw15 sw16 | 36 * |------------------------------------------------| 37 * | sw1 |-------------------| sw8 | 38 * | sw3 sw4 | | sw7 sw5 | 39 * | sw2 | LCD Display | sw6 | 40 * | | | | 41 * | |-------------------| | 42 * | sw9 sw10 sw11 sw12 sw13 sw14 | 43 * |------------------------------------------------| 44 */ 45 46 sw1 { 47 gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; 48 label = "DPAD-UP"; 49 linux,code = <BTN_DPAD_UP>; 50 }; 51 sw2 { 52 gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; 53 label = "DPAD-DOWN"; 54 linux,code = <BTN_DPAD_DOWN>; 55 }; 56 sw3 { 57 gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; 58 label = "DPAD-LEFT"; 59 linux,code = <BTN_DPAD_LEFT>; 60 }; 61 sw4 { 62 gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; 63 label = "DPAD-RIGHT"; 64 linux,code = <BTN_DPAD_RIGHT>; 65 }; 66 sw5 { 67 gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; 68 label = "BTN-A"; 69 linux,code = <BTN_EAST>; 70 }; 71 sw6 { 72 gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; 73 label = "BTN-B"; 74 linux,code = <BTN_SOUTH>; 75 }; 76 sw7 { 77 gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; 78 label = "BTN-Y"; 79 linux,code = <BTN_WEST>; 80 }; 81 sw8 { 82 gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; 83 label = "BTN-X"; 84 linux,code = <BTN_NORTH>; 85 }; 86 sw9 { 87 gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; 88 label = "F1"; 89 linux,code = <BTN_TRIGGER_HAPPY1>; 90 }; 91 sw10 { 92 gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; 93 label = "F2"; 94 linux,code = <BTN_TRIGGER_HAPPY2>; 95 }; 96 sw11 { 97 gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; 98 label = "F3"; 99 linux,code = <BTN_TRIGGER_HAPPY3>; 100 }; 101 sw12 { 102 gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; 103 label = "F4"; 104 linux,code = <BTN_TRIGGER_HAPPY4>; 105 }; 106 sw13 { 107 gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; 108 label = "F5"; 109 linux,code = <BTN_TRIGGER_HAPPY5>; 110 }; 111 sw14 { 112 gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; 113 label = "F6"; 114 linux,code = <BTN_TRIGGER_HAPPY6>; 115 }; 116 sw15 { 117 gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; 118 label = "TOP-LEFT"; 119 linux,code = <BTN_TL>; 120 }; 121 sw16 { 122 gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; 123 label = "TOP-RIGHT"; 124 linux,code = <BTN_TR>; 125 }; 126 }; 127 128 leds: gpio-leds { 129 compatible = "gpio-leds"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&blue_led_pin>; 132 133 blue_led: led-0 { 134 label = "blue:heartbeat"; 135 gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 136 linux,default-trigger = "heartbeat"; 137 }; 138 }; 139 140 vccsys: vccsys { 141 compatible = "regulator-fixed"; 142 regulator-name = "vcc3v8_sys"; 143 regulator-always-on; 144 regulator-min-microvolt = <3800000>; 145 regulator-max-microvolt = <3800000>; 146 }; 147 148 vcc_host: vcc_host { 149 compatible = "regulator-fixed"; 150 regulator-name = "vcc_host"; 151 regulator-min-microvolt = <5000000>; 152 regulator-max-microvolt = <5000000>; 153 154 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 155 enable-active-high; 156 regulator-always-on; 157 vin-supply = <&vccsys>; 158 }; 159}; 160 161&cpu0 { 162 cpu-supply = <&vdd_arm>; 163}; 164 165&cpu1 { 166 cpu-supply = <&vdd_arm>; 167}; 168 169&cpu2 { 170 cpu-supply = <&vdd_arm>; 171}; 172 173&cpu3 { 174 cpu-supply = <&vdd_arm>; 175}; 176 177&cru { 178 assigned-clocks = <&cru PLL_NPLL>, 179 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 180 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 181 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, 182 <&cru PLL_CPLL>; 183 184 assigned-clock-rates = <1188000000>, 185 <200000000>, <200000000>, 186 <150000000>, <150000000>, 187 <100000000>, <200000000>, 188 <17000000>; 189}; 190 191&display_subsystem { 192 status = "okay"; 193}; 194 195&dsi { 196 status = "okay"; 197 198 ports { 199 mipi_out: port@1 { 200 reg = <1>; 201 202 mipi_out_panel: endpoint { 203 remote-endpoint = <&mipi_in_panel>; 204 }; 205 }; 206 }; 207 208 panel@0 { 209 compatible = "elida,kd35t133"; 210 reg = <0>; 211 backlight = <&backlight>; 212 iovcc-supply = <&vcc_lcd>; 213 reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; 214 vdd-supply = <&vcc_lcd>; 215 216 port { 217 mipi_in_panel: endpoint { 218 remote-endpoint = <&mipi_out_panel>; 219 }; 220 }; 221 }; 222}; 223 224&dsi_dphy { 225 status = "okay"; 226}; 227 228&gpu { 229 mali-supply = <&vdd_logic>; 230 status = "okay"; 231}; 232 233&i2c0 { 234 clock-frequency = <400000>; 235 i2c-scl-falling-time-ns = <16>; 236 i2c-scl-rising-time-ns = <280>; 237 status = "okay"; 238 239 rk817: pmic@20 { 240 compatible = "rockchip,rk817"; 241 reg = <0x20>; 242 interrupt-parent = <&gpio0>; 243 interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pmic_int>; 246 rockchip,system-power-controller; 247 wakeup-source; 248 #clock-cells = <1>; 249 clock-output-names = "rk808-clkout1", "xin32k"; 250 251 vcc1-supply = <&vccsys>; 252 vcc2-supply = <&vccsys>; 253 vcc3-supply = <&vccsys>; 254 vcc4-supply = <&vccsys>; 255 vcc5-supply = <&vccsys>; 256 vcc6-supply = <&vccsys>; 257 vcc7-supply = <&vccsys>; 258 259 regulators { 260 vdd_logic: DCDC_REG1 { 261 regulator-name = "vdd_logic"; 262 regulator-min-microvolt = <950000>; 263 regulator-max-microvolt = <1150000>; 264 regulator-ramp-delay = <6001>; 265 regulator-always-on; 266 regulator-boot-on; 267 268 regulator-state-mem { 269 regulator-on-in-suspend; 270 regulator-suspend-microvolt = <950000>; 271 }; 272 }; 273 274 vdd_arm: DCDC_REG2 { 275 regulator-name = "vdd_arm"; 276 regulator-min-microvolt = <950000>; 277 regulator-max-microvolt = <1350000>; 278 regulator-ramp-delay = <6001>; 279 regulator-always-on; 280 regulator-boot-on; 281 282 regulator-state-mem { 283 regulator-off-in-suspend; 284 regulator-suspend-microvolt = <950000>; 285 }; 286 }; 287 288 vcc_ddr: DCDC_REG3 { 289 regulator-name = "vcc_ddr"; 290 regulator-always-on; 291 regulator-boot-on; 292 293 regulator-state-mem { 294 regulator-on-in-suspend; 295 }; 296 }; 297 298 vcc_3v3: DCDC_REG4 { 299 regulator-name = "vcc_3v3"; 300 regulator-min-microvolt = <3300000>; 301 regulator-max-microvolt = <3300000>; 302 regulator-always-on; 303 regulator-boot-on; 304 305 regulator-state-mem { 306 regulator-off-in-suspend; 307 regulator-suspend-microvolt = <3300000>; 308 }; 309 }; 310 311 vcc_1v8: LDO_REG2 { 312 regulator-name = "vcc_1v8"; 313 regulator-min-microvolt = <1800000>; 314 regulator-max-microvolt = <1800000>; 315 regulator-always-on; 316 regulator-boot-on; 317 318 regulator-state-mem { 319 regulator-on-in-suspend; 320 regulator-suspend-microvolt = <1800000>; 321 }; 322 }; 323 324 vdd_1v0: LDO_REG3 { 325 regulator-name = "vdd_1v0"; 326 regulator-min-microvolt = <1000000>; 327 regulator-max-microvolt = <1000000>; 328 regulator-always-on; 329 regulator-boot-on; 330 331 regulator-state-mem { 332 regulator-on-in-suspend; 333 regulator-suspend-microvolt = <1000000>; 334 }; 335 }; 336 337 vcc3v3_pmu: LDO_REG4 { 338 regulator-name = "vcc3v3_pmu"; 339 regulator-min-microvolt = <3300000>; 340 regulator-max-microvolt = <3300000>; 341 regulator-always-on; 342 regulator-boot-on; 343 344 regulator-state-mem { 345 regulator-on-in-suspend; 346 regulator-suspend-microvolt = <3300000>; 347 }; 348 }; 349 350 vccio_sd: LDO_REG5 { 351 regulator-name = "vccio_sd"; 352 regulator-min-microvolt = <1800000>; 353 regulator-max-microvolt = <3300000>; 354 regulator-always-on; 355 regulator-boot-on; 356 357 regulator-state-mem { 358 regulator-on-in-suspend; 359 regulator-suspend-microvolt = <3300000>; 360 }; 361 }; 362 363 vcc_sd: LDO_REG6 { 364 regulator-name = "vcc_sd"; 365 regulator-min-microvolt = <3300000>; 366 regulator-max-microvolt = <3300000>; 367 regulator-boot-on; 368 369 regulator-state-mem { 370 regulator-on-in-suspend; 371 regulator-suspend-microvolt = <3300000>; 372 }; 373 }; 374 375 vcc_bl: LDO_REG7 { 376 regulator-name = "vcc_bl"; 377 regulator-min-microvolt = <3300000>; 378 regulator-max-microvolt = <3300000>; 379 380 regulator-state-mem { 381 regulator-off-in-suspend; 382 regulator-suspend-microvolt = <3300000>; 383 }; 384 }; 385 386 vcc_lcd: LDO_REG8 { 387 regulator-name = "vcc_lcd"; 388 regulator-min-microvolt = <2800000>; 389 regulator-max-microvolt = <2800000>; 390 391 regulator-state-mem { 392 regulator-off-in-suspend; 393 regulator-suspend-microvolt = <2800000>; 394 }; 395 }; 396 397 vcc_cam: LDO_REG9 { 398 regulator-name = "vcc_cam"; 399 regulator-min-microvolt = <3000000>; 400 regulator-max-microvolt = <3000000>; 401 402 regulator-state-mem { 403 regulator-off-in-suspend; 404 regulator-suspend-microvolt = <3000000>; 405 }; 406 }; 407 }; 408 }; 409}; 410 411/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ 412&i2c1 { 413 clock-frequency = <400000>; 414 status = "okay"; 415}; 416 417/* I2S 1 Channel Used */ 418&i2s1_2ch { 419 status = "okay"; 420}; 421 422&io_domains { 423 vccio1-supply = <&vcc_3v3>; 424 vccio2-supply = <&vccio_sd>; 425 vccio3-supply = <&vcc_3v3>; 426 vccio4-supply = <&vcc_3v3>; 427 vccio5-supply = <&vcc_3v3>; 428 vccio6-supply = <&vcc_3v3>; 429 status = "okay"; 430}; 431 432&pmu_io_domains { 433 pmuio1-supply = <&vcc3v3_pmu>; 434 pmuio2-supply = <&vcc3v3_pmu>; 435 status = "okay"; 436}; 437 438&pwm1 { 439 status = "okay"; 440}; 441 442&saradc { 443 vref-supply = <&vcc_1v8>; 444 status = "okay"; 445}; 446 447&sdmmc { 448 cap-sd-highspeed; 449 card-detect-delay = <200>; 450 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ 451 sd-uhs-sdr12; 452 sd-uhs-sdr25; 453 sd-uhs-sdr50; 454 sd-uhs-sdr104; 455 vmmc-supply = <&vcc_sd>; 456 vqmmc-supply = <&vccio_sd>; 457 status = "okay"; 458}; 459 460&tsadc { 461 status = "okay"; 462}; 463 464&u2phy { 465 status = "okay"; 466 467 u2phy_host: host-port { 468 status = "okay"; 469 }; 470 471 u2phy_otg: otg-port { 472 status = "disabled"; 473 }; 474}; 475 476&usb20_otg { 477 status = "okay"; 478}; 479 480/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ 481&uart1 { 482 pinctrl-names = "default"; 483 pinctrl-0 = <&uart1_xfer &uart1_cts>; 484 status = "okay"; 485}; 486 487&uart2 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&uart2m1_xfer>; 490 status = "okay"; 491}; 492 493&vopb { 494 status = "okay"; 495}; 496 497&vopb_mmu { 498 status = "okay"; 499}; 500 501&pinctrl { 502 btns { 503 btn_pins: btn-pins { 504 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, 505 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, 506 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, 507 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, 508 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, 509 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, 510 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, 511 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, 512 <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, 513 <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, 514 <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, 515 <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, 516 <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, 517 <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, 518 <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, 519 <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 520 }; 521 }; 522 523 headphone { 524 hp_det: hp-det { 525 rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; 526 }; 527 }; 528 529 leds { 530 blue_led_pin: blue-led-pin { 531 rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 532 }; 533 }; 534 535 pmic { 536 dc_det: dc-det { 537 rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 538 }; 539 540 pmic_int: pmic-int { 541 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; 542 }; 543 544 soc_slppin_gpio: soc_slppin_gpio { 545 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 546 }; 547 548 soc_slppin_rst: soc_slppin_rst { 549 rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; 550 }; 551 552 soc_slppin_slp: soc_slppin_slp { 553 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 554 }; 555 }; 556}; 557