1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Seung-Woo Kim <sw0312.kim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * Joonyoung Shim <jy0922.shim@samsung.com> 8 * 9 * Based on drivers/media/video/s5p-tv/hdmi_drv.c 10 */ 11 12 #include <drm/exynos_drm.h> 13 #include <linux/clk.h> 14 #include <linux/component.h> 15 #include <linux/delay.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/hdmi.h> 18 #include <linux/i2c.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_graph.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/regmap.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/wait.h> 32 33 #include <sound/hdmi-codec.h> 34 #include <media/cec-notifier.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_bridge.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "exynos_drm_crtc.h" 43 #include "regs-hdmi.h" 44 45 #define HOTPLUG_DEBOUNCE_MS 1100 46 47 enum hdmi_type { 48 HDMI_TYPE13, 49 HDMI_TYPE14, 50 HDMI_TYPE_COUNT 51 }; 52 53 #define HDMI_MAPPED_BASE 0xffff0000 54 55 enum hdmi_mapped_regs { 56 HDMI_PHY_STATUS = HDMI_MAPPED_BASE, 57 HDMI_PHY_RSTOUT, 58 HDMI_ACR_CON, 59 HDMI_ACR_MCTS0, 60 HDMI_ACR_CTS0, 61 HDMI_ACR_N0 62 }; 63 64 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = { 65 { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 }, 66 { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT }, 67 { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON }, 68 { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 }, 69 { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 }, 70 { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 }, 71 }; 72 73 static const char * const supply[] = { 74 "vdd", 75 "vdd_osc", 76 "vdd_pll", 77 }; 78 79 struct hdmiphy_config { 80 int pixel_clock; 81 u8 conf[32]; 82 }; 83 84 struct hdmiphy_configs { 85 int count; 86 const struct hdmiphy_config *data; 87 }; 88 89 struct string_array_spec { 90 int count; 91 const char * const *data; 92 }; 93 94 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a } 95 96 struct hdmi_driver_data { 97 unsigned int type; 98 unsigned int is_apb_phy:1; 99 unsigned int has_sysreg:1; 100 struct hdmiphy_configs phy_confs; 101 struct string_array_spec clk_gates; 102 /* 103 * Array of triplets (p_off, p_on, clock), where p_off and p_on are 104 * required parents of clock when HDMI-PHY is respectively off or on. 105 */ 106 struct string_array_spec clk_muxes; 107 }; 108 109 struct hdmi_audio { 110 struct platform_device *pdev; 111 struct hdmi_audio_infoframe infoframe; 112 struct hdmi_codec_params params; 113 bool mute; 114 }; 115 116 struct hdmi_context { 117 struct drm_encoder encoder; 118 struct device *dev; 119 struct drm_device *drm_dev; 120 struct drm_connector connector; 121 bool dvi_mode; 122 struct delayed_work hotplug_work; 123 struct cec_notifier *notifier; 124 const struct hdmi_driver_data *drv_data; 125 126 void __iomem *regs; 127 void __iomem *regs_hdmiphy; 128 struct i2c_client *hdmiphy_port; 129 struct i2c_adapter *ddc_adpt; 130 struct gpio_desc *hpd_gpio; 131 int irq; 132 struct regmap *pmureg; 133 struct regmap *sysreg; 134 struct clk **clk_gates; 135 struct clk **clk_muxes; 136 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; 137 struct regulator *reg_hdmi_en; 138 struct exynos_drm_clk phy_clk; 139 struct drm_bridge *bridge; 140 141 /* mutex protecting subsequent fields below */ 142 struct mutex mutex; 143 struct hdmi_audio audio; 144 bool powered; 145 }; 146 147 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) 148 { 149 return container_of(e, struct hdmi_context, encoder); 150 } 151 152 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c) 153 { 154 return container_of(c, struct hdmi_context, connector); 155 } 156 157 static const struct hdmiphy_config hdmiphy_v13_configs[] = { 158 { 159 .pixel_clock = 27000000, 160 .conf = { 161 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 162 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 163 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 164 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 165 }, 166 }, 167 { 168 .pixel_clock = 27027000, 169 .conf = { 170 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 171 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 172 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 173 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 174 }, 175 }, 176 { 177 .pixel_clock = 74176000, 178 .conf = { 179 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 180 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 181 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 182 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80, 183 }, 184 }, 185 { 186 .pixel_clock = 74250000, 187 .conf = { 188 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 189 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 190 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, 191 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80, 192 }, 193 }, 194 { 195 .pixel_clock = 148500000, 196 .conf = { 197 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 198 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 199 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, 200 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80, 201 }, 202 }, 203 }; 204 205 static const struct hdmiphy_config hdmiphy_v14_configs[] = { 206 { 207 .pixel_clock = 25200000, 208 .conf = { 209 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08, 210 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 211 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 212 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 213 }, 214 }, 215 { 216 .pixel_clock = 27000000, 217 .conf = { 218 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20, 219 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, 220 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 221 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 222 }, 223 }, 224 { 225 .pixel_clock = 27027000, 226 .conf = { 227 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, 228 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 229 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 230 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 231 }, 232 }, 233 { 234 .pixel_clock = 36000000, 235 .conf = { 236 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08, 237 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 238 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 239 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 240 }, 241 }, 242 { 243 .pixel_clock = 40000000, 244 .conf = { 245 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08, 246 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 247 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 248 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 249 }, 250 }, 251 { 252 .pixel_clock = 65000000, 253 .conf = { 254 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08, 255 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, 256 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 257 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 258 }, 259 }, 260 { 261 .pixel_clock = 71000000, 262 .conf = { 263 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08, 264 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 265 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 266 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 267 }, 268 }, 269 { 270 .pixel_clock = 73250000, 271 .conf = { 272 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08, 273 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 274 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 275 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 276 }, 277 }, 278 { 279 .pixel_clock = 74176000, 280 .conf = { 281 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, 282 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 283 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 284 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 285 }, 286 }, 287 { 288 .pixel_clock = 74250000, 289 .conf = { 290 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, 291 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 292 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 293 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 294 }, 295 }, 296 { 297 .pixel_clock = 83500000, 298 .conf = { 299 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08, 300 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 301 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 302 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 303 }, 304 }, 305 { 306 .pixel_clock = 85500000, 307 .conf = { 308 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08, 309 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80, 310 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 311 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 312 }, 313 }, 314 { 315 .pixel_clock = 106500000, 316 .conf = { 317 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, 318 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 319 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 320 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 321 }, 322 }, 323 { 324 .pixel_clock = 108000000, 325 .conf = { 326 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08, 327 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 328 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 329 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 330 }, 331 }, 332 { 333 .pixel_clock = 115500000, 334 .conf = { 335 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08, 336 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, 337 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 338 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 339 }, 340 }, 341 { 342 .pixel_clock = 119000000, 343 .conf = { 344 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08, 345 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 346 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 347 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 348 }, 349 }, 350 { 351 .pixel_clock = 146250000, 352 .conf = { 353 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, 354 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 355 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 356 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 357 }, 358 }, 359 { 360 .pixel_clock = 148500000, 361 .conf = { 362 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, 363 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 364 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 365 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 366 }, 367 }, 368 }; 369 370 static const struct hdmiphy_config hdmiphy_5420_configs[] = { 371 { 372 .pixel_clock = 25200000, 373 .conf = { 374 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8, 375 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 376 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66, 377 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 378 }, 379 }, 380 { 381 .pixel_clock = 27000000, 382 .conf = { 383 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0, 384 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 385 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 386 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 387 }, 388 }, 389 { 390 .pixel_clock = 27027000, 391 .conf = { 392 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8, 393 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 394 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 395 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 396 }, 397 }, 398 { 399 .pixel_clock = 36000000, 400 .conf = { 401 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8, 402 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 403 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 404 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 405 }, 406 }, 407 { 408 .pixel_clock = 40000000, 409 .conf = { 410 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8, 411 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 412 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 413 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 414 }, 415 }, 416 { 417 .pixel_clock = 65000000, 418 .conf = { 419 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8, 420 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 421 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 422 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 423 }, 424 }, 425 { 426 .pixel_clock = 71000000, 427 .conf = { 428 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8, 429 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 430 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 431 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 432 }, 433 }, 434 { 435 .pixel_clock = 73250000, 436 .conf = { 437 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8, 438 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 439 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 440 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 441 }, 442 }, 443 { 444 .pixel_clock = 74176000, 445 .conf = { 446 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, 447 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 448 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 449 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 450 }, 451 }, 452 { 453 .pixel_clock = 74250000, 454 .conf = { 455 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08, 456 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 457 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 458 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 459 }, 460 }, 461 { 462 .pixel_clock = 83500000, 463 .conf = { 464 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8, 465 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 466 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 467 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 468 }, 469 }, 470 { 471 .pixel_clock = 88750000, 472 .conf = { 473 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8, 474 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 475 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 476 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 477 }, 478 }, 479 { 480 .pixel_clock = 106500000, 481 .conf = { 482 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8, 483 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 484 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 485 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 486 }, 487 }, 488 { 489 .pixel_clock = 108000000, 490 .conf = { 491 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, 492 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 493 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 494 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 495 }, 496 }, 497 { 498 .pixel_clock = 115500000, 499 .conf = { 500 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8, 501 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 502 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 503 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 504 }, 505 }, 506 { 507 .pixel_clock = 146250000, 508 .conf = { 509 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8, 510 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 511 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 512 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 513 }, 514 }, 515 { 516 .pixel_clock = 148500000, 517 .conf = { 518 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08, 519 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 520 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 521 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80, 522 }, 523 }, 524 }; 525 526 static const struct hdmiphy_config hdmiphy_5433_configs[] = { 527 { 528 .pixel_clock = 27000000, 529 .conf = { 530 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02, 531 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 532 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 533 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 534 }, 535 }, 536 { 537 .pixel_clock = 27027000, 538 .conf = { 539 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3, 540 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 541 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 542 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 543 }, 544 }, 545 { 546 .pixel_clock = 40000000, 547 .conf = { 548 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02, 549 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 550 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 551 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 552 }, 553 }, 554 { 555 .pixel_clock = 50000000, 556 .conf = { 557 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3, 558 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 559 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 560 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 561 }, 562 }, 563 { 564 .pixel_clock = 65000000, 565 .conf = { 566 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6, 567 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 568 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 569 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 570 }, 571 }, 572 { 573 .pixel_clock = 74176000, 574 .conf = { 575 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42, 576 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 577 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 578 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 579 }, 580 }, 581 { 582 .pixel_clock = 74250000, 583 .conf = { 584 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2, 585 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 586 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 587 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 588 }, 589 }, 590 { 591 .pixel_clock = 108000000, 592 .conf = { 593 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02, 594 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 595 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 596 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 597 }, 598 }, 599 { 600 .pixel_clock = 148500000, 601 .conf = { 602 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1, 603 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5, 604 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30, 605 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, 606 }, 607 }, 608 { 609 .pixel_clock = 297000000, 610 .conf = { 611 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2, 612 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 613 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 614 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 615 }, 616 }, 617 }; 618 619 static const char * const hdmi_clk_gates4[] = { 620 "hdmi", "sclk_hdmi" 621 }; 622 623 static const char * const hdmi_clk_muxes4[] = { 624 "sclk_pixel", "sclk_hdmiphy", "mout_hdmi" 625 }; 626 627 static const char * const hdmi_clk_gates5433[] = { 628 "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk" 629 }; 630 631 static const char * const hdmi_clk_muxes5433[] = { 632 "oscclk", "tmds_clko", "tmds_clko_user", 633 "oscclk", "pixel_clko", "pixel_clko_user" 634 }; 635 636 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = { 637 .type = HDMI_TYPE13, 638 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs), 639 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 640 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 641 }; 642 643 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = { 644 .type = HDMI_TYPE14, 645 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs), 646 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 647 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 648 }; 649 650 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = { 651 .type = HDMI_TYPE14, 652 .is_apb_phy = 1, 653 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs), 654 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 655 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 656 }; 657 658 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = { 659 .type = HDMI_TYPE14, 660 .is_apb_phy = 1, 661 .has_sysreg = 1, 662 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs), 663 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433), 664 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433), 665 }; 666 667 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id) 668 { 669 if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE) 670 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type]; 671 return reg_id; 672 } 673 674 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id) 675 { 676 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id)); 677 } 678 679 static inline void hdmi_reg_writeb(struct hdmi_context *hdata, 680 u32 reg_id, u8 value) 681 { 682 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id)); 683 } 684 685 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, 686 int bytes, u32 val) 687 { 688 reg_id = hdmi_map_reg(hdata, reg_id); 689 690 while (--bytes >= 0) { 691 writel(val & 0xff, hdata->regs + reg_id); 692 val >>= 8; 693 reg_id += 4; 694 } 695 } 696 697 static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id, 698 u8 *buf, int size) 699 { 700 for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4) 701 writel(*buf++, hdata->regs + reg_id); 702 } 703 704 static inline void hdmi_reg_writemask(struct hdmi_context *hdata, 705 u32 reg_id, u32 value, u32 mask) 706 { 707 u32 old; 708 709 reg_id = hdmi_map_reg(hdata, reg_id); 710 old = readl(hdata->regs + reg_id); 711 value = (value & mask) | (old & ~mask); 712 writel(value, hdata->regs + reg_id); 713 } 714 715 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, 716 u32 reg_offset, const u8 *buf, u32 len) 717 { 718 if ((reg_offset + len) > 32) 719 return -EINVAL; 720 721 if (hdata->hdmiphy_port) { 722 int ret; 723 724 ret = i2c_master_send(hdata->hdmiphy_port, buf, len); 725 if (ret == len) 726 return 0; 727 return ret; 728 } else { 729 int i; 730 for (i = 0; i < len; i++) 731 writel(buf[i], hdata->regs_hdmiphy + 732 ((reg_offset + i)<<2)); 733 return 0; 734 } 735 } 736 737 static int hdmi_clk_enable_gates(struct hdmi_context *hdata) 738 { 739 int i, ret; 740 741 for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) { 742 ret = clk_prepare_enable(hdata->clk_gates[i]); 743 if (!ret) 744 continue; 745 746 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n", 747 hdata->drv_data->clk_gates.data[i], ret); 748 while (i--) 749 clk_disable_unprepare(hdata->clk_gates[i]); 750 return ret; 751 } 752 753 return 0; 754 } 755 756 static void hdmi_clk_disable_gates(struct hdmi_context *hdata) 757 { 758 int i = hdata->drv_data->clk_gates.count; 759 760 while (i--) 761 clk_disable_unprepare(hdata->clk_gates[i]); 762 } 763 764 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy) 765 { 766 struct device *dev = hdata->dev; 767 int ret = 0; 768 int i; 769 770 for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) { 771 struct clk **c = &hdata->clk_muxes[i]; 772 773 ret = clk_set_parent(c[2], c[to_phy]); 774 if (!ret) 775 continue; 776 777 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n", 778 hdata->drv_data->clk_muxes.data[i + 2], 779 hdata->drv_data->clk_muxes.data[i + to_phy], ret); 780 } 781 782 return ret; 783 } 784 785 static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata) 786 { 787 struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe; 788 u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; 789 int len; 790 791 len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf)); 792 if (len < 0) 793 return len; 794 795 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); 796 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len); 797 798 return 0; 799 } 800 801 static void hdmi_reg_infoframes(struct hdmi_context *hdata) 802 { 803 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 804 union hdmi_infoframe frm; 805 u8 buf[25]; 806 int ret; 807 808 if (hdata->dvi_mode) { 809 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 810 HDMI_AVI_CON_DO_NOT_TRANSMIT); 811 hdmi_reg_writeb(hdata, HDMI_VSI_CON, 812 HDMI_VSI_CON_DO_NOT_TRANSMIT); 813 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN); 814 return; 815 } 816 817 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 818 &hdata->connector, m); 819 if (!ret) 820 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); 821 if (ret > 0) { 822 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC); 823 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret); 824 } else { 825 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); 826 } 827 828 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, 829 &hdata->connector, m); 830 if (!ret) 831 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, 832 sizeof(buf)); 833 if (ret > 0) { 834 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC); 835 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3); 836 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3); 837 } 838 839 hdmi_audio_infoframe_apply(hdata); 840 } 841 842 static enum drm_connector_status hdmi_detect(struct drm_connector *connector, 843 bool force) 844 { 845 struct hdmi_context *hdata = connector_to_hdmi(connector); 846 847 if (gpiod_get_value(hdata->hpd_gpio)) 848 return connector_status_connected; 849 850 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); 851 return connector_status_disconnected; 852 } 853 854 static void hdmi_connector_destroy(struct drm_connector *connector) 855 { 856 struct hdmi_context *hdata = connector_to_hdmi(connector); 857 858 cec_notifier_conn_unregister(hdata->notifier); 859 860 drm_connector_unregister(connector); 861 drm_connector_cleanup(connector); 862 } 863 864 static const struct drm_connector_funcs hdmi_connector_funcs = { 865 .fill_modes = drm_helper_probe_single_connector_modes, 866 .detect = hdmi_detect, 867 .destroy = hdmi_connector_destroy, 868 .reset = drm_atomic_helper_connector_reset, 869 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 870 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 871 }; 872 873 static int hdmi_get_modes(struct drm_connector *connector) 874 { 875 struct hdmi_context *hdata = connector_to_hdmi(connector); 876 struct edid *edid; 877 int ret; 878 879 if (!hdata->ddc_adpt) 880 return -ENODEV; 881 882 edid = drm_get_edid(connector, hdata->ddc_adpt); 883 if (!edid) 884 return -ENODEV; 885 886 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); 887 DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n", 888 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"), 889 edid->width_cm, edid->height_cm); 890 891 drm_connector_update_edid_property(connector, edid); 892 cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid); 893 894 ret = drm_add_edid_modes(connector, edid); 895 896 kfree(edid); 897 898 return ret; 899 } 900 901 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) 902 { 903 const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs; 904 int i; 905 906 for (i = 0; i < confs->count; i++) 907 if (confs->data[i].pixel_clock == pixel_clock) 908 return i; 909 910 DRM_DEV_DEBUG_KMS(hdata->dev, "Could not find phy config for %d\n", 911 pixel_clock); 912 return -EINVAL; 913 } 914 915 static int hdmi_mode_valid(struct drm_connector *connector, 916 struct drm_display_mode *mode) 917 { 918 struct hdmi_context *hdata = connector_to_hdmi(connector); 919 int ret; 920 921 DRM_DEV_DEBUG_KMS(hdata->dev, 922 "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 923 mode->hdisplay, mode->vdisplay, mode->vrefresh, 924 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true : 925 false, mode->clock * 1000); 926 927 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000); 928 if (ret < 0) 929 return MODE_BAD; 930 931 return MODE_OK; 932 } 933 934 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { 935 .get_modes = hdmi_get_modes, 936 .mode_valid = hdmi_mode_valid, 937 }; 938 939 static int hdmi_create_connector(struct drm_encoder *encoder) 940 { 941 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 942 struct drm_connector *connector = &hdata->connector; 943 struct cec_connector_info conn_info; 944 int ret; 945 946 connector->interlace_allowed = true; 947 connector->polled = DRM_CONNECTOR_POLL_HPD; 948 949 ret = drm_connector_init_with_ddc(hdata->drm_dev, connector, 950 &hdmi_connector_funcs, 951 DRM_MODE_CONNECTOR_HDMIA, 952 hdata->ddc_adpt); 953 if (ret) { 954 DRM_DEV_ERROR(hdata->dev, 955 "Failed to initialize connector with drm\n"); 956 return ret; 957 } 958 959 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); 960 drm_connector_attach_encoder(connector, encoder); 961 962 if (hdata->bridge) { 963 ret = drm_bridge_attach(encoder, hdata->bridge, NULL); 964 if (ret) 965 DRM_DEV_ERROR(hdata->dev, "Failed to attach bridge\n"); 966 } 967 968 cec_fill_conn_info_from_drm(&conn_info, connector); 969 970 hdata->notifier = cec_notifier_conn_register(hdata->dev, NULL, 971 &conn_info); 972 if (!hdata->notifier) { 973 ret = -ENOMEM; 974 DRM_DEV_ERROR(hdata->dev, "Failed to allocate CEC notifier\n"); 975 } 976 977 return ret; 978 } 979 980 static bool hdmi_mode_fixup(struct drm_encoder *encoder, 981 const struct drm_display_mode *mode, 982 struct drm_display_mode *adjusted_mode) 983 { 984 struct drm_device *dev = encoder->dev; 985 struct drm_connector *connector; 986 struct drm_display_mode *m; 987 struct drm_connector_list_iter conn_iter; 988 int mode_ok; 989 990 drm_mode_set_crtcinfo(adjusted_mode, 0); 991 992 drm_connector_list_iter_begin(dev, &conn_iter); 993 drm_for_each_connector_iter(connector, &conn_iter) { 994 if (connector->encoder == encoder) 995 break; 996 } 997 if (connector) 998 drm_connector_get(connector); 999 drm_connector_list_iter_end(&conn_iter); 1000 1001 if (!connector) 1002 return true; 1003 1004 mode_ok = hdmi_mode_valid(connector, adjusted_mode); 1005 1006 if (mode_ok == MODE_OK) 1007 goto cleanup; 1008 1009 /* 1010 * Find the most suitable mode and copy it to adjusted_mode. 1011 */ 1012 list_for_each_entry(m, &connector->modes, head) { 1013 mode_ok = hdmi_mode_valid(connector, m); 1014 1015 if (mode_ok == MODE_OK) { 1016 DRM_INFO("desired mode doesn't exist so\n"); 1017 DRM_INFO("use the most suitable mode among modes.\n"); 1018 1019 DRM_DEV_DEBUG_KMS(dev->dev, 1020 "Adjusted Mode: [%d]x[%d] [%d]Hz\n", 1021 m->hdisplay, m->vdisplay, 1022 m->vrefresh); 1023 1024 drm_mode_copy(adjusted_mode, m); 1025 break; 1026 } 1027 } 1028 1029 cleanup: 1030 drm_connector_put(connector); 1031 1032 return true; 1033 } 1034 1035 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq) 1036 { 1037 u32 n, cts; 1038 1039 cts = (freq % 9) ? 27000 : 30000; 1040 n = 128 * freq / (27000000 / cts); 1041 1042 hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n); 1043 hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts); 1044 hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts); 1045 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); 1046 } 1047 1048 static void hdmi_audio_config(struct hdmi_context *hdata) 1049 { 1050 u32 bit_ch = 1; 1051 u32 data_num, val; 1052 int i; 1053 1054 switch (hdata->audio.params.sample_width) { 1055 case 20: 1056 data_num = 2; 1057 break; 1058 case 24: 1059 data_num = 3; 1060 break; 1061 default: 1062 data_num = 1; 1063 bit_ch = 0; 1064 break; 1065 } 1066 1067 hdmi_reg_acr(hdata, hdata->audio.params.sample_rate); 1068 1069 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE 1070 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE 1071 | HDMI_I2S_MUX_ENABLE); 1072 1073 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN 1074 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); 1075 1076 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); 1077 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); 1078 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); 1079 1080 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; 1081 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); 1082 1083 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */ 1084 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5) 1085 | HDMI_I2S_SEL_LRCK(6)); 1086 1087 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3) 1088 | HDMI_I2S_SEL_SDATA0(4)); 1089 1090 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1) 1091 | HDMI_I2S_SEL_SDATA2(2)); 1092 1093 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0)); 1094 1095 /* I2S_CON_1 & 2 */ 1096 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE 1097 | HDMI_I2S_L_CH_LOW_POL); 1098 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE 1099 | HDMI_I2S_SET_BIT_CH(bit_ch) 1100 | HDMI_I2S_SET_SDATA_BIT(data_num) 1101 | HDMI_I2S_BASIC_FORMAT); 1102 1103 /* Configuration of the audio channel status registers */ 1104 for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++) 1105 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i), 1106 hdata->audio.params.iec.status[i]); 1107 1108 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); 1109 } 1110 1111 static void hdmi_audio_control(struct hdmi_context *hdata) 1112 { 1113 bool enable = !hdata->audio.mute; 1114 1115 if (hdata->dvi_mode) 1116 return; 1117 1118 hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ? 1119 HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN); 1120 hdmi_reg_writemask(hdata, HDMI_CON_0, enable ? 1121 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); 1122 } 1123 1124 static void hdmi_start(struct hdmi_context *hdata, bool start) 1125 { 1126 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1127 u32 val = start ? HDMI_TG_EN : 0; 1128 1129 if (m->flags & DRM_MODE_FLAG_INTERLACE) 1130 val |= HDMI_FIELD_EN; 1131 1132 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); 1133 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN); 1134 } 1135 1136 static void hdmi_conf_init(struct hdmi_context *hdata) 1137 { 1138 /* disable HPD interrupts from HDMI IP block, use GPIO instead */ 1139 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL | 1140 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); 1141 1142 /* choose HDMI mode */ 1143 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1144 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); 1145 /* apply video pre-amble and guard band in HDMI mode only */ 1146 hdmi_reg_writeb(hdata, HDMI_CON_2, 0); 1147 /* disable bluescreen */ 1148 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); 1149 1150 if (hdata->dvi_mode) { 1151 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1152 HDMI_MODE_DVI_EN, HDMI_MODE_MASK); 1153 hdmi_reg_writeb(hdata, HDMI_CON_2, 1154 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS); 1155 } 1156 1157 if (hdata->drv_data->type == HDMI_TYPE13) { 1158 /* choose bluescreen (fecal) color */ 1159 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12); 1160 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34); 1161 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56); 1162 1163 /* enable AVI packet every vsync, fixes purple line problem */ 1164 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02); 1165 /* force RGB, look to CEA-861-D, table 7 for more detail */ 1166 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5); 1167 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5); 1168 1169 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02); 1170 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); 1171 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); 1172 } else { 1173 hdmi_reg_infoframes(hdata); 1174 1175 /* enable AVI packet every vsync, fixes purple line problem */ 1176 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5); 1177 } 1178 } 1179 1180 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata) 1181 { 1182 int tries; 1183 1184 for (tries = 0; tries < 10; ++tries) { 1185 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); 1186 1187 if (val & HDMI_PHY_STATUS_READY) { 1188 DRM_DEV_DEBUG_KMS(hdata->dev, 1189 "PLL stabilized after %d tries\n", 1190 tries); 1191 return; 1192 } 1193 usleep_range(10, 20); 1194 } 1195 1196 DRM_DEV_ERROR(hdata->dev, "PLL could not reach steady state\n"); 1197 } 1198 1199 static void hdmi_v13_mode_apply(struct hdmi_context *hdata) 1200 { 1201 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1202 unsigned int val; 1203 1204 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1205 hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3, 1206 (m->htotal << 12) | m->vtotal); 1207 1208 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 1209 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val); 1210 1211 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; 1212 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val); 1213 1214 val = (m->hsync_start - m->hdisplay - 2); 1215 val |= ((m->hsync_end - m->hdisplay - 2) << 10); 1216 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20; 1217 hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val); 1218 1219 /* 1220 * Quirk requirement for exynos HDMI IP design, 1221 * 2 pixels less than the actual calculation for hsync_start 1222 * and end. 1223 */ 1224 1225 /* Following values & calculations differ for different type of modes */ 1226 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1227 val = ((m->vsync_end - m->vdisplay) / 2); 1228 val |= ((m->vsync_start - m->vdisplay) / 2) << 12; 1229 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1230 1231 val = m->vtotal / 2; 1232 val |= ((m->vtotal - m->vdisplay) / 2) << 11; 1233 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1234 1235 val = (m->vtotal + 1236 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2; 1237 val |= m->vtotal << 11; 1238 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val); 1239 1240 val = ((m->vtotal / 2) + 7); 1241 val |= ((m->vtotal / 2) + 2) << 12; 1242 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val); 1243 1244 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1245 val |= ((m->htotal / 2) + 1246 (m->hsync_start - m->hdisplay)) << 12; 1247 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val); 1248 1249 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1250 (m->vtotal - m->vdisplay) / 2); 1251 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1252 1253 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249); 1254 } else { 1255 val = m->vtotal; 1256 val |= (m->vtotal - m->vdisplay) << 11; 1257 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1258 1259 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0); 1260 1261 val = (m->vsync_end - m->vdisplay); 1262 val |= ((m->vsync_start - m->vdisplay) << 12); 1263 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1264 1265 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001); 1266 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001); 1267 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1268 m->vtotal - m->vdisplay); 1269 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1270 } 1271 1272 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1273 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); 1274 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); 1275 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1276 } 1277 1278 static void hdmi_v14_mode_apply(struct hdmi_context *hdata) 1279 { 1280 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1281 struct drm_display_mode *am = 1282 &hdata->encoder.crtc->state->adjusted_mode; 1283 int hquirk = 0; 1284 1285 /* 1286 * In case video mode coming from CRTC differs from requested one HDMI 1287 * sometimes is able to almost properly perform conversion - only 1288 * first line is distorted. 1289 */ 1290 if ((m->vdisplay != am->vdisplay) && 1291 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366)) 1292 hquirk = 258; 1293 1294 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1295 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); 1296 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal); 1297 hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1, 1298 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0); 1299 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, 1300 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0); 1301 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, 1302 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); 1303 1304 /* 1305 * Quirk requirement for exynos 5 HDMI IP design, 1306 * 2 pixels less than the actual calculation for hsync_start 1307 * and end. 1308 */ 1309 1310 /* Following values & calculations differ for different type of modes */ 1311 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1312 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1313 (m->vsync_end - m->vdisplay) / 2); 1314 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1315 (m->vsync_start - m->vdisplay) / 2); 1316 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2); 1317 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1318 (m->vtotal - m->vdisplay) / 2); 1319 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 1320 m->vtotal - m->vdisplay / 2); 1321 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal); 1322 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 1323 (m->vtotal / 2) + 7); 1324 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 1325 (m->vtotal / 2) + 2); 1326 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 1327 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1328 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 1329 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1330 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1331 (m->vtotal - m->vdisplay) / 2); 1332 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1333 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 1334 m->vtotal - m->vdisplay / 2); 1335 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 1336 (m->vtotal / 2) + 1); 1337 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 1338 (m->vtotal / 2) + 1); 1339 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 1340 (m->vtotal / 2) + 1); 1341 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0); 1342 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0); 1343 } else { 1344 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1345 m->vsync_end - m->vdisplay); 1346 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1347 m->vsync_start - m->vdisplay); 1348 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal); 1349 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1350 m->vtotal - m->vdisplay); 1351 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff); 1352 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff); 1353 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff); 1354 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff); 1355 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff); 1356 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff); 1357 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1358 m->vtotal - m->vdisplay); 1359 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1360 } 1361 1362 hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2, 1363 m->hsync_start - m->hdisplay - 2); 1364 hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2, 1365 m->hsync_end - m->hdisplay - 2); 1366 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff); 1367 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff); 1368 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff); 1369 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff); 1370 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff); 1371 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff); 1372 hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff); 1373 hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff); 1374 hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff); 1375 hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff); 1376 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff); 1377 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff); 1378 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff); 1379 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff); 1380 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff); 1381 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff); 1382 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff); 1383 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff); 1384 1385 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1386 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, 1387 m->htotal - m->hdisplay - hquirk); 1388 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk); 1389 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1390 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1391 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1); 1392 } 1393 1394 static void hdmi_mode_apply(struct hdmi_context *hdata) 1395 { 1396 if (hdata->drv_data->type == HDMI_TYPE13) 1397 hdmi_v13_mode_apply(hdata); 1398 else 1399 hdmi_v14_mode_apply(hdata); 1400 1401 hdmi_start(hdata, true); 1402 } 1403 1404 static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1405 { 1406 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1); 1407 usleep_range(10000, 12000); 1408 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1); 1409 usleep_range(10000, 12000); 1410 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); 1411 usleep_range(10000, 12000); 1412 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); 1413 usleep_range(10000, 12000); 1414 } 1415 1416 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable) 1417 { 1418 u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET; 1419 1420 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1421 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE); 1422 } 1423 1424 static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1425 { 1426 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1427 int ret; 1428 const u8 *phy_conf; 1429 1430 ret = hdmi_find_phy_conf(hdata, m->clock * 1000); 1431 if (ret < 0) { 1432 DRM_DEV_ERROR(hdata->dev, "failed to find hdmiphy conf\n"); 1433 return; 1434 } 1435 phy_conf = hdata->drv_data->phy_confs.data[ret].conf; 1436 1437 hdmi_clk_set_parents(hdata, false); 1438 1439 hdmiphy_conf_reset(hdata); 1440 1441 hdmiphy_enable_mode_set(hdata, true); 1442 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32); 1443 if (ret) { 1444 DRM_DEV_ERROR(hdata->dev, "failed to configure hdmiphy\n"); 1445 return; 1446 } 1447 hdmiphy_enable_mode_set(hdata, false); 1448 hdmi_clk_set_parents(hdata, true); 1449 usleep_range(10000, 12000); 1450 hdmiphy_wait_for_pll(hdata); 1451 } 1452 1453 /* Should be called with hdata->mutex mutex held */ 1454 static void hdmi_conf_apply(struct hdmi_context *hdata) 1455 { 1456 hdmi_start(hdata, false); 1457 hdmi_conf_init(hdata); 1458 hdmi_audio_config(hdata); 1459 hdmi_mode_apply(hdata); 1460 hdmi_audio_control(hdata); 1461 } 1462 1463 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) 1464 { 1465 if (!hdata->sysreg) 1466 return; 1467 1468 regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY, 1469 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); 1470 } 1471 1472 /* Should be called with hdata->mutex mutex held. */ 1473 static void hdmiphy_enable(struct hdmi_context *hdata) 1474 { 1475 if (hdata->powered) 1476 return; 1477 1478 pm_runtime_get_sync(hdata->dev); 1479 1480 if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk)) 1481 DRM_DEV_DEBUG_KMS(hdata->dev, 1482 "failed to enable regulator bulk\n"); 1483 1484 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1485 PMU_HDMI_PHY_ENABLE_BIT, 1); 1486 1487 hdmi_set_refclk(hdata, true); 1488 1489 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN); 1490 1491 hdmiphy_conf_apply(hdata); 1492 1493 hdata->powered = true; 1494 } 1495 1496 /* Should be called with hdata->mutex mutex held. */ 1497 static void hdmiphy_disable(struct hdmi_context *hdata) 1498 { 1499 if (!hdata->powered) 1500 return; 1501 1502 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); 1503 1504 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); 1505 1506 hdmi_set_refclk(hdata, false); 1507 1508 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1509 PMU_HDMI_PHY_ENABLE_BIT, 0); 1510 1511 regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); 1512 1513 pm_runtime_put_sync(hdata->dev); 1514 1515 hdata->powered = false; 1516 } 1517 1518 static void hdmi_enable(struct drm_encoder *encoder) 1519 { 1520 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1521 1522 mutex_lock(&hdata->mutex); 1523 1524 hdmiphy_enable(hdata); 1525 hdmi_conf_apply(hdata); 1526 1527 mutex_unlock(&hdata->mutex); 1528 } 1529 1530 static void hdmi_disable(struct drm_encoder *encoder) 1531 { 1532 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1533 1534 mutex_lock(&hdata->mutex); 1535 1536 if (hdata->powered) { 1537 /* 1538 * The SFRs of VP and Mixer are updated by Vertical Sync of 1539 * Timing generator which is a part of HDMI so the sequence 1540 * to disable TV Subsystem should be as following, 1541 * VP -> Mixer -> HDMI 1542 * 1543 * To achieve such sequence HDMI is disabled together with 1544 * HDMI PHY, via pipe clock callback. 1545 */ 1546 mutex_unlock(&hdata->mutex); 1547 cancel_delayed_work(&hdata->hotplug_work); 1548 if (hdata->notifier) 1549 cec_notifier_phys_addr_invalidate(hdata->notifier); 1550 return; 1551 } 1552 1553 mutex_unlock(&hdata->mutex); 1554 } 1555 1556 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { 1557 .mode_fixup = hdmi_mode_fixup, 1558 .enable = hdmi_enable, 1559 .disable = hdmi_disable, 1560 }; 1561 1562 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = { 1563 .destroy = drm_encoder_cleanup, 1564 }; 1565 1566 static void hdmi_audio_shutdown(struct device *dev, void *data) 1567 { 1568 struct hdmi_context *hdata = dev_get_drvdata(dev); 1569 1570 mutex_lock(&hdata->mutex); 1571 1572 hdata->audio.mute = true; 1573 1574 if (hdata->powered) 1575 hdmi_audio_control(hdata); 1576 1577 mutex_unlock(&hdata->mutex); 1578 } 1579 1580 static int hdmi_audio_hw_params(struct device *dev, void *data, 1581 struct hdmi_codec_daifmt *daifmt, 1582 struct hdmi_codec_params *params) 1583 { 1584 struct hdmi_context *hdata = dev_get_drvdata(dev); 1585 1586 if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv || 1587 daifmt->frame_clk_inv || daifmt->bit_clk_master || 1588 daifmt->frame_clk_master) { 1589 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1590 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1591 daifmt->bit_clk_master, 1592 daifmt->frame_clk_master); 1593 return -EINVAL; 1594 } 1595 1596 mutex_lock(&hdata->mutex); 1597 1598 hdata->audio.params = *params; 1599 1600 if (hdata->powered) { 1601 hdmi_audio_config(hdata); 1602 hdmi_audio_infoframe_apply(hdata); 1603 } 1604 1605 mutex_unlock(&hdata->mutex); 1606 1607 return 0; 1608 } 1609 1610 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool mute) 1611 { 1612 struct hdmi_context *hdata = dev_get_drvdata(dev); 1613 1614 mutex_lock(&hdata->mutex); 1615 1616 hdata->audio.mute = mute; 1617 1618 if (hdata->powered) 1619 hdmi_audio_control(hdata); 1620 1621 mutex_unlock(&hdata->mutex); 1622 1623 return 0; 1624 } 1625 1626 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, 1627 size_t len) 1628 { 1629 struct hdmi_context *hdata = dev_get_drvdata(dev); 1630 struct drm_connector *connector = &hdata->connector; 1631 1632 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1633 1634 return 0; 1635 } 1636 1637 static const struct hdmi_codec_ops audio_codec_ops = { 1638 .hw_params = hdmi_audio_hw_params, 1639 .audio_shutdown = hdmi_audio_shutdown, 1640 .digital_mute = hdmi_audio_digital_mute, 1641 .get_eld = hdmi_audio_get_eld, 1642 }; 1643 1644 static int hdmi_register_audio_device(struct hdmi_context *hdata) 1645 { 1646 struct hdmi_codec_pdata codec_data = { 1647 .ops = &audio_codec_ops, 1648 .max_i2s_channels = 6, 1649 .i2s = 1, 1650 }; 1651 1652 hdata->audio.pdev = platform_device_register_data( 1653 hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1654 &codec_data, sizeof(codec_data)); 1655 1656 return PTR_ERR_OR_ZERO(hdata->audio.pdev); 1657 } 1658 1659 static void hdmi_hotplug_work_func(struct work_struct *work) 1660 { 1661 struct hdmi_context *hdata; 1662 1663 hdata = container_of(work, struct hdmi_context, hotplug_work.work); 1664 1665 if (hdata->drm_dev) 1666 drm_helper_hpd_irq_event(hdata->drm_dev); 1667 } 1668 1669 static irqreturn_t hdmi_irq_thread(int irq, void *arg) 1670 { 1671 struct hdmi_context *hdata = arg; 1672 1673 mod_delayed_work(system_wq, &hdata->hotplug_work, 1674 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); 1675 1676 return IRQ_HANDLED; 1677 } 1678 1679 static int hdmi_clks_get(struct hdmi_context *hdata, 1680 const struct string_array_spec *names, 1681 struct clk **clks) 1682 { 1683 struct device *dev = hdata->dev; 1684 int i; 1685 1686 for (i = 0; i < names->count; ++i) { 1687 struct clk *clk = devm_clk_get(dev, names->data[i]); 1688 1689 if (IS_ERR(clk)) { 1690 int ret = PTR_ERR(clk); 1691 1692 dev_err(dev, "Cannot get clock %s, %d\n", 1693 names->data[i], ret); 1694 1695 return ret; 1696 } 1697 1698 clks[i] = clk; 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int hdmi_clk_init(struct hdmi_context *hdata) 1705 { 1706 const struct hdmi_driver_data *drv_data = hdata->drv_data; 1707 int count = drv_data->clk_gates.count + drv_data->clk_muxes.count; 1708 struct device *dev = hdata->dev; 1709 struct clk **clks; 1710 int ret; 1711 1712 if (!count) 1713 return 0; 1714 1715 clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL); 1716 if (!clks) 1717 return -ENOMEM; 1718 1719 hdata->clk_gates = clks; 1720 hdata->clk_muxes = clks + drv_data->clk_gates.count; 1721 1722 ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates); 1723 if (ret) 1724 return ret; 1725 1726 return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes); 1727 } 1728 1729 1730 static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable) 1731 { 1732 struct hdmi_context *hdata = container_of(clk, struct hdmi_context, 1733 phy_clk); 1734 mutex_lock(&hdata->mutex); 1735 1736 if (enable) 1737 hdmiphy_enable(hdata); 1738 else 1739 hdmiphy_disable(hdata); 1740 1741 mutex_unlock(&hdata->mutex); 1742 } 1743 1744 static int hdmi_bridge_init(struct hdmi_context *hdata) 1745 { 1746 struct device *dev = hdata->dev; 1747 struct device_node *ep, *np; 1748 1749 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1); 1750 if (!ep) 1751 return 0; 1752 1753 np = of_graph_get_remote_port_parent(ep); 1754 of_node_put(ep); 1755 if (!np) { 1756 DRM_DEV_ERROR(dev, "failed to get remote port parent"); 1757 return -EINVAL; 1758 } 1759 1760 hdata->bridge = of_drm_find_bridge(np); 1761 of_node_put(np); 1762 1763 if (!hdata->bridge) 1764 return -EPROBE_DEFER; 1765 1766 return 0; 1767 } 1768 1769 static int hdmi_resources_init(struct hdmi_context *hdata) 1770 { 1771 struct device *dev = hdata->dev; 1772 int i, ret; 1773 1774 DRM_DEV_DEBUG_KMS(dev, "HDMI resource init\n"); 1775 1776 hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); 1777 if (IS_ERR(hdata->hpd_gpio)) { 1778 DRM_DEV_ERROR(dev, "cannot get hpd gpio property\n"); 1779 return PTR_ERR(hdata->hpd_gpio); 1780 } 1781 1782 hdata->irq = gpiod_to_irq(hdata->hpd_gpio); 1783 if (hdata->irq < 0) { 1784 DRM_DEV_ERROR(dev, "failed to get GPIO irq\n"); 1785 return hdata->irq; 1786 } 1787 1788 ret = hdmi_clk_init(hdata); 1789 if (ret) 1790 return ret; 1791 1792 ret = hdmi_clk_set_parents(hdata, false); 1793 if (ret) 1794 return ret; 1795 1796 for (i = 0; i < ARRAY_SIZE(supply); ++i) 1797 hdata->regul_bulk[i].supply = supply[i]; 1798 1799 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk); 1800 if (ret) { 1801 if (ret != -EPROBE_DEFER) 1802 DRM_DEV_ERROR(dev, "failed to get regulators\n"); 1803 return ret; 1804 } 1805 1806 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en"); 1807 1808 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) { 1809 if (IS_ERR(hdata->reg_hdmi_en)) 1810 return PTR_ERR(hdata->reg_hdmi_en); 1811 1812 ret = regulator_enable(hdata->reg_hdmi_en); 1813 if (ret) { 1814 DRM_DEV_ERROR(dev, 1815 "failed to enable hdmi-en regulator\n"); 1816 return ret; 1817 } 1818 } 1819 1820 return hdmi_bridge_init(hdata); 1821 } 1822 1823 static const struct of_device_id hdmi_match_types[] = { 1824 { 1825 .compatible = "samsung,exynos4210-hdmi", 1826 .data = &exynos4210_hdmi_driver_data, 1827 }, { 1828 .compatible = "samsung,exynos4212-hdmi", 1829 .data = &exynos4212_hdmi_driver_data, 1830 }, { 1831 .compatible = "samsung,exynos5420-hdmi", 1832 .data = &exynos5420_hdmi_driver_data, 1833 }, { 1834 .compatible = "samsung,exynos5433-hdmi", 1835 .data = &exynos5433_hdmi_driver_data, 1836 }, { 1837 /* end node */ 1838 } 1839 }; 1840 MODULE_DEVICE_TABLE (of, hdmi_match_types); 1841 1842 static int hdmi_bind(struct device *dev, struct device *master, void *data) 1843 { 1844 struct drm_device *drm_dev = data; 1845 struct hdmi_context *hdata = dev_get_drvdata(dev); 1846 struct drm_encoder *encoder = &hdata->encoder; 1847 struct exynos_drm_crtc *crtc; 1848 int ret; 1849 1850 hdata->drm_dev = drm_dev; 1851 1852 hdata->phy_clk.enable = hdmiphy_clk_enable; 1853 1854 drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs, 1855 DRM_MODE_ENCODER_TMDS, NULL); 1856 1857 drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs); 1858 1859 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI); 1860 if (ret < 0) 1861 return ret; 1862 1863 crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI); 1864 crtc->pipe_clk = &hdata->phy_clk; 1865 1866 ret = hdmi_create_connector(encoder); 1867 if (ret) { 1868 DRM_DEV_ERROR(dev, "failed to create connector ret = %d\n", 1869 ret); 1870 drm_encoder_cleanup(encoder); 1871 return ret; 1872 } 1873 1874 return 0; 1875 } 1876 1877 static void hdmi_unbind(struct device *dev, struct device *master, void *data) 1878 { 1879 } 1880 1881 static const struct component_ops hdmi_component_ops = { 1882 .bind = hdmi_bind, 1883 .unbind = hdmi_unbind, 1884 }; 1885 1886 static int hdmi_get_ddc_adapter(struct hdmi_context *hdata) 1887 { 1888 const char *compatible_str = "samsung,exynos4210-hdmiddc"; 1889 struct device_node *np; 1890 struct i2c_adapter *adpt; 1891 1892 np = of_find_compatible_node(NULL, NULL, compatible_str); 1893 if (np) 1894 np = of_get_next_parent(np); 1895 else 1896 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0); 1897 1898 if (!np) { 1899 DRM_DEV_ERROR(hdata->dev, 1900 "Failed to find ddc node in device tree\n"); 1901 return -ENODEV; 1902 } 1903 1904 adpt = of_find_i2c_adapter_by_node(np); 1905 of_node_put(np); 1906 1907 if (!adpt) { 1908 DRM_INFO("Failed to get ddc i2c adapter by node\n"); 1909 return -EPROBE_DEFER; 1910 } 1911 1912 hdata->ddc_adpt = adpt; 1913 1914 return 0; 1915 } 1916 1917 static int hdmi_get_phy_io(struct hdmi_context *hdata) 1918 { 1919 const char *compatible_str = "samsung,exynos4212-hdmiphy"; 1920 struct device_node *np; 1921 int ret = 0; 1922 1923 np = of_find_compatible_node(NULL, NULL, compatible_str); 1924 if (!np) { 1925 np = of_parse_phandle(hdata->dev->of_node, "phy", 0); 1926 if (!np) { 1927 DRM_DEV_ERROR(hdata->dev, 1928 "Failed to find hdmiphy node in device tree\n"); 1929 return -ENODEV; 1930 } 1931 } 1932 1933 if (hdata->drv_data->is_apb_phy) { 1934 hdata->regs_hdmiphy = of_iomap(np, 0); 1935 if (!hdata->regs_hdmiphy) { 1936 DRM_DEV_ERROR(hdata->dev, 1937 "failed to ioremap hdmi phy\n"); 1938 ret = -ENOMEM; 1939 goto out; 1940 } 1941 } else { 1942 hdata->hdmiphy_port = of_find_i2c_device_by_node(np); 1943 if (!hdata->hdmiphy_port) { 1944 DRM_INFO("Failed to get hdmi phy i2c client\n"); 1945 ret = -EPROBE_DEFER; 1946 goto out; 1947 } 1948 } 1949 1950 out: 1951 of_node_put(np); 1952 return ret; 1953 } 1954 1955 static int hdmi_probe(struct platform_device *pdev) 1956 { 1957 struct hdmi_audio_infoframe *audio_infoframe; 1958 struct device *dev = &pdev->dev; 1959 struct hdmi_context *hdata; 1960 struct resource *res; 1961 int ret; 1962 1963 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL); 1964 if (!hdata) 1965 return -ENOMEM; 1966 1967 hdata->drv_data = of_device_get_match_data(dev); 1968 1969 platform_set_drvdata(pdev, hdata); 1970 1971 hdata->dev = dev; 1972 1973 mutex_init(&hdata->mutex); 1974 1975 ret = hdmi_resources_init(hdata); 1976 if (ret) { 1977 if (ret != -EPROBE_DEFER) 1978 DRM_DEV_ERROR(dev, "hdmi_resources_init failed\n"); 1979 return ret; 1980 } 1981 1982 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1983 hdata->regs = devm_ioremap_resource(dev, res); 1984 if (IS_ERR(hdata->regs)) { 1985 ret = PTR_ERR(hdata->regs); 1986 return ret; 1987 } 1988 1989 ret = hdmi_get_ddc_adapter(hdata); 1990 if (ret) 1991 return ret; 1992 1993 ret = hdmi_get_phy_io(hdata); 1994 if (ret) 1995 goto err_ddc; 1996 1997 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func); 1998 1999 ret = devm_request_threaded_irq(dev, hdata->irq, NULL, 2000 hdmi_irq_thread, IRQF_TRIGGER_RISING | 2001 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2002 "hdmi", hdata); 2003 if (ret) { 2004 DRM_DEV_ERROR(dev, "failed to register hdmi interrupt\n"); 2005 goto err_hdmiphy; 2006 } 2007 2008 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 2009 "samsung,syscon-phandle"); 2010 if (IS_ERR(hdata->pmureg)) { 2011 DRM_DEV_ERROR(dev, "syscon regmap lookup failed.\n"); 2012 ret = -EPROBE_DEFER; 2013 goto err_hdmiphy; 2014 } 2015 2016 if (hdata->drv_data->has_sysreg) { 2017 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 2018 "samsung,sysreg-phandle"); 2019 if (IS_ERR(hdata->sysreg)) { 2020 DRM_DEV_ERROR(dev, "sysreg regmap lookup failed.\n"); 2021 ret = -EPROBE_DEFER; 2022 goto err_hdmiphy; 2023 } 2024 } 2025 2026 pm_runtime_enable(dev); 2027 2028 audio_infoframe = &hdata->audio.infoframe; 2029 hdmi_audio_infoframe_init(audio_infoframe); 2030 audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 2031 audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 2032 audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 2033 audio_infoframe->channels = 2; 2034 2035 ret = hdmi_register_audio_device(hdata); 2036 if (ret) 2037 goto err_rpm_disable; 2038 2039 ret = component_add(&pdev->dev, &hdmi_component_ops); 2040 if (ret) 2041 goto err_unregister_audio; 2042 2043 return ret; 2044 2045 err_unregister_audio: 2046 platform_device_unregister(hdata->audio.pdev); 2047 2048 err_rpm_disable: 2049 pm_runtime_disable(dev); 2050 2051 err_hdmiphy: 2052 if (hdata->hdmiphy_port) 2053 put_device(&hdata->hdmiphy_port->dev); 2054 if (hdata->regs_hdmiphy) 2055 iounmap(hdata->regs_hdmiphy); 2056 err_ddc: 2057 put_device(&hdata->ddc_adpt->dev); 2058 2059 return ret; 2060 } 2061 2062 static int hdmi_remove(struct platform_device *pdev) 2063 { 2064 struct hdmi_context *hdata = platform_get_drvdata(pdev); 2065 2066 cancel_delayed_work_sync(&hdata->hotplug_work); 2067 2068 component_del(&pdev->dev, &hdmi_component_ops); 2069 platform_device_unregister(hdata->audio.pdev); 2070 2071 pm_runtime_disable(&pdev->dev); 2072 2073 if (!IS_ERR(hdata->reg_hdmi_en)) 2074 regulator_disable(hdata->reg_hdmi_en); 2075 2076 if (hdata->hdmiphy_port) 2077 put_device(&hdata->hdmiphy_port->dev); 2078 2079 if (hdata->regs_hdmiphy) 2080 iounmap(hdata->regs_hdmiphy); 2081 2082 put_device(&hdata->ddc_adpt->dev); 2083 2084 mutex_destroy(&hdata->mutex); 2085 2086 return 0; 2087 } 2088 2089 static int __maybe_unused exynos_hdmi_suspend(struct device *dev) 2090 { 2091 struct hdmi_context *hdata = dev_get_drvdata(dev); 2092 2093 hdmi_clk_disable_gates(hdata); 2094 2095 return 0; 2096 } 2097 2098 static int __maybe_unused exynos_hdmi_resume(struct device *dev) 2099 { 2100 struct hdmi_context *hdata = dev_get_drvdata(dev); 2101 int ret; 2102 2103 ret = hdmi_clk_enable_gates(hdata); 2104 if (ret < 0) 2105 return ret; 2106 2107 return 0; 2108 } 2109 2110 static const struct dev_pm_ops exynos_hdmi_pm_ops = { 2111 SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL) 2112 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2113 pm_runtime_force_resume) 2114 }; 2115 2116 struct platform_driver hdmi_driver = { 2117 .probe = hdmi_probe, 2118 .remove = hdmi_remove, 2119 .driver = { 2120 .name = "exynos-hdmi", 2121 .owner = THIS_MODULE, 2122 .pm = &exynos_hdmi_pm_ops, 2123 .of_match_table = hdmi_match_types, 2124 }, 2125 }; 2126